ECTC Drop Impact Reliability Leadfree CSPs Presentation

8/14/2019 ECTC Drop Impact Reliability Leadfree CSPs Presentation

1/64

-1-Andrew Farris

Add CompanyLogo HereMay 27 30, 2008

58th ECTC, Lake Buena Vista, May 2730, 2008

Drop Test Reliability of Lead-free

Chip Scale Packages

Andrew Farris, Jianbiao Pan, Ph.D., Albert Liddicoat, Ph.D.California Polytechnic State University at San Luis Obispo

Brian J. Toleno, Ph.D., Dan Maslyk

Henkel Corporation

Dongkai Shangguan, Ph.D., Jasbir Bath, Dennis Willie,

David A. GeigerFlextronics International


2/64

-2-Andrew Farris


Agenda

IntroductionTest Vehicle Design and Assembly

Failure Detection Systems

Reliability DataFailure Analysis

Local Acceleration on Component Location

Conclusions


3/64

-3-Andrew Farris


Prior Work

Lead-free SnAgCu solders with various alloy additives(Syed 2006, Pandher 2007) and low-silver content (Lai

2005, Kim 2007) have been studied to improve drop

impact reliability of solder joints

Underfills (Zhang 2003, Toleno 2007) and cornerbonding (Tian 2005) have been used to improve drop

impact reliability


4/64

-4-Andrew Farris


Purpose of this Study

Compare the drop impact reliability of lead-free Chip

Scale Package (CSP) solder joints, as determined by

two different failure detection systems

In-situ data acquisition based dynamic resistance

measurement

Static post-drop resistance measurement

Determine the effects of edge bonding on CSP drop

impact performance

Further investigate the failure mechanisms of dropimpact failures in lead-free CSPs under JEDEC drop

impact test conditions


5/64

-5-Andrew Farris


Test Vehicle

JEDEC JESD22-B111 preferred board, 8-layer FR4,132 mm x 77 mm x 1mm, OSP finish

Amkor 12mm x 12mm CSPs, 228 I/Os, 0.5mm pitch,

SAC305 solder bumpsMulticore 318 LF 97SC (SAC305) solder paste


6/64

-6-Andrew Farris


Edge Bond Materials

Edge bonding 12mm CSPs Acrylated Urethane material

Cured by UV exposure for 80s using Zeta 7411 Lamp

Epoxy material

Thermally cured for 20min in 80 C oven

EpoxyAcrylic


7/64-7-

Andrew Farris



Compare two failure detection systems In-situ dynamic resistance measurement by data

acquisition (DAQ)

Uses voltage divider circuit to relate voltage to

resistance, and analog-to-digital conversion at 50kHz

Post-drop static resistance measurement

Single resistance measurement taken after the drop


8/64

-8-Andrew Farris


Failure Event

Display results plot: sampled voltage vs time

Intermittent Transitional failureObservable only during PWB bending

8


9/64

-9-Andrew Farris


Failure Event


Failure (temporary discontinuity)occurs during the PWB bending

Rcomp => as Vcomp => 5V

This failure is not as easily

detected after the test

9


10/64

-10-Andrew Farris



Failure Event

Complete Failure occurs when the daisy-chain has lost continuity even after the PWBvibration stops

10


11/64

-11-Andrew Farris


Test Vehicle Drop Orientation

Test vehicle is always mounted with componentsface down


12/64

-12-Andrew Farris





13/64

-13-Andrew Farris


Agenda





Conclusions


14/64

-14-Andrew Farris


Reliability Test Design

Two failure detection systemsThree acceleration conditions

Edge-bonded and not edge-bonded CSPs

Failure Detection DAQ System Post-Drop System

Edge-bonding Yes No Yes No

900 G 0.7 ms 0 3 0 3

1500 G 0.5 ms 4 3 4 3

2900 G 0.3 ms 4 1 4 0


15/64

-15-Andrew Farris


Component Locations

JEDEC defined component numbering Our DAQ cable always attaches near component 6, on the

short end of the board


16/64

-16-Andrew Farris


Table 2 - DAQ No Edge-bond


17/64


18/64

-18-Andrew Farris


Table 4 - DAQ with Edge-bond


19/64


20/64

-20-Andrew Farris


Agenda





Conclusions


21/64

-21-Andrew Farris


Cracks develop underneath the copper pads, allowingthe copper pad to lift away from the board

Cracking Under Pads (Cratering)


22/64

-22-Andrew Farris


Input/Output (I/O) traces that connect to the daisy-chain resistor were often broken

Many components had this broken trace and no other

identifiable failure

I/O Trace Failure

Board sideComponent side


23/64

-23-Andrew Farris


Cross-sectioned solder joint is shown to be crackednear the board side copper pad

Solder Fracture Failure


24/64

-24-Andrew Farris


Solder Fracture Failure

Cross-sectioned solder joint is shown to be crackednear the board side copper pad

Copper trace failure also shown (left side)


25/64

-25-Andrew Farris


Dye Stained Solder Fractures

Dye stained solder fractures were found Partial solder fracture (left) was not completely fractured

before the component was removed

Complete solder fracture (right) was fully fractured before

the component was removed


26/64

-26-Andrew Farris


I/O Trace and Daisy-chain Trace failures are bothcaused by pad cratering

Pad cratering was present on 88% of electrically

failed components, and is directly responsible for

69% of all electrical failures

Failure Mode Comparison


27/64

-27-Andrew Farris


Failures After 10 Drops (No EB)


28/64

-28-Andrew Farris


Failures After 14 Drops (No EB)


29/64

-29-Andrew Farris


Failures After 325 Drops (Epoxy EB)


30/64

-30-Andrew Farris


Failures After 279 Drops (Acrylic EB)


31/64

-31-Andrew Farris


Cable Influence on PWB Loading

Results from the comparison of failure detectionmethods

The DAQ system cable attached to the PWB appears to

effects loading conditions

Fewer components fell off the DAQ tested boards than

off the post-drop tested boards

The earliest component failure locations vary between

DAQ and post-drop tested boards


32/64

-32-Andrew Farris


Agenda





Conclusions


33/64

-33-Andrew Farris


Local Acceleration Conditions

AccelerometerAccelerometer

aboveabove

Component C8Component C8

AccelerometerAccelerometer

on Drop Tableon Drop Table

Testing the acceleration condition on the

board and table simultaneously


34/64

-34-Andrew Farris



Table baseplate has insignificant vibrationBoard vibrates over period longer than 10ms


35/64

-35-Andrew Farris


Component Locations

JEDEC defined component numbering The DAQ cable attaches near component C6 (in between

components C1 and C11)


36/64

-36-Andrew Farris


Blank PWB No Cable vs Cable

Symmetry of acceleration peaks has shifted (C7 vs C9)

Maximums greatly reduced by cable (C3, C13, C8)

1500G Input Acceleration


37/64

-37-Andrew Farris


Populated PWB No Edge Bond

Dampening due to the cable seems less significant than withblank PWB (both graphs are more similar)



38/64

-38-Andrew Farris


Epoxy Edge Bonded CSPs

Stiffer board with edge bonding has less symmetry disturbance

Overall accelerations are significantly reduced vs no edge-bond



39/64

-39-Andrew Farris


Acrylic Edge Bonded CSPs

Stiffer board with edge bonding has less symmetry disturbance

Overall accelerations are significantly reduced vs no edge-bond



40/64

-40-Andrew Farris


Conclusions

Edge bonding significantly increases the reliabilityof lead-free CSPs in drop impact conditions

Increased drops to failure between 5x to 8x

The reliability increase of the two edge bond materials

used did not differ significantly

The component location on the test vehicle has a

significant role in reliability


41/64

-41-Andrew Farris


Conclusions

Cohesive or adhesive failure between the PWBouter resin layer and the board fiberglass leads to

pad cratering

Pad cratering causes trace breakage that is the

most common electrical failure mode for this

specific lead-free test vehicle

Board laminate materials are the weakest link in

this lead-free test vehicle assembly, rather than thesolder joints


42/64

-42-Andrew Farris


Acknowledgements

Project Sponsors:

Office of Naval Research (ONR)

Through California Central Coast Research Park (C3RP)

Society of Manufacturing Engineers Education Foundation

Surface Mount Technology Association San Jose Chapter


43/64

-43-Andrew Farris



44/64

-44-Andrew Farris


Supplemental

Slides


45/64

-45-Andrew Farris


Drop Impact Reliability

Mobile electronic devices

Are prone to being dropped (or thrown)

Are important to our everyday activities

Are expected to just work even after rough handling


46/64

-46-Andrew Farris


Drop Test Reliability (cont.)

Mobile electronic devices also Are complicated and expensive

Are easily damaged by drop impacts

Are designed to be lightweight and portable

Drop test reliability is: The study of how well a device or part survives repeated

drop impacts

A process to determine where design improvements areneeded for future high reliability designs


47/64

-47-Andrew Farris


Drop Impact Reliability

Drop impact reliability testing evaluates thereliability of electronics when subjected to

mechanical shock

Shock causes PWB bending that results in mechanical

stress and strain in solder joints

Generally focused on lead-free solder usage in

consumer electronics (handheld products)

Due to governmental regulations pushing toward a lead-free market for these products


48/64

-48-Andrew Farris


SE300

SMT Assembly

DEK

Stencil

Printing

CyberOptic

Solder Paste

Inspection

Siemens F5

Placement

Heller Oven

EXL1800

Dedicated lead-free SMT assembly line


49/64

-49-Andrew Farris


SMT Assembly (cont.)

Stencil (DEK) 4 mil thick

Electro-Polish

12 mil square

Stencil Printing

Front/Rear Speed: 40 mm/s

Front/Rear Pressure: 12 kg

Squeegee length: 300mm Separation Speed: 10 mm/s


50/64

-50-Andrew Farris


Solder Reflow Profile


51/64

-51-Andrew Farris


X-Ray and SEM images after assembly showedround, uniform, and well collapsed solder joints

Solder Joint Integrity after Assembly


52/64

-52-Andrew Farris


Definition: Drop Impact Failure

Drop impact failure Occurs when the electrical connections in the device

are damaged so that it no longer functions as designed

Is typically detected by change of resistance or loss of

continuity in board level circuits May be either a permanent or intermittent condition


53/64

-53-Andrew Farris





54/64

-54-Andrew Farris



55/64

-55-Andrew Farris


Drop Impact Input Acceleration

e.g. 1500g - 0.5mse.g. 1500g - 0.5ms

or 2900g - 0.3msor 2900g - 0.3msLansmont MTS II Shock Tester

Typical Half-sine

Acceleration Pulse

V lt Di id Ci it


56/64

-56-Andrew Farris


Voltage Divider Circuit

Dynamic resistance measurement is achieved byusing a series voltage divider circuit to relate

voltage to resistance (Luan 2006)

RComp =VComp RStatic

VDC - VComp

VComp =VDC RCompRComp + RStatic

D t A i iti S t S


57/64

-57-Andrew Farris


Data Acquisition System Summary

DAQ system capabilities 17 channels (15 for the components, 1 each for power

supply voltage and trigger)

Sampling frequency of 50kHz per channel

Follows JEDEC standard recommendation

16 bit measurement accuracy (over 0-5V range)

Store entire data set for later analysis

Tab-separated-text (CSV) data value tables

PDF format graphs of each measured channel


58/64

P t D R i t M t


59/64

-59-Andrew Farris


Post-Drop Resistance Measurement

Advantage: No wires soldered to the test board, no interference

with board mechanics

Low cost system

Disadvantages:

Cannot test in-situ dynamic response (during board

deflection and vibration conditions)

Only one test per drop provides fairly poor resolution

for when failure occurs

Not easily automated (operator must take readings)


60/64

-60-Andrew Farris

Add Company

Logo HereMay 27 30, 2008

PWB Loading Conditions

JEDEC drop testing causes a complex PWB straincondition; not all solder joints experience the same

stress and strain

Reliability and failure analysis must consider

component location, drop count, and acceleration pulseprofile

(Image from JEDEC JESD22-B111)(Image from JEDEC JESD22-B111)


61/64

-61-Andrew Farris

Add Company


I/O Trace Failure Location

F il A l i


62/64

-62-Andrew Farris

Add Company


Failure Analysis

Cross-sectioning with SEM and optical microscopyDye penetrant method with optical microscopy

Dominant failure modes Trace fracture in board-side copper due to pad cratering

Solder fracture near board-side intermetallic layer

L l A l ti C diti


63/64

-63-Andrew Farris

Add Company



Using two accelerometers, the acceleration profileof the board at each component location was tested

Eight board variations

Blank PWB, Populated, with edge bond, and without

edge bond

With and without DAQ cable soldered into the board

C bl I fl A l ti


64/64

Cable Influence on Acceleration

Symmetry of acceleration/deflection/strain iseffected:

A cable soldered to the PWB will effect the test

conditions for any test vehicle assembly

Components cannot be grouped as liberally forreliability statistics if test conditions at their locations

are not similar

Lightest possible wire gauge should be used

But must provide reliable through-hole solder joints

ECTC Drop Impact Reliability Leadfree CSPs Presentation

Documents

Transcript of ECTC Drop Impact Reliability Leadfree CSPs Presentation