Sam PalermoAnalog & Mixed-Signal Center

Texas A&M University

ECEN689: Special Topics in High-Speed Links Circuits and Systems

Spring 2010

Lecture 16: Equalization Introduction

Announcements

• HW4 due Wednesday 5PM• Any issues?

• Exam 1 is March 12• 9:10-10:10AM (10 extra minutes)• Closed book w/ one standard note sheet

• 8.5”x11” front & back

• Bring your calculator

2

Agenda

• Equalization theory and circuits• Equalization overview• Equalization implementations

• TX FIR• RX FIR• RX CTLE• RX DFE

• Setting coefficients• Equalization effectiveness• Alternate/future approaches

3

High-Speed Electrical Link System

4

Link with Equalization

5

Seria

lizer

DTX[N:0]

TX Clk Generation

(PLL)

TX FIR Equalization

RX Clk Recovery

(CDR/Fwd Clk)

Σ

RX CTLE + DFE Equalization

Des

eria

lizer

DRX[N:0]

Channel

f

6

Channel Performance Impact

7

Channel Performance Impact

TX FIR Equalization

• TX FIR filter pre-distorts transmitted pulse in order to invert channel distortion at the cost of attenuated transmit signal (de-emphasis)

8

L

L L

L

L

L

L

L

L

1x 4x 2x 1x

1/4 1 1/2 1/4IDACs&

BiasControl

sgn-1 sgn0 sgn1 sgn2

50Ω

Out-P

Out-N

4:2MUX

2

2

2

21

D0

D1

D2

D3

VDDA=1.2VVDD=1.0V

VDDIO=1.0V

VDDA=1.2V

1

1

1

C2 (5GHz)From on-chip PLL

2

(2.5

Gb/

s)

(10Gb/s)

(5Gb/s)

ESD

L

L L

L

L

L

L

L

L

LL

LL LL

LL

LL

LL

LL

LL

LL

1x 4x 2x 1x

1/4 1 1/2 1/4IDACs&

BiasControl

sgn-1 sgn0 sgn1 sgn2

50Ω

Out-P

Out-N

4:2MUX

2

2

2

21

D0

D1

D2

D3

VDDA=1.2VVDD=1.0V

VDDIO=1.0V

VDDA=1.2V

1

1

1

C2 (5GHz)From on-chip PLL

2

(2.5

Gb/

s)

(10Gb/s)

(5Gb/s)

ESD

( ) ( ) ( ) ( ) ( )[ ]

−+−++= − 2

21010 2101TERM

outRDIDIDIDIV

“A Low Power 10Gb/s Serial Link Transmitter in 90-nm CMOS,” A. Rylyakov et al., CSICS 2005

6Gb/s TX FIR Equalization Example

• Pros• Simple to implement• Can cancel ISI in pre-

cursor and beyond filter span

• Doesn’t amplify noise• Can achieve 5-6bit

resolution

• Cons• Attenuates low

frequency content due to peak-power limitation

• Need a “back-channel” to tune filter taps

9

RX Equalization #1: RX FIR

• Pros• With sufficient dynamic range, can amplify

high frequency content (rather than attenuate low frequencies)

• Can cancel ISI in pre-cursor and beyond filter span

• Filter tap coefficients can be adaptively tuned without any back-channel

• Cons• Amplifies noise/crosstalk• Implementation of analog delays• Tap precision

10

w-1

z-1

x w0

z-1

x

z-1

x wn-1

z-1

wnx

Σ DEQ

Din

Analog Delay Elements

*

*D. Hernandez-Garduno and J. Silva-Martinez, “A CMOS 1Gb/s 5-Tap Transversal Equalizer based on 3rd-Order Delay Cells," ISSCC, 2007.

RX Equalization #2: RX CTLE

11

Din- Din+

Vo-Vo+

• Pros• Provides gain and

equalization with low power and area overhead

• Can cancel both pre-cursor and long-tail ISI

• Cons• Generally limited to 1st

order compensation• Amplifies noise/crosstalk• PVT sensitivity• Can be hard to tune

RX Equalization #3: RX DFE

12

z-1clk

Σ

x

w1

z-1x

w2

z-1x

wn-1

z-1x

wn

Din DRX

• Pros• No noise and crosstalk

amplification• Filter tap coefficients

can be adaptively tuned without any back-channel

• Cons• Cannot cancel pre-

cursor ISI• Critical feedback timing

path• Timing of ISI

subtraction complicates CDR phase detection

Equalization Effectiveness

• Some observations:• Big initial performance boost with 2-tap TX eq.• With only TX eq., not much difference between 2 to 4-tap• RX equalization, particularly DFE, allows for further performance

improvement• Caution – hard to build fast DFEs due to critical timing path

13

Incr

easi

ng

Equa

lizat

ion

Channel Responses

Next Time

• Equalization theory and circuits• Equalization implementations

• TX FIR• RX FIR• RX CTLE• RX DFE

• Setting coefficients• Equalization effectiveness• Alternate/future approaches

14