ECEN 248 Lab6_report

8/10/2019 ECEN 248 Lab6_report

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Lab 6: Introduction to Logic

Simulation and Verilog

Deanna Sessions

ECEN 248-511TA: Priya Venkatas

Date: October 16, 2013


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Objectives:The objective of this weeks lab is to gain familiarity with Verilog by describing simple circuitsin code that we have had to breadboard in previous labs. This includes learning the syntax of the

Verilog language, becoming acquainted with the Verilog software, and the proper way to

describe a basic circuit and target errors in pre-written code.

Design:Below are the five different source codes that were used during the lab with appropriate

comments notating what is happening in each step of the code. Each source code is run using apreviously written test bench source code that is downloaded and used to facilitate the creation

of a waveform diagram demonstrating the waveforms of the described circuit.

//two_one_mux`timescale 1 ns/ 1 psmodule two_one_mux(Y, A, B, S);

output wire Y; //declaring variables to be usedinput wire A, B, S;

wire notS; //declaring wireswire andA;wire andB;

not not0(notS, S); //declaring logic gates and what variables are used within themand and0(andA, notS,A);and and1(andB, S, B);or or0(Y, andA, andB);

endmodule //end of module

//four_bit_mux`timescale 1 ns/ 1 ps

`default_nettype none//connection 4 1-bit, 2:1 MUXs to create a 4-bit 2:1 MUXmodule four_bit_mux (Y, A, B, S);

input wire [3:0] A, B, Y; //A & B are 4-bit wide wiresinput wire S; //select

//instantiation of 4-bits through using the two_one_mux moduletwo_one_mux MUX0(Y[0], A[0], B[0], S);two_one_mux MUX1(Y[1], A[1], B[1], S);

two_one_mux MUX2(Y[2], A[2], B[2], S);two_one_mux MUX3(Y[3], A[3], B[3], S);

endmodule

//full_Adder`timescale 1 ns/ 1 ps`default_nettype none


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module full_adder(S, Cout, A, B, Cin);input wire A, B, Cin; //declare input and output variablesoutput wire S, Cout;

wire andBCin, andACin, andAB; //declaring 1-bit wires to be used

assign S = A ^ B ^ Cin; //XORedassign andAB = A & B; //ANDedassign andBCin = B & Cin; //AND for BCinassign andACin = A & Cin; //AND for ACinassign Cout = andAB | andBCin | andACin; //ORed all AND functions together together

endmodule

//add_sub

`timescale 1 ns/ 1 ps`default_nettype none

module add_sub (output wire [3:0] Sum, //declaring the outputs and inputs

output wire Overflow,input wire [3:0] opA, opB,input wire opSel );

wire [3:0] notB; //declaring wireswire c0, c1, c2, c3;

assign notB[0] = opB[0] ^ opSel; //XORing and assigning to a notB wireassign notB[1] = opB[1] ^ c0;assign notB[2] = opB[2] ^ c1;assign notB[3] = opB[3] ^ c2;

full_adder adder0(Sum[0], c0, opA[0], notB[0], opSel); //all of the full adders in the circuit

full_adder adder1(Sum[1], c1, opA[1], notB[1], c0);full_adder adder2(Sum[2], c2, opA[2], notB[2], c1);full_adder adder3(Sum[3], c3, opA[3], notB[3], c2);

assign Overflow = c2 ^ c3; //Overflow is carryouts 2 and 3 XORed

endmodule

//four_bit_alu`timescale 1 ns/ 1 ps`default_nettype none

module four_bit_alu( //defining the variables associated with this module

output wire [3:0] Result,output wire Overflow,input wire [3:0] opA, opB,/*crtl | operation** 00 | AND ** 01 | ADD ** 10 | AND ** 11 | SUB */input wire [1:0] ctrl);


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wire [3:0] tsum, tand; //defining temporary sum and AND blockswire tempover; //temporary overflow to be used in operations below

add_sub addsub(tsum, tempover, opA, opB, ctrl[1]); //calling the add_sub moduleassign tand = opA&opB; //defining what temporary AND is

assign Result[0] = (tsum[0] & ctrl[0])|(~ctrl[0] &tand[0]); //assigning answers to all different scenariosassign Result[1] = (tsum[1] & ctrl[0])|(~ctrl[0] &tand[1]); //using the sum, control, and AND resultsassign Result[2] = (tsum[2] & ctrl[0])|(~ctrl[0] &tand[2]);assign Result[3] = (tsum[3] & ctrl[0])|(~ctrl[0] &tand[3]);assign Overflow = tempover & ctrl[0];

endmodule

Results:The waveforms that resulted from each source code are shown below. These waveforms arecreated by running the Test bench code along with the above source code in order to produce a

visual representation of the timing within the described circuit.

Figure 6.1: 1-bit 2:1 Multiplexer waveform


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Figure 6.2: 4-bit 2:1 Multiplexer waveform

Figure 6.3: Full Adder waveform


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Figure 6.4: Addition Subtraction waveform

Figure 6.5: Four bit ALU waveform


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Conclusion:While this was a learning process, I successfully got all of my source code to work in a fairlypainless manner. The modules linked together and called previously created modules much like

the usage of a block diagram in regular circuit design so the lab built upon itself as it progressed.

Post- Lab Deliverables:

1. Source code can be found in the design section.2. Waveform screenshots can be found in the results section.3. My understanding of the two_one_mux_tb test bench source code is that it takes the code

that I have written and then puts it through a series of tests that ensure the circuit is

feasible and follows the rules that it is supposed to follow. If one test fails then the

circuited has been botched in one way or another and is in need of adjusting. The code

takes in the inputs and outputs then tests them against the predetermined set of inputs andoutputs that have been determined by the truth table for the circuit. An example of this

test is shown below:

{A, B, S} = {3'b100}; #10; passTest(Y, 1'b1, "Mux Test 5", passed);

The code above is part of the 8-piece set in the test bench source code. This particularpiece has the inputs shown in red where A=1, B=0, and S=0. The rest of the code dictates

a 10 ns time delay and then a function called passTest that is created earlier based on the

actual output and the expected output. In this case, Y is the actual output and 1b1 is theexpected output, if these two values match then this particular set of inputs is good

returns Mux Test 5 passed whereas if Y=0 instead of the expected output of 1 it would

return Mux Test 5 failed and this would require the code to be changed.4. Not all inputs are tested because that would imply that there would be hundreds of

outputs due to A and B both being four bit wires and requiring each possible set to be

tested, however it isnt necessary to test all inputs like that because only 16 sets of inputs

are needed to demonstrate that the circuit works the proper way in using the proper

pathways.5. a. There are advantages and disadvantages associated with both HDL design and bread-

boarding. Bread-boarding is very tangible way to see the connections being made in thecircuit and it is easy to physically see why something isnt working where in HDL a

semicolon can be missing and the entire thing doesnt work. However, in HDL it is much

easier to describe a complex circuit than it would be to build it on a breadboard. The

ALU is a prime example because that circuit was an absolute mess to build on abreadboard, but was fairly simple to describe in HDL because the circuit itself is not hard

to understand how inputs and outputs are supposed to flow they just happen to be very

confusing on a breadboard with wires and components everywhere. I certainly prefer

Verilog HDL design to bread-boarding in our more complex circuits.

b. Comparing schematics and HDL design is a little bit more difficult because I preferboth of them. The schematic is great for seeing the physical flow of a circuit and allows

for a greater understanding of the circuit at a gate level, but it can be confusing at times tolook at a schematic and know what it is trying to accomplish. On the opposite side of the

spectrum, HDL design doesnt have a very physical aspect to it, but it is concise and

(assuming comments are helpful and the code is organized) fairly easy to understand thethought process on what is happening in the circuit. Once again for these more complex


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circuits I have to say that I prefer HDL design because it is so much cleaner and easier to

organize in a way that allows for comprehension.

6. The structural approach is shown best in the 2:1 and 4:1 MUX source codes and thedataflow approach is demonstrated in the full adder source code. The dataflow is based

on function rather than just the structural elements and it uses operands to describe the

functions of the circuit instead of logic gates like the structural approach. The reason Iwould personally want to use structural over dataflow would be if I was given aschematic and told to describe it using Verilog because it would be very easy to just state

the gates and their inputs and outputs. Dataflow would be more useful if I were given a

circuit described by Boolean algebra or a truth table because that could be easily input

using Boolean operators.

Student Feedback:

1. I actually feel like I learned a lot about Verilog because the lab was set up in a way where

it was more of a tutorial with checkpoints along the way to make sure we understoodwhat the code was doing and we were able to insert our own parts into the code tocomplete it. There was not a single part in the lab where I felt lost, I did have some basic

questions to make sure I understood correctly, but the lab manual did a fantastic job of

making everything extremely clear. It was nice having a lab where it grew in complexity,

but was never too much to handle. The first part walked through all parts and then itslowly got sparser in instructions which really tested me on my ability to learn and

remember what I had just done. Bravo, ECEN 248 lab writers, bravo.

2. Extremely clear and genuinely informative in all parts of the lab manual.3. This lab manual is brilliant. Do not change a thing.

ECEN 248 Lab6_report

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