ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS...
Transcript of ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS...
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ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN
Week 8 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
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FINITE STATE MACHINE DESIGN PROCEDURE (Moore Machines)
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Overview
Design of systems that input flip flops and combinational logic
Specifications start with a word description Create a state table to indicate next states Convert next states and outputs to output and flip
flop input equations Reduce logic expressions using truth tables
Draw resulting circuits.
Lots of opportunities for interesting design
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Designing Finite State Machines
Specify the problem with words (e.g. Design a circuit that detects three
consecutive 1 inputs) Assign binary values to states Develop a state table Use K-maps to simplify expressions
Flip flop input equations and output equations
Create appropriate logic diagram Should include combinational logic and flip
flops
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Example: Detect 3 Consecutive 1 inputs
State S0 : zero 1s detected State S1 : one 1 detected State S2 : two 1s detected State S3 : three 1s detected
0
Note that each state has 2 output arrows Two bits needed to encode state
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State Table for Sequence Detector
Sequence of outputs, inputs, and flip flop states enumerated in state table
Present state indicates current value of flip flops
Next state indicates state after next rising clock edge
Output is output value on current clock edge
Present State
Next State
A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 1
Present Output Input
S0 = 00 S1 = 01
S2 = 10 S3 = 11
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Finding Expressions for Next State and Output Value Create K-map directly from state table (3 columns = 3 K-maps)
Minimize K-maps to find SOP representations
Separate circuit for each next state and output value
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Circuit for Consecutive 1s Detector
Note location of state flip flops
Output value (y) is function of state
This is a Moore machine.
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Concept of the State Machine Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
State Diagram
Symbolic State Transition Table
Encoded State Transition Table
Note: Present state and output are the same value Moore machine
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Concept of the State Machine Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
D FF Implementation
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
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Mealy and Moore Machines
Solution 1: (Mealy)
0/0
Even
Odd
1/1 1/0
0/1
0 Even
1 1
0
Reset [0]
Odd [1]
Output
Input Output
Input
Transition Arc
Output is dependent only on current state
O/P is dependent on current state and input in Mealy
Solution 2: (Moore)
Mealy Machine: Output is associated with the state transition - Appears before the state transition is completed (by the next clock pulse).
Moore Machine: Output is associated with the state - Appears after the state transition takes place.
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Vending Machine FSM
Deliver package of gum after 15 cents deposited
Single coin slot for dimes, nickels
No change
Design the FSM using combinational logic and flip flops
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Vending Machine FSM
Symbolic State Table
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Vending Machine FSM How many flip-flops are needed?
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Vending Machine FSM
K-map for Open K-map for D0 K-map for D1
Q1 Q0 D N
Q1
Q0
D N
Q1 Q0 D N
Q1
Q0
D N
Q1 Q0 D N
Q1
Q0
D N
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D Q
Q R
D Q
Q R
Q0
N
N
Q0
Q1 N
Q1 D
D0
D1 Q1
OPEN
D
CLK
CLK
Vending machine FSM implementation based on D flip-flops(Moore).
Q1
Q0
Reset
Reset
Minimized Implementation
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Summary
Finite state machines form the basis of many digital systems
Designs often start from clear specifications Develop state diagram and state table Optimize using combinational design techniques Mealy or Moore implementations possible
Can model approach using HDL.
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Counters
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Overview Counters are important components in computers
The increment or decrement by one in response to input
Two main types of counters Ripple (asynchronous) counters Synchronous counters
Ripple counters Flip flop output serves as a source for triggering other
flip flops
Synchronous counters All flip flops triggered by a clock signal
Synchronous counters are more widely used in industry.
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Shift Register Cascade chain of Flip-Flops Bits travel on Clock edges Serial in – Serial out, can also have parallel
load / read
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Binary Ripple Counter
Reset signal sets all outputs to 0
Count signal toggles output of low-order flip flop
Low-order flip flop provides trigger for adjacent flip flop
Not all flip flops change value simultaneously Lower-order flops change first
Focus on D flip flop implementation
Count
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Another Asynchronous Ripple Counter
° Similar to T flip-flop example on previous slide
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Asynchronous Counters Each FF output drives the CLK input of the next FF. FFs do not change states in exact synchronism with
the applied clock pulses. There is delay between the responses of successive
FFs. Ripple counter due to the way the FFs respond one
after another in a kind of rippling effect. A3 A2 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0
A1 0 0 1 1 0 0 0 0
A0 0 1 0 1 0 1 0 1
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Synchronous Counters
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Synchronous counters
Synchronous(parallel) counters All of the FFs are triggered
simultaneously by the clock input pulses.
All FFs change at same time
Remember If J=K=0, flop maintains value
If J=K=1, flop toggles
Most counters are synchronous in computer systems.
Can also be made from D flops
Value increments on positive edge
Note that low-order bit (A0) toggles on each clock cycle
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Synchronous UP/Down counters
Up/Down Counter can either count up or down on each clock cycle
Up counter counts from 0000 to 1111 and then changes back to 0000
Down counter counts from 1111 to 0000 and then back to 1111
Counter counts up or down each clock cycle
Output changes occur on clock rising edge
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Counters with Parallel Load
Counters with parallel load can have a preset value
Load signal indicates that data (I3…I0) should be loaded into the counter
Clear resets counter to all zeros
Carry output could be used for higher-order bits
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Counters with Parallel Load
Clear Clk Load Count Function 0 X X X Clear to 0 1 ↑ 1 X Load inputs 1 ↑ 0 1 Count 1 ↑ 0 0 No Change
Function Table
If Clear is asserted (0), the counter is cleared
If Load is asserted data inputs are loaded
If Count asserted counter value is incremented
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Binary Counter with Parallel Load and Asynchronous Preset
If PL’ = 0, load P into flops
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Binary Counter with Parallel Load and Preset
• Commercial version of binary counter