ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN
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Transcript of ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS
DESIGN
Lecture 7
Dr. Shi
Dept. of Electrical and Computer Engineering
BINARY ADDERS
Overview
Addition of binary data is fundamental Need to determine hardware implementation
Represent inputs and outputs Inputs: single bit values, carry in Outputs: Sum, Carry
Hardware features Create a single-bit adder and chain together
Dealing with overflow What happens if numbers are too big?
4-Bit Adder
Think top-down: How to break a problem into pieces?
Multiple-bit Addition
A3 A2 A1 A0
0 1 0 1A 0 1 1 1B3 B2 B1 B0
B
0 1 0 10 1 1 1
A
B
0
1
0
1
1
1
1
Ai
+Bi
Ci
Si
Ci+1
Consider single-bit adder for each bit position.
Each bit position creates a sum and carry
Full Adder
Block Diagram
Single-bit full adder, building block of large adders
Common piece of computer hardware
Full Adder
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Ci Ai Bi Si Ci+1
1 1
1 1
Ci
AiBi
00 01 11 10
0
1
Si
Full adder includes carry in Ci
Notice interesting pattern in Karnaugh map.
Full Adder
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Ci Ai Bi Si Ci+1
1
1 11
Ci
AiBi
00 01 11 10
0
1
Ci+1
Now consider implementation of carry outTwo outputs per full adder bit (Ci+1, Si)
Note: 3 inputs
Full Adder Implementation
A
B
S
C
C i+1
i
i
i
i
Si = Ci (Ai Bi)
Ci+1 = Ai · Bi + Ci · (Ai Bi)
Full Adder
A full adder can be made fromtwo half adders (plus an OR gate).
Hardware repetition simplifies hardware design
4-Bit Adder
C 1 1 1 0A 0 1 0 1B 0 1 1 1S 1 1 0 0
Chain single-bit adders together.What does this do to delay?
Half Adder (not very useful)
C A B S 0 0 0 1 A 0 B 0
S 0
C 1
0 0 0 00 1 1 01 0 1 01 1 0 1
Dec Binary
1 1+1 +1 2 10
Add two binary numbers
• A0 , B0 -> single bit inputs
• S0 -> single bit sum
• C1 -> carry out
Multiplexers
Multiplexers
Select an input value with one or more select bits
Use for transmitting data Allows for conditional transfer of data Sometimes called a mux
4– to– 1- Line Multiplexer
Quadruple 2–to–1-Line Multiplexer
Notice enable bitNotice select bit4 bit inputs
Multiplexer as combinational modules
Connect input variables to select inputs of multiplexer (n-1 for n variables)
Set data inputs to multiplexer equal to values of function for corresponding assignment of select variables
Using a variable at data inputs reduces the size of the multiplexer
Implementing a Four- Input Function with a Multiplexer
Multiplexers & Shannon Expansion
Shannon Expansion Theorem
The Shannon expansion develops the idea that Boolean functions can be reduced by means of the identity:
where F is any function and Fx and Fx' are Shannon cofactors of F.
Example
f = yz + xyz' + x'y'z
= yz(x' + x) + xyz' + x'y'z
= x'yz + xyz + xyz' + x'y'z
= x'(yz + y'z) + x(yz + yz')
= x'gx' + xgx
Expand about 2 variables
Multiplexer Implementation
DECODERS
Overview Binary decoders
Converts an n-bit code to a single active output Can be developed using AND/OR gates Can be used to implement logic circuits.
Binary encoders Converts one of 2n inputs to an n-bit output Useful for compressing data Can be developed using AND/OR gates
Both encoders and decoders are extensively used in digital systems
Binary Decoder
Black box with n input lines and 2n output lines
Only one output is a 1 for any given input
BinaryDecoder
ninputs 2n outputs
Enable
2-to-4 Binary Decoder2-to-4 Binary Decoder
From truth table, circuit for 2x4 decoder is:
Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY)
F0 = X'Y'E
F1 = X'YE
F2 = XY'E
F3 = XYE
X Y
Truth Table:
2-to-4Decoder
X
Y
F0
F1
F2
F3
Enable
Enable
Enable = 1
3-to-8 Binary Decoder3-to-8 Binary Decoder
x y z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1
F1 = x'y'zE
x zy
F0 = x'y'z’E
F2 = x'yz'E
F3 = x'yzE
F5 = xy'zE
F4 = xy'z'E
F6 = xyz'EF7 = xyzE
Truth Table:
3-to-8Decoder
X
Y
F0
F1
F2
F3
F4
F5
F6
F7
Z
Enable
Enable
Enable = 1
Implementing Functions Using Implementing Functions Using DecodersDecoders
Any n-variable logic function can be implemented using a single n-to-2n decoder to generate the minterms OR gate forms the sum. The output lines of the decoder corresponding to
the minterms of the function are used as inputs to the or gate.
Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder with m OR gates.
Suitable when a circuit has many outputs, and each output function is expressed with few minterms.
Example: Full adderS(x, y, z) = (1,2,4,7)
C(x, y, z) = (3,5,6,7)
3-to-8Decode
rS2
S1
S0
x
y
z
01234567
S
C
x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
Implementing Functions Using Implementing Functions Using DecodersDecoders
Enable
Enable = 1
Use two 3 to 8 decoders to make 4 to 16 decoder In this example, only one decoder
can be active at a time. x, y, z effectively select output line
for w
Encoders
Encoders
If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder. e.g. 2n-to-n
The simplest encoder is a 2n-to-n binary encoder One of 2n inputs = 1 Output is an n-bit binary number
.
.
.
.
.
.
2n
inputsn outputs
Binaryencoder
8-to-3 Binary Encoder8-to-3 Binary Encoder
At any one time, only one input line has a value of 1.
Inputs Outputs
I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0
1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1
I0
I1
I2
I3
I4
I5
I6
I7
y0 = I1 + I3 + I5 + I7
y1 = I2 + I3 + I6 + I7
y2 = I4 + I5 + I6 + I7
8-to-3 Priority Encoder8-to-3 Priority Encoder
• What if more than one input line has a value of 1?• Ignore “lower priority” inputs.• Idle indicates that no input is a 1.
Inputs Outputs
I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0 Idle
0 0 0 0 0 0 0 0 x x x 01 0 0 0 0 0 0 0 0 0 0 1X 1 0 0 0 0 0 0 0 0 1 1X X 1 0 0 0 0 0 0 1 0 1X X X 1 0 0 0 0 0 1 1 1X X X X 1 0 0 0 1 0 0 1X X X X X 1 0 0 1 0 1 1X X X X X X 1 0 1 1 0 1X X X X X X X 1 1 1 1 1
Priority Encoder (8 to 3 encoder)
Priority Encoder : H7=I7 (Highest Priority) H6=I6·I7’ H5=I5·I6’ ·I7’ H4=I4·I5’ ·I6’·I7’ H3=I3.I4’·I5’ ·I6’·I7’ H2=I2.I3’·I4’ ·I5’·I6’ ·I7’ H1=I1· I2’ ·I3’·I4’ · I5’·I6’ ·I7’ H0=I0·I1’ ·I2’·I3’ ·I4’ ·I5’ ·I6’ ·I7’ IDLE= I0’ ·I1’ · I2’ ·I3’ ·I4’ ·I5’ ·I6’ ·I7’
Inputs Outputs
I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0 Idle0 0 0 0 0 0 0 0 x x x 01 0 0 0 0 0 0 0 0 0 0 1X 1 0 0 0 0 0 0 0 0 1 1X X 1 0 0 0 0 0 0 1 0 1X X X 1 0 0 0 0 0 1 1 1X X X X 1 0 0 0 1 0 0 1X X X X X 1 0 0 1 0 1 1X X X X X X 1 0 1 1 0 1X X X X X X X 1 1 1 1 1
I1
I2
I3
I4
I5
I6
I0
I7
H1
H2
H3
H4
H5
H6
H0
H7
IDLE
Priority Encoder (8 to 3 encoder)
Assign priorities to the inputs When more than one input are asserted, the output generates
the code of the input with the highest priority Priority Encoder :
H7=I7 (Highest Priority) H6=I6·I7’ H5=I5·I6’ ·I7’ H4=I4·I5’ ·I6’·I7’ H3=I3.I4’·I5’ ·I6’·I7’ H2=I2.I3’·I4’ ·I5’·I6’ ·I7’ H1=I1· I2’ ·I3’·I4’ · I5’·I6’ ·I7’ H0=I0·I1’ ·I2’·I3’ ·I4’ ·I5’ ·I6’ ·I7’ IDLE= I0’ ·I1’ · I2’ ·I3’ ·I4’ ·I5’ ·I6’ ·I7’
Encoder Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7
Y1
Y2
Y0
IDLE
I1
I2
I3 Y1
Y2I4
I5
I6
I0
Y0
I7
Binary encoder Priority Circuit
I1
I2
I3
I4
I5
I6
I0
I7
H1
H2
H3
H4
H5
H6
H0
H7
IDLE
I1
I2
I3
I4
I5
I6
I0
I7
Priority encoder