Marist BrothersSecond Trinal ExaminationsNotre Dame of Kidapawan CollegeFebruary 2-5, 2015Second Semester, SY 2014-2015ECE323 - Logic Circuits and Switching Theory Kidapawan CityMar Lou P. Galinato, ECE, MEP

Name: _____________________________________Course/Yr: ____________________

TEST I. MULTIPLE CHOICE [60 PTS] Shade the letter of your choice to each item. Erasures are considered wrong.

[1] 2COVERAGE: Digital Arithmetic: Operations and Circuits; Counters and Registers

[1] What range of signed decimal values can be represented in 12 bits (including the sign bit)?[A] -128 to +127[B] -1023 to +1024[C] -2047 to +2048[D] -2048 to +2047

[2] How many bits are required to represent decimal values ranging from -50 to +50?[A] Five[B] Six [C] Seven[D] Eight

[3] What is the largest negative decimal value that can be represented by a two-byte number?[A] -32768[B] -32767[C] -32769[D] -32770

[4] Whenever the sum of two signed binary numbers has a sign bit of 1, the magnitude of the sum is in[A] 1s compliment form[B] 2s compliment form[C] Sign-magnitude form[D] Negation form

[5] How can arithmetic overflow be detected when signed numbers are being added?[A] By comparing the sign bit of the sum with the numbers of bits being added[B] By comparing the sign bit of the addend with the sign bits of the numbers being added[C] By comparing the sign bit of the sum with the sign bits of the numbers being added[D] None of the above

[6] How can you tell when a correction is needed in BCD addition?[A] The sum of at least one decimal digit position is lesser than 1001 (9)[B] The sum of at least one decimal digit position is greater than 1001 (9)[C] The sum of at least one decimal digit position is greater than 0110 (6)[D] The sum of at least one decimal digit position is lesser than 0110 (6)

[7] The following hex numbers represent positive values except?[A] 2F[B] 77EC[C] C000[D] 6D

[8] How many inputs does a full adder have? How many outputs?[A] Three, two respectively[B] Four, two respectively[C] Three, one respectively[D] Two, three respectively

[9] Determine the contents of the A register after the following sequence of operations: [A]=0000, [0110][B], [S][A], [1110][B], [S][A].[A] 1000[B] 0111[C] 0110[D] 0100

[10] How many 74HC283 chips are needed to add two 20-bit numbers?[A] Ten chips[B] Eight chips[C] Twenty chips[D] Five chips

[11] If a 74HC283 has a maximum propagation delay of 30 ns from C0 to C4, what will be the total propagation delay of a 32-bit adder constructed from 74HC283s?[A] 230 ns[B] 240 ns[C] 250 ns[D] 260 ns

[12] When the adder/subtractor circuit is used for subtraction, the ____ of the subtrahend appears at the input of the adder.[A] negation[B] magnitude[C] 1s complement[D] 2s complement

[13] How does the BCD adder circuit detects the need for a correction and executes it?[A] The correction logic detects a difference greater than 9 and then causes a 0111 to be added to the sum[B] The correction logic detects a sum greater than 9 and then causes a 0110 to be added to the sum[C] The correction logic detects a sum equal to 9 and then causes a 0101 to be subtracted to the sum[D] Either A or B

[14] How many 74HC382s are needed to add two 32-bit numbers?[A] Eight[B] Twelve[C] Four[D] Six

[15] What FF outputs should be connected to the clearing NAND gate to form a MOD-13 counter?[A] C, and B[B] D, and A[C] D, C, and A[D] D, C, and B

[16] What is the output frequency of a decade counter that is clocked from a 50-kHz signal?[A] 20 kHz[B] 15 kHz[C] 10 kHz[D] 5 kHz

[17] A 2-kHz clock signal is applied to of a 74LS293. What is the frequency at ?[A] 250 Hz[B] 260 Hz[C] 270 Hz[D] 280 Hz

[18] What is the MOD number of a 74HC4040 counter?[A] 4096[B] 4095[C] 1024[D] 1023

[19] What would the notation DIV64 mean on a counter symbol?[A] The counter only divides the frequency by 64.[B] The counter is MOD-64 only.[C] The counter is MOD-64 and divides the frequency by 64.[D] None of the above

[20] How does an asynchronous down-counter circuit differ from an up-counter circuit?[A] The inverted output of each LSB FF is connected to the CLK input of the MSB FF[B] The non-inverted output of each FF is connected to the CLK input of the following FF[C] The inverted output of each FF is connected to the CLK input of the following FF[D] Either A or B

[21] Why is it that ripple counters maximum frequency limitation decreases as more FFs are added to the ripple counter?[A] Each FF adds its propagation delay to the total counter delay in response to a clock pulse.[B] Ripple counter is also an asynchronous counter[C] Propagation delay of a FF is negligible to the total counter delay in response to a clock pulse.[D] Either B or C

[22] A certain J-K flip-flop has tpd=12 ns. What is the largest MOD counter that can be constructed from these FFs and still operate up to 10 MHz?[A] MOD-256[B] MOD-255[C] MOD-512[D] MOD-511

[23] What is the advantage of a synchronous counter over an asynchronous counter? What is the disadvantage?[A] Can operate without clock frequencies but more expensive circuitry[B] Can operate lower clock frequencies and more complex circuitry[C] Can operate at higher clock frequencies and more complex circuitry[D] Either A or C

[24] How many logic devices are required for a MOD-64 parallel counter?[A] Six FFs and four OR gates[B] Six FFs and four AND gates[C] Six FFs and four NAND gates[D] Six FFs and four XOR gates

[25] What logic signal drives the J, K inputs of the MSB flip-flop for the counter of [24]?[A] ABC[B] ABCD[C] ABCDE[D] ABCDEF

[26] What is the difference between asynchronous and synchronous presetting?[A] Asynchronous presetting is dependent of the clock input, while synchronous presetting occurs on the active edge of the clock signal[B] Asynchronous presetting is independent of the clock input, while synchronous presetting occurs on the active edge of the clock signal[C] Synchronous presetting is independent of the clock input, while asynchronous presetting occurs on the active edge of the clock signal[D] Either B or C

[27] Describe the function of the inputs and to .[A] When is pulsed HIGH, the counter is preset to 0000.[B] When is pulsed LOW, the counter is preset to the binary number present in inputs 0000[C] When is pulsed LOW, the counter is preset to the binary number present in inputs to [D] Either B or C

[28] What logic levels must be present at and in order for the 74LS193 to count pulses that appear at ?[A] 1, 0, 0 respectively[B] 0, 1, 0 respectively[C] 1, 1, 1 respectively[D] 1, 1, 0 respectively

[29] What would be the maximum counting range for a four-stage counter made up of 74LS193 ICs?[A] 0 to 65,536[B] 0 to 65,535[C] 0 to 65,524[D] 0 to 65,525

[30] Describe the function of the MR input[A] A HIGH at MR overrides all other input to reset the counter to 0000.[B] A LOW at MR overrides all other input to reset the counter to 0000.[C] A HIGH at MR overrides all other input to reset the counter to 1111.[D] A LOW at MR overrides all other input to reset the counter to 1111.

TEST II. DESIGN PROBLEMS (40 PTS)White your answer on provided newsprints.

[1] Design a parallel adder/subtractor circuit in the 2s complement system using 74LS283 (4-bit parallel adder), AND gates, OR gates, and D flip-flops.

[2] Design a BCD adder that contains two four-bit adders and a correction-detector circuit.

[3] Show how to wire the 74LS293 as a MOD-21 counter.

- NOTHING FOLLOWS -