ECE 3610 LAB BOOK Semester

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LAB 1

Asynchronous Receiver

OBJECTIVE: The student will become familiar with integrated design tools and how to use them to design a component of a digital system. The student will also gain experience with asynchronous serial communication. Complete the given code so the state machine takes correct path, create a test bench to assure it will work then pass of working version on board.

DIAGRAMS:

Hand drawn schematics and/or other higher level block diagrams will go here. You should draw schematics of major modules (e.g. receiver.vhd) if possible.

See the example below:

In the receiver we have three major components. The State-Register, timer, shift register. The state register was modeled after the mealy machine depicted in figure 2.

1Figure

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State machine diagram (include additional figures if you have more than one) will go here

See an example below:

VHDL CODES:

RECEIVER.VHD Code Will Go Here. You should include the most important modules in this section. You can also include test benches (optional).

Your comments and other notes can also be included: see the example below

DeBugging: When we first wrote the state machine we had a few syntax errors that we had to fix. The first one we found was that we wrote all of our elsif statements as else if is stead of elsif just meaning it wanted us to put two end if statements at the end of each statement so we changed that to clean the code up a little bit. The first being that all of our next_state statements were receiving present_state instead of stating the actual state it was supposed to go to or stay in. The next problem was the condition statements determining a change in state was that the AND combination was incorrect we were converting the value of the AND combination and setting “ if time_out and sdata = ‘0’ ” instead of checking both values which should have been either if time_out&sdata = “01” or (timeout = ‘0’ and sdata = ‘1’) THEN… it was never letting our state machine leave the first state because of the specific condition we gave.After correcting the syntax errors, conditional statements, and elsif statements we ran the test bench without a hiccup and as seen below in figure 1 are the results from our test bench. SIMULATION RESULTS:

MAIN SIMULATION RESULTS WILL GO HERE. SEE THE EXAMPLE BELOW:

Figure 2

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SUMMARY:

Here you can write more comments and summary of your experience

See the example below:

After fiddling with impact and programming the FPGA we were able to configure everything and then open Putty terminal emulator basically the means on which we could communicate from the computers keyboard to print on the boards LCD screen. This lab helped us better understand state machines and how to implement them into VHDL and using Putty to communicate with our board by means of a serial connection.

3Figure