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BUILDING BLOCKS OF A BASIC MICROPROCESSOR

Part 1PowerPoint Format of Lecture 3 of Book

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• Decoder• Tri-state device• Full adder, full subtractor• Arithmetic Logic Unit (ALU)• Multiplexer• Memories• Example showing how to write to a memory• Homework assignments

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• Recall concept of a decoder• Interpret as a “function code decoder”

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• In many digital systems it is required to connect multiple output devices onto the same wire or group of wires– Output device: Switch (outputs a voltage, which indicates the

state of the switch)– Input device: LED (requires an applied voltage to turn the light

on/off).

• Problem: What happens when two or more devices attempt to drive different voltages on the same wire (or group of wires, i.e., a bus)– Result: line (or bus) contention, damage to circuit.

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• For example, consider two devices Device A and Device B need to send voltages to Device C

• What would happen if A sent +5 V and B sent 0 V at the same time? – Line contention: it’s like Device A’s positive terminal power

supply is connected to ground with no resistance. Not good!

Device A Device B

Device C

Output DevicesVoltage Source

Input DeviceVoltage Sink

5V 5V

Common Ground

GND

5V

Effectively

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A SOLUTION: TRI-STATE BUFFER

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APPLICATION OF TRI-STATE BUFFER

• Only one device can output a voltage (0V or 5V) at one time.

• Therefore, the outputs of the Device A and B may be connected together, safely.

Device A Device B

Device C

Write Control

Active low tri-state buffer

Active high tri-state buffer

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• Context (an application of a full adder)– Two multi-bit numbers may be added

one column at a time, using a full adder circuit.

• Design of full adder

x y Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

1-bit Binary

Number Wheel

Add

1

Carry Axis0

Truth table

0 1 0 1

1 0 1 0

xyCin

001 11 10

1

00

S = x’yCin’ + xy’Cin’ + x’y’Cin + xyCin

S

0 0 1 0

0 1 1 1

xyCin

001 11 10

1

00

Cout = xy + xCin + YCin

Cout

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FULL ADDER

_ _ _ _ x _ _ _Number A

Number B

Carry In

_ _ _ _ y _ _ __ _ _ _ Cin _ _ _

0

1

1-bit BinaryNumberWheel

x y Cin Cout S

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 00 10 11 00 11 01 01 1

x

y

Cin

Cout

S = x y z + x y z + x y z + x y z

Sum _ _ _ _ S _ _ _

Carry Out _ _ _ _ Cout _ _ _

Cout = x y + x z + yz

Logical OR

From a Karnaugh map:

FA S

Truth Table

Full Adder Block Diagram

Add

x + y + Cin

Arithmetic Sum

We taught (designed) the

digital circuit how to add using the

1-bit number wheel.

Carry Axis

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_ _ _ _ x _ _ _Number A

Number B

Borrow In

_ _ _ _ y _ _ __ _ _ _ Bin _ _ _

0

1

1-bit BinaryNumberWheel

x y Bin Bout D

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 01 11 11 00 10 00 01 1

x

y

Bin

Bout

D = S = x y z + x y z + x y z + x y z

Difference _ _ _ _ D _ _ _

Borrow Out _ _ _ _ Bout _ _ _

Bout = x y + x z + yz

Logical OR

From a Karnaugh map:

FS D

Truth Table

Full Subtracter Block Diagram

Subtract

x - y - Bin

ArithmeticDifference

Cout = x y + x z + yz

We taught (designed) the

digital circuit how to subtract using the 1-bit number

wheel.

Carry (Borrow) Axis

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4-BIT FULL

ADDER

1 0 1 1Number A

Number B

Carry In

0

1

1-bit BinaryNumberWheel

Sum

Carry Out

FA

Add

Ci

Ai

Bi

Si

Ci+1

0 0 1 1

0

3 2 1 0i

B0 A0

C0

S0

C1FA

B1 A1

S1

C2FA

B2 A2

S2

C3FA

B3 A3

S3

C4

0000

1000

0001

0010

0011

0100

0101

0110

0111

1111

1110

1101

1100

1011

1010

1001

4-bit BinaryNumber wheel

Add

May be extended to n-bit full adder and corresponding n-bit number wheel.

Carry Axis

C4: Most Significant Carry Axis

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4-BITAND and OR CIRCUITS

• Other functions such as XOR, NAND, NOR, and NOT may be similarly implemented.

A3

B3

A2

B2

A1

B1

A0

B0

F3

F2

F1

F0

A3

B3

A2

B2

A1

B1

A0

B0

F3

F2

F1

F0

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4-BIT ARITHMETIC LOGIC UNIT (ALU)SIMPLIFIED FUNCTIONAL DESCRIPTION

4 FA 4 FS 4 AND 4 OR …

SWITCH (MUX)

A B MS3S2S1S0

FUNCTION SELECTORS

INPUTS

C B

F

OUTPUTS

Cout

TWO 4-BIT NUMBERS

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EXAMPLE4-BIT ALU FUNCTION TABLE

S3 S2 S1 S0 LOGICM=1

ARITHMETICM=0

0 0 0 0 A’ A

0 0 0 1 B’ B

0 0 1 0 A AND B A PLUS B

0 0 1 1 A OR B A MINUS B

0 1 0 0 A NAND B A + 1

0 1 0 1 A A - 1

0 1 1 0 B B + 1

0 1 1 1 A XOR B B - 1

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OPTIMIZED VERSION

CONTAINS 4-BIT FA AND LOGIC CIRCUITS AS ABOVE, BUTDOES NOT HAVE FS

ADD/SUBCONTROL

C0

A3 A2 A0A1

B3 B2 B0B1

R3 R2 R0R1

C3

PERFORMS 1S COMPLEMENT OF B WHEN ADD/SUB = 1

ADDS 1 TO OPERANDS WHEN ADD/SUB = 1

MOST SIGNIFICANT CARRY OR BORROW

A – B = A + 2s(B)

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• In this course, we do not use the optimized, 2’s complement ALU.– The optimized version does not contain a FS circuit.

• We use the non-optimized, basic ALU, which does contain a FS circuit.

• This means that in this course, the ALU has a FS circuit to perform subtraction.

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• 2-to-1 mux– Word size: 1-bit

2-1Mux

IN1

SIN2

OU1

• 2-to-1 mux– Word size: n-bit

2-1Mux

IN1

IN2

OU1

n

nn

S

• 4-to-2 mux– Word size: n-bit– Takes one n-bit input and

sends it to one or two outputs, or both outputs.

4-2Mux

OU1IN1

n

IN2n n

S1 S2S0

OU2n

IN4n

IN3n

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• There are three types of memories:

– Flip Flop (FF) (1-bit storage) and Latch• What is the difference between a Flip Flop and a Latch?

– Register (n-bit storage)

– Memory (m-words by n-bits of storage)

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……

…

…… …

…

m x n Memorym = 2k words

Each word has n-bits

n-1Word 0Word 1

Word 2k-1

0

p-bit registerp-1 0

Flip-flop (1-bit)

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MEMORY (SEQUENTIAL) CIRCUITS

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WAYS TO TRIGGER A FLIP FLOPLATCH FLIP FLOP

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REGISTER

• Can be designed as a group of flip flops• Example: 4-bit register, or a 4-bit word

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WRITING TO A REGISTER

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WRITING TO A REGISTER

Data InputD3D2D1D0 Valid

CLK (external)

WriteTimingDiagram

CLK (internal)

Q3Q2Q1Q0 Q3=D3,Q2=D2,Q1=D1,Q0=D0 Valid

OE (optional)

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READING FROM A REGISTER

• Note: other control designs are possible:– For example, R/W and OE could be input to a 2-input AND gate, whose output could be

connected to the Enable pins of the tri-state buffers.

OE

Q3Q2Q1Q0 O3O2O1O0 Valid

ReadTimingDiagram

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MEMORY

Address3-bit

Data4-bit Words

000 0 0 0 1

001 0 1 1 0

010 1 0 1 1

011 0 1 0 0

100 0 1 0 1

101 1 0 1 0

110 0 1 0 0

111 1 1 1 0

Example: 8 x 4 MemoryEight Words, and each word has 4-bits

A0

A1

D0

D1

R/Wn OE CS

8 x 4 Memory8 = 23 words, and each word has 4-bits

A2D2

D3

Block Diagram Representation

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m x n MEMORY

m by nMemory

A0

A1

Ak-2

Ak-1

.

.

.

D0

D1

Dn-1

OE CS

m x n Memorym = 2k words, and each word has n-bits

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WRITING TO MEMORY

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READING FROM MEMORY

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EXAMPLE: 4X3 MEMORY

Address2-bit

Data3-bit Words

00 0 0 0

01 0 1 1

10 1 0 1

11 0 1 0

Example: 4 x 3 MemoryFour Words, and each word has 3-bits

A0

A1

D0

D1

R/Wn OE CS

4 x 3 Memory4 = 22 words, and each word has 3-bits

D2

Block Diagram Representation

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BLOCKING AND ENABLING PROPERTY OF THEAND GATE

E

XY If E =1, then Y = X (Enable)

If E =0, then Y = 0 (Block)

E

CLKY If E = 1, then Y =

If E = 0, then Y = 0

Example Application: Clock Enable

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A1

A0

D0

D1

R/WnOE

CS

D2

Input data pins and output data pins are separated to simplify

the analysis.

Block Diagram

Schematic

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EXAMPLE

• Goal: Write 0b101 to location 0b10, i.e., write 5 to location 2.

• End result should be:

A0

A1

D0

D1

R/WnOE

CS

D21 0 1

When writing to (or reading from) a

memory (or register), the entire word is

accessed. For example, you cannot write to

just one bit of a word.When writing to (or

reading from) a memory, only one word may be accessed at a time. For example, you cannot write to two words at

the same time.

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Step 1: Setup data word: 0b101

101Data

Address

R/Wn

CS

At this point in time, the voltages (data) are applied to pins I2-I0.

1 0 1

00

‘0’ = 0 V ‘1’ = 5 V

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Step 1: Setup data word: 0b101

101Data

Address

1 0 1

R/Wn

CS

At this point in time, the voltages have flowed to the inputs of the FFs.

1 0 1

1 0 1

1 0 1

1 0 1

00

‘0’ = 0 V ‘1’ = 5 V

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Step 1: Setup data word: 0b101

101Data

Address

1 0 1

R/Wn

CS

Also at this point in time, the 0 V applied to pin CS has forced 0 V at the CLK inputs of the FFs.

1 0 1

1 0 1

1 0 1

1 0 1

00

‘0’ = 0 V ‘1’ = 5 V

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0 0

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Step 1: Setup data word: 0b101Step 2: Setup address: 0b10

101Data

Address

1 0 1

R/Wn

CS

At this point in time, the address applied to pins A1-A0 has flowed to the Word Select gates.

1 0 1

1 0 1

1 0 1

1 0 1

00

‘0’ = 0 V ‘1’ = 5 V

0

0

0

0

10

10

11

00

10

10

0

0

0

0

0

0

0

0

0

0

0 0

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Step 1: Setup data word: 0b101Step 2: Setup address: 0b10

101Data

Address

1 0 1

R/Wn

CS

Due to {A1A0} = {10}, Word 2 Select Line is the only active word select line.

1 0 1

1 0 1

1 0 1

1 0 1

00

‘0’ = 0 V ‘1’ = 5 V

0

0

0

0

10

10

111

00

10

10

0

0

0

0

0

0

0

0

0

0

0

0

0

0 0

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Step 1: Setup data word: 0b101Step 2: Setup address: 0b10Step 3: Select write mode

101Data

Address

1 0 1

R/Wn

CS

R/Wn is normally low (0), so write mode is selected.

1 0 1

1 0 1

1 0 1

1 0 1

00

‘0’ = 0 V ‘1’ = 5 V

0

0

0

0

10

10

111

00

10

10

0

0

0

0

0

0

0

0

0

0

0

0

0

0 0

1

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Step 1: Setup data word: 0b101Step 2: Setup address: 0b10Step 3: Select write modeStep 4: Trigger the circuit by making CS=1

Data

Address

1 0 1

R/Wn

CS

At this point in time, the Write gate at Word 2 becomes ‘1’.

1 0 1

1 0 1

1 0 1

1 0 1

10

‘0’ = 0 V ‘1’ = 5 V

1

1

1

1

10

111

00

10

10

0

0

0

0

0

0

101

10

10

0

0

0

0

0

0

0 0

1

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Step 1: Setup data word: 0b101Step 2: Setup address: 0b10Step 3: Select write modeStep 4: Trigger the circuit by making CS=1

Data

Address

1 0 1

R/Wn

CS

Also at this point in time, the CLK inputs to the FFs of Word 2 undergo a position transition.

1 0 1

1 0 1

1 0 1

1 0 1

10

‘0’ = 0 V ‘1’ = 5 V

1

1

1

1

10

111

00

10

10

0

0

0

0

0

1

0

101

10

11 1

0

0

0

0

0 0

1

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Step 1: Setup data word: 0b101Step 2: Setup address: 0b10Step 3: Select write modeStep 4: Trigger the circuit by making CS=1

Data

Address

1 0 1

R/Wn

CS

Also at this point in time, the data (101) is written into the FFs of Word 2.

1 0 1

1 0 1

1 0 1

1 0 1

10

‘0’ = 0 V ‘1’ = 5 V

1

1

1

1

10

111

00

10

10

0

0

0

0

0

0

101

10

1 0 11

11 1

0

0

0

0

0 0

1

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HOMEWORK: PERFORM A SIMILAR ANALYSIS FOR READ

• Show the incremental steps and timing diagram required to read the data located at memory location 0b10.

A0

A1

D0

D1

R/WnOE

CS

D21 0 1

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A BLANK MEMORY FOR

YOU

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HOMEWORK: PROBLEM STATEMENT

• Design a circuit that stores the 5-bit result of the last addition operation performed by a 4-bit full adder (FA) to an 8 words x 4-bit memory.

• Use an 8x4 memory that has similar control signals as the 4x3 memory given in the previous slides.

• Store the 5-bit result as follows:

– Step 1: store the MSb of the 5-bit result to Bit-0 of address 000 of the memory. Ensure that the other bits of address 000 are set to zero.

– Step 2: take the 4-bit output of the 4-bit FA circuit and store it at address 001 of the memory.

– Use a given clock signal to execute the above steps and write to the memory.

• Hint: Multiplexer and Counter.

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HOMEWORK: PROBLEM STATEMENT PICTORIALLY

CLK

F3F2F1F0

C

ALU

A0

A1

D0

D1

R/Wn OE CS

A2D2

D3

Your Circuit

0 0 0 CF3F2F1F0

DesiredResult

Given

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HOMEWORK: YOUR SOLUTION