ECE 353Introduction to Microprocessor Systems

Michael G. Morrow, P.E.

Week 8

Intel Information SessionWednesday, October 24th

4:00PM – 5:30PMMemorial Union, Refer to ‘TITU’ for

LocationEngineering students are invited to attend and learn about

exciting full-time and intern opportunities at Intel.

Refreshments will be provided.

Intel now accepts resumes online at: www.intel.com/jobs/resume

Casual attire is appropriate for all our campus events! We offer internships and full time positions in Washington,

Oregon, New Mexico, Arizona, Massachusetts, Colorado, and Northern and Southern California.

Intel Open Forum Mike Splinter, Intel Executive VPDirector of Sales and Marketing Friday, October 26th 11:30AM – 1:00PMUnion South, Refer to ‘TITU’ for Location

All Students invited to come and hear about Intel’s current direction and future strategies from a top leader within the company. Questions are encouraged!

Biography:

Mike is a graduate of the University of Wisconsin, earning both bachelor and master degrees in Electrical Engineering in 1972 and 1974, respectively.

Mike joined Intel in 1984 as a Fabrication Manager. He has held various management positions within the company, most notable as Assistant General Manager of the Technology Manufacturing Group and as Executive Vice President and General Manager of the Technology and Manufacturing Group. He was promoted to Senior Vice President in January 1999.

He holds two Rockwell patents: one for the quarter micron transistor process, and the other for microwave annealing of implanted junctions.

TopicsClock and reset generation.Bus timing.Bus signal de-multiplexing.System bufferingDetermine suitability of logic family interconnections.

System Diagram

80C188EB Package

Clock and ResetClock Generation Internal Oscillator External Oscillator Processor ClockReset Cold-start vs. warm-start RC reset circuit Microprocessor Supervisors

MAX807

Bus CyclesBasic Read Cycle Sequence DiagramBasic Write Cycle Sequence DiagramStates and PhasesBus Cycle State DiagramTypes of Bus Cycles S2:0 indicate the type of bus cycle in

progress.

Bus Cycles80C188EB Bus Cycle Timing Read Cycle Write CycleExercise: What type(s) of bus cycles are run? What address and data during each?001A BA 1000 mov dx, 1000h001D C7 07 1234 mov [bx], 1234h0021 8A 07 mov al, [bx]0023 EE out dx, al0024 ED in ax, dx

De-multiplexingMultiplexed Signal Timing Bus signal phasesRemote vs. Local De-multiplexingImplementation Devices / Connections Timing

Read Write

Fully-Buffered SystemAdvantages and DisadvantagesSignal Buffering Address bus Data bus

Transceivers Control signals

Control bus Contention issues

Terminology Local bus Buffered bus Partial buffering

Logic Family CompatibilityLogic family characteristics Definitions

DC noise margins Driver characteristics Receiver characteristics

Compatibility Voltage Current Exercises Capacitive loading TTL to CMOS

Wrapping UpHomework #4 due Friday, 10/26/2001

80C188EB Clock Generator

MAX807

Basic Read Cycle

Basic Write Cycle

Bus Cycle State Diagram

Bus Cycle Types

Read Cycle

Write Cycle

States & Phases

001A BA 1000 mov dx, 1000h

001D C7 07 1234 mov [bx], 1234h

0021 8A 07 mov al, [bx]

0023 EE out dx, al

0024 ED in ax, dx

Logic Compatibility Exercises

For the following logic families, determine compatibility, noise margins, and fan-out. 74ALS driving 74AC 74AC driving 74ALS

VOHmin VIHmin VOLmax VILmax IOHmax IIHmax IOLmax IILmax

74ALS

2.7V 2.0V 0.5V 0.8V -400uA +20uA +8.0mA

-200uA

74AC 4.9V3.76V

0.7*VCC 0.1V0.7V

0.3*VCC -50uA-24mA

+1uA +50uA+24mA

-1uA

Note: For 74AC, top line is with CMOS load, bottom line is with TTL load.