DUT

1

DUT

VDD

(1) Power Supply/Current Meter

What you need to test an IC ?

Idd

2

DUT

VDD

(2) Signal Generator


in

3

DUT

VDD

(3) Oscilloscope/Logic Analyzer


out

4

DUT

VDD

(4) Voltage Source/Current Meter


in

Iin

+Volt

_

I-meter

5

DUT

VDD

(5) Current Source/Voltage Meter


out

Vout

+Current

_

V-meter

6

Basic Request for IC Tester

Combine following function in Test Machine

(1) Power Supply/Current Meter (2) Signal Generator (3) Oscilloscope/Logic Analyzer (4) Voltage Source/Current Meter(5) Current Source/Voltage Meter

7

DUTout2

PowerDriver

in2

out1

in1

DPS

PinDriver

Comparator

PMU

PEC

PMU

V-SourceI-Meter

I-SourceV-Meter

8

PowerDriver

DPS

1. Provide device under test with operating power.

2. Power supply voltage can be programming. @2V, @4V, @8V, @10V Range

3. Ability for supply current measurement function. @1uA, @10uA, @100uA, @1mA, @10mA,@100mA, @1A Range

4. Four independent DPS source in System.

9

PinDriver

PEC

Comparator

1. Provide DUT with specified level stimulus signals.

2. Provide two rail comparators to capture output signal.

3. Stimulus/Capture are controlled by “Pat”, “TG”, “Format” and “Levels” . All are programmable to fit application.

4. 256 independent channels source in System.

10

PMU

1. Provide device pins with Voltage/Current source. And ability for Current/Voltage measurement. FVMI and FIMV mode.

2. Voltage Source/Measurement function. @2V, @4V, @8V, @10V Range

3. Current Source/Measurement function. @1uA, @10uA, @100uA, @1mA, @10mA,@100mA, @1A Range

4. Four independent PMU source in System.

V/I SourceI/V Meter

11

PLAN(cont); DISCONNECT(ALLPINS, PMU); DPS_FV(DPS1, 0.000nV, V1I6); SET_REF_LEVEL( OS_TEST_LVL ); SET_PIN_LOW( ALLPINS ); CONNECT(ALLPINS, DCL); WAIT(3ms); PMU_FIMV(ALLPINS, -100.000uA, V1I4, -1.000V, -200.000mV, 0.000ms, OFF, ON ); SET_FORMAT(INIT); DISCONNECT(ALLPINS, PMU);END_PLAN;

FORMAT_SET( OS_TEST ); ALLPINS = ( NRZ, NRZ, NORMAL);END_FS;

TIMING_SET( FASTCON, 20.00us ); ALLPINS = F( 0.00ns, 100.00ns ), IO( 0.00ns, 100.00ns ), STB( 19.00us, 19.5us );END_TS;

LEVEL_SET( OS_TEST_LVL ); ALLPINS = VIH(3.60 V), VIL( 0.0 V), VOH(-0.2 V), VOL(-1.0 V), IOH(200uA), IOL(200uA), VCM(-2.00 V);END_LS;

Open/Short(Continuity) Test

12

. . . . . . .

. . . . . . .

DCL

PMU

DCL

PMU

DCL

PMU

DCL

PMU

0.0V 0.0V

0.0V

VDD

IN_1

IN_2

OUT_1

OUT_2

GND

0.0V

Normal value= +0.6V(100uA)or -0.6V(-100uA)

DPS force 0.0V

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. . . . . . .

. . . . . . .

DCL

PMU

DCL

PMU

DCL

PMU

DCL

PMU

0.0V 0.0V

0.0V

VDD

IN_1

IN_2

OUT_1

OUT_2

GND

0.0V

Pin opened

Measured value= +2.5(100uA@V1)or -2.5(-100uA @V1)

DPS force 0.0V

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. . . . . . .

. . . . . . .

DCL

PMU

DCL

PMU

DCL

PMU

DCL

PMU

0.0V 0.0V

0.0V

VDD

IN_1

IN_2

OUT_1

OUT_2

GND

0.0V

Pin to pin short

Measured value = 0.0V

DPS force 0.0V

15

VIH

VIL

0/1

ON/OFF

VOL

VOH

VCC

GND

A B010101 HLHLHL

CMP_H

CMP_L

A B

0 11 0

/* AB */

* 0H *; * 1L *;

Truth table pattern

7404

Connect to DPS

Connect to GND

TPDhl TPDlh

A

B

Functional Test

DUT

16

What is Pattern ?

What is TG ?

What is FORMAT ?

What is Level ?

17

Pattern

• Pattern is the “truth table”.

Symbol Main information in the period0 Force 01 Force 1H Compare HighL Compare LowX No Drive / Don’t care outputZ No Drive / Compare Tri-stateO Force 0 + Compare Lowo Force 0 + Compare HighI Force 1 + Compare Highi Force 1 + Compare Low

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TG (timing Generator)

• FTG define the timing of input signal goes 1 and goes 0• IOTG define the timing of input signal turns on and off• STB define the timing to capture output signal

F

IO

STB

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Format

• Format is waveform type.

Format RemarkNRN Non Return to Zero ( Once goes 1, not back to 0 in period)RZ Return to zero ( Once goes 1, back to 0 later in period)

RTO Return To One (Once goes 0, back to 1 later in period)NXOR Surround by compliment @1

FH Static 1, not pattern controlledFL Static 0, not pattern controlled

• F- Format.(control goes 1/0)

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Format RemarkNRN Non Return to Zero ( Once drive on, not back to off in period)RZ Return to zero ( Once drive on, back to off later in period)

RTO Return To One (Once drive off, back to on later in period)NXOR Surround by compliment @2DON Driver always turns on , not pattern controlledDOFF Driver always turns off , not pattern controlled

• IO- Format.(control drive on/off)

Format Remark

NORMALFollow IO( IO turns on , load is off. IO turns off, load is on automatically)

LON Load always on , not pattern controlledLOFF Load always off , not pattern controlled

• L- Format.(control load on/off)

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D Q( D Flip-Flop )CLK

AND

NRZ Block

PAT

TG

PAT

TG

RZ Block

OR

XOR

RTO Block

PAT

TG

PAT

TG

NXOR Block

INV

INV

NRZ Out

RZ Out

RTO Out

NXOR Out

DFF. D = PATDFF. CLK = TGNRZ Out = DFF. Q

RZ Out = PAT TG

RTO Out = TG + PAT

NXOR Out = TG PAT

.

- Data bus- Addr bus

- Clock pin- Control pin(high active)

- Clock pin- Control pin(low active)

- Addr bus (access test)

Function Block Function Description Application

F and IO Format

22

PAT 0 1 1 0 0

TG

NRZ

RZ

RTO

NXOR

Combine Pattern, TG and Format

23

Level

Level RemarkVIH The voltage when pin driver goes 1 VIL The voltage when pin driver goes 0

VOH The High threshold voltage for of DUT outputVOL The low threshold voltage for of DUT outputIOH The current load when DUT output HighIOL The current load when DUT output Low

• Level defines the Input/Output DC level

VCM The communication voltage for Tri-State or switching IOH/IOL

24

NRZ

RZ

RTO

NXOR

MUX

F_PATF_TG

(Fixed High) 1

(Fixed Low) 0

F_CTRL

F_FORM_SEL 3

NRZ

RZ

RTO

NXOR

MUX

D_PATD_TG

(Drv On) 1

(Drv Off) 0

D_CTRL

D_FORM_SEL 3

Pin Drive

VIH

VIL

IO control

Transmission gate

(IO_TG)

(IO_FORM_SEL)

Pin Driver Block Diagram

25

VIH

VIL

Hi-Z

F_CTRL

D_CTRL

Strobe

Goes 1Goes 0

Drive off

Drive on

F_CTRL, D_CTRL and Level

26

VIHx

VILx

F_CTRLx

D_CTRLx

1

0

IOLx

IOHx

GND

L_CTRLx

VCMx

Comp

Comp

VOHx

VOLx

PEH_Px

PEL_Px

PMU

PE_PxDCL

(From reference buffer)





PEC Block Diagram -- Pin Electronics

D1 D2

(To Format/Response Chips)

(To Format/Response Chips)

(To Back plane connector,then to DUT via Flat Cable)

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*XXXXXXXXXX* TS = FASTCON;*Z000000000*;*0Z00000000*;*00Z0000000*;*000Z000000*;*0000Z00000*;*00000Z0000*;*000000Z000*;*0000000Z00*;*00000000Z0*;*000000000Z*;*XXXXXXXXXX* Halt;

PLAN(fast_con); DISCONNECT(ALLPINS, PMU); CONNECT(ALLPINS, DCL); SET_FORMAT(OS_TEST); SET_REF_LEVEL(OS_TEST_LVL); DPS_FV(DPS4, 0.000nV, V1I6); BURST_PATTERN(OS); SET_FORMAT(INIT); DISCONNECT(ALLPINS, PMU); END_PLAN;

FORMAT_SET( OS_TEST ); ALLPINS = ( NRZ, NRZ, NORMAL);END_FS;

TIMING_SET( FASTCON, 20.00us ); ALLPINS = F( 0.00ns, 100.00ns ), IO( 0.00ns, 100.00ns ), STB( 19.00us, 19.5us );END_TS;

LEVEL_SET( OS_TEST_LVL ); ALLPINS = VIH(3.60 V), VIL( 0.0 V), VOH(-0.2 V), VOL(-1.0 V), IOH(200uA), IOL(200uA), VCM(-2.00 V);END_LS;

Fast Continuity Test

28

DCL

DCL

VDD

IN_1

IN_2

GND

0.0V

100uA~200uA

100uA~200uA

VCM = 2.0V (-2.0V)

VOH = 1.0V (-0.2V)

VOL = 0.2V (-1.0V)

0.6V(-0.6V)

To Responseblock

To Responseblock

(compare Z)

1(1)

1(1)

DPS force 0.0V

29

DCL

DCL

VDD

IN_1

IN_2

GND

0.0V

100uA~200uA

100uA~200uA

VCM = 2.0V (-2.0V)

VOH = 1.0V (-0.2V)

VOL = 0.2V (-1.0V)

2.0V(-2.0V)

To Responseblock

To Responseblock

(compare Z)

0(1)

1(0)

DPS force 0.0V

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DCL

DCL

VDD

IN_1

IN_2

GND

0.0V

100uA~200uA

100uA~200uA

VCM = 2.0V (-2.0V)

VOH = 1.0V (-0.2V)

VOL = 0.2V (-1.0V)

0.0V(-0.0V)

To Responseblock

To Responseblock

(compare Z)

1(0)

0(1)

DPS force 0.0V

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D[0..7] Q[0..7]

74HC273

CLK

/CLR

D[0..7]

CLK

/CLR

Q[0..7]

1(F-RTO) /CLR(IO-NRZ)

(F-NRZ) D(IO-NRZ)

(F-NRZ) Q(output)(IO-NRZ)

(F-RZ) CLK(IO-NRZ)

A B C D

A B C D

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A[0..14] D[0..7]

62256

/OE

/WE

ADDR[0..14]

/OE

/WE

DATA[0..7]

1(F-NRZ) /OE(IO-NRZ)

(F-NRZ) ADDR(IO-NRZ)

(F-NRZ) DATA(input)(IO-NRZ)

(F-RTO) /WE(IO-NRZ)

A A+1 A+2 A+3

D(A) D(A+1) D(A+2) D(A+3)

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DB[0..11]

/CS

/WE

(F-NRZ) /CS(IO-NRZ)

(F-NRZ) DATA(input)(IO-NRZ)

(F-RTO) /WE(IO-NRZ)

D(0) D(1) D(2) D(3)

DB[0..11]

DAC Digital to Analog Converter

/CS/WE/LDAC

VOUT

/LDAC

(F-RTO) /LDAC(IO-NRZ)

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A[0..14] D[0..7]

62256

/OE

/WE

ADDR[0..14]

/OE

/WE

DATA[0..7]

0(F-NRZ) /OE(IO-NRZ)

(F-NXOR) ADDR(IO-NRZ)

(F-NRZ) DATA(output)(IO-NRZ)

(F-NRZ) /WE(IO-NRZ)

A1 A1A1 A2 A2A2 A3 A3

D(A1) D(A1)D(A1) D(A2) D(A2) D(A3)D(A2)

1

access time

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A[0..7] B[0..7]

74HC245

/G

DIR

A[0..7]

/GATE

DIR

B[0..7]

1(F-NRZ) /GATE

(F-NRZ) A(IO-RZ)

(F-NRZ) B(IO-RZ)

(RZ) DIR

A B

A B

A IO_TG

B IO_TG

A B

A B

A B

A B

A B

A B

A

A

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How to check if the pull-high resistor exist.

37

DCL

DCL

VDD

IN_1

IN_2

GND

DPS FV=VDD

Pull high resistor = Ry

Pull high resistor = Rx

VIH = VDD + Vy

VIL

VIH = VDD + Vx

VIL

Ix = Vx/Rx

Iy = Vy/Ry

ISB = ISBexp - (Vx/Rx) - (Vy/Ry)

Note : Vx,Vy might be +/-20 mV deviation if Rx,Ry are 20K Ohm, ISB will have 1uA/pin deviation

38

DCL

DCL

VDD

IN_1

IN_2

GND

DPS FV=VDD



VIH = VDD + Vy

VIL

VIH = VDD + Vx

VIL

Ix = 0

Iy = 0

ISB = ISBexp

Note : Vx,Vy might be +/-20 mV deviation

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PMU

PMU

VDD

IN_1

IN_2

GND

DPS FV=VDD



Rx ~= V_drop/Ix

Ry ~= V_drop/Iy

PMU FV = VDD - V_drop

PMU FV = VDD - V_drop

Ix

Iy

Check pull-high resistor by PMU_FVMI to get current value.Set PMU force value to be a little voltage drop(ex. 0.1 or 0.5V)lower than VDD. Pull-high resistance can be roughly calculatedby Voltage_drop/Current_value.

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PATTERN( Demo, Header1, F_Fumc); *000111XXXXXXXXXX* TS= TS1; *000111XXXHLHLXXX*; *000111XXXHLHLXXX*; *000111XXXHLHLXXX*; *000111XXXHLHLXXX*; *000111XXXHLHLXXX* Halt;END_PATTERN;

PLAN( Low_Func); . . BURST_PATTERN(Demo); . . END_PLAN;

PATTERN( Demo, Header1); *000111XXXXXXXXXX* TS= TS1; *000111XXXHLHLXXX*; *000111XXXHLHLXXX*; *000111XXXHLHLXXX*; *000111XXXHLHLXXX*; *000111XXXHLHLXXX* Halt;END_PATTERN;

PLAN( Low_Func); . . SET_FORMAT(F_Func); BURST_PATTERN(Demo); . . END_PLAN;

Better one

DUT

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Transcript of DUT