DSI Division of Integrated Systems Design Functional Verification Environments Development Goals Our...
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DSI Division of Integrated Systems Design Functional Verification Environments Development Goals Our main goals are in the field of developing modular verification environments that support module, cluster, chip and system level verification. Research and development done by our engineers will enhance your SoC verification by including the capability of re-running the process as the design specifications are updated just by performing some simple changes in the interfaces or by adding new functionality features. We facilitate fast verification tasks by mapping flexible verification environments into hardware using emulation solutions in order to support prototype testing at the final stage of the design. Verification solutions Modular Environment Module, cluster, chip & system levels Adaptive solution to spec changes Hierarchical and easy to apply Independence and compatibility with commercial simulators Module to System level verification Corner Case Verification Mode Verification of the deterministic knowledge of the circuit Special cases checking Assertion rules extracted from RTL Wide C++ Class Library for ad-hoc Development Verification measurement confidence Path, toggle and fault coverage metrics Embedded counters of equivalent and undetectable faults due to reconvergence fanout Pattern Generation: Random generators Statistical analysis General-purpose objects and application specific data types Modular environments Co-verification Emulation Hw/Sw modeling Performance analysis Verilog, e- language, VHDL, SystemC… Pattern generators Prototypes testing Integrated Systems for Broadband Communications Challenges in today’s SoC (System-on-Chip) design need robust system verification environments which ensure the correctness at every design level (module, cluster, chip and/or system level). Verification represents much of the success in a commercial product, and failures detection at early stages in the design flow permits a good price reduction. However, writing adhoc testbenches is tedious, unproductive and its reusability is low. DSI provides high performance software and hardware solutions to face current system verification processes and collaborates with your design engineers in order to diminish time-to-market requirements. Proven experience in: - - - - Automatic Verification based on Rules Pattern generation driven by coverage metrics Circuit behavior provided by high level reference models Verilog, e-language, VHDL or SystemC integration
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Transcript of DSI Division of Integrated Systems Design Functional Verification Environments Development Goals Our...
DSIDivision of Integrated Systems Design
Functional Verification Environments Development
Goals
Our main goals are in the field of developing modular verification environments that support module, cluster, chip and system level verification. Research and development done by our engineers will enhance your SoC verification by including the capability of re-running the process as the design specifications are updated just by performing some simple changes in the interfaces or by adding new functionality features. We facilitate fast verification tasks by mapping flexible verification environments into hardware using emulation solutions in order to support prototype testing at the final stage of the design.
Verification solutions
Modular Environment Module, cluster, chip & system levels Adaptive solution to spec changes Hierarchical and easy to apply Independence and compatibility with commercial simulators
Module to System level verification
Corner Case Verification Mode Verification of the deterministic knowledge of the circuit Special cases checking Assertion rules extracted from RTL
Wide C++ Class Library for ad-hoc Development Verification measurement confidence
Path, toggle and fault coverage metricsEmbedded counters of equivalent and undetectable faults due to reconvergence fanout
Pattern Generation:Random generatorsStatistical analysis
General-purpose objects and application specific data types
Modular environments
Co-verification
Emulation
Hw/Sw modeling
Performance analysis
Verilog, e-language,VHDL, SystemC…
Pattern generators
Prototypes testing
Integrated Systems for Broadband Communications
Challenges in today’s SoC (System-on-Chip) design need robust system verification environments which ensure the correctness at every design level (module, cluster, chip and/or system level). Verification represents much of the success in a commercial product, and failures detection at early stages in the design flow permits a good price reduction. However, writing adhoc testbenches is tedious, unproductive and its reusability is low. DSI provides high performance software and hardware solutions to face current system verification processes and collaborates with your design engineers in order to diminish time-to-market requirements.
Proven experience in:
--
--
Automatic Verification based on Rules Pattern generation driven by coverage metrics Circuit behavior provided by high level reference models
Verilog, e-language, VHDL or SystemC integration
DSIDivision of Integrated Systems Design
Functional Verification Environments Development
Emulation based solutions
Main measurement resources 1.4 GHz Logic analyzer and IC temp. tester (-100 to + 250ºC) 20 GHz TDR oscilloscope and spectrum analyzer VXI system for ATM analysis and BER measurements (2.7 GHz)
Test service
Functional Test by Emulation DSI provides emulation based solutions to speed up the functional verification. The DUV (Device Under Verification) and several functional verification modules are emulated into our VSTATION while corner cases are executed in hardware. Unimplemented blocks are simulated by using the reference model.
Performance AnalysisFunctionality and performance are checked in short times increasing the verification speed with emulation.
Prototype Testing Physical access layer replaced to interface with the physical device Full test support from the modular verification environment Framework reusability at the test stage
Hw/Sw Modeling and Co-VerificationSystem level validation and software verification are run into a mixed Hw/Sw co-debug environment at early stages.
About DSIThe Division of Integrated Systems Design is composed of experienced researchers who are developing commercial products and doing outstanding private and public research in the field of microelectronics since late 80s. The strength of the team is based on its know-how, cutting-edge resources and a set of services which permit to fulfill your company requirements, increasing its competitiveness and international position in new challenging markets.
For more information on DSI’s Integrated Systems for Functional Verification, please contact:
© 2004 Division of Integrated Systems Design
IUMAUniversidad de Las Palmas de Gran CanariaCampus Universitario de TafiraLas Palmas de Gran Canaria, SPAINTel: +34 928451232 (direct) +34 928451250 (reception desk)Fax: +34 928451243URL: www.iuma.ulpgc.es
