Documentation 122

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1.2 Some background on AES :

In 1995 the US #ational Instit!te of Standards and echnology p!t o!t a call for candidates

for a replacement for the ageing 6ata Encryption Standard 6ES% 13 candidates &ere accepted

for f!rther consideration and after a f!lly p!"lic process and three open international

conferences the n!m"er of candidates &as red!ced to five% In Fe"r!ary 2$$1 the final candidate

&as anno!nced and comments &ere solicited% 21 organi.ations and individ!als s!"mitted

comments% #one had any reservations a"o!t the s!ggested algorithm%

AES is fo!nded on solid and &ell/p!"lished mathematical gro!nd and appears to resist all

+no&n attac+s &ell% here7s a strong indication that in fact no "ac+/door or +no&n &ea+ness

e,ists since it has "een p!"lished for a long time has "een the s!"8ect of intense scr!tiny "y

researchers all over the &orld and s!ch enormo!s amo!nts of economic val!e and information is

already s!ccessf!lly protected "y AES% here are no !n+no&n factors in its design and it &as

developed "y *elgian researchers in *elgi!m therefore voiding the conspiracy theories

sometimes voiced concerning an encryption standard developed "y a United States government

agency% A strong encryption algorithm need only meet only single main criteria

here m!st "e no &ay to find the !nencrypted clear te,t if the +ey is !n+no&n e,cept

"r!te force i%e% to try all possi"le +eys !ntil the right one is fo!nd%

A secondary criterion m!st also "e met

he n!m"er of possi"le +eys m!st "e so large that it is comp!tationally infeasi"le to

act!ally stage a s!ccessf!l "r!te force attac+ in short eno!gh a time%

he older standard 6ES or 6ata Encryption Standard meets the first criterion "!t no longer the

secondary one : comp!ter speeds have ca!ght !p &ith it or soon &ill% AES meets "oth criteria in

all of its variants AES/12- AES/192 and AES/234%


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1.3 Encr!"#on mu$" be done !ro!er% :

AES may as all algorithms "e !sed in different &ays to perform encryption% 6ifferent

methods are s!ita"le for different sit!ations% It is vital that the correct method is applied in the

correct manner for each and every sit!ation or the res!lt may &ell "e insec!re even if AES as

s!ch is sec!re% It is very easy to implement a system !sing AES as its encryption algorithm "!t

m!ch more s+ill and e,perience is re0!ired to do it in the right &ay for a given sit!ation% #o

more than a hammer and a sa& &ill ma+e anyone a good carpenter &ill AES ma+e a system

sec!re "y itself% o descri"e e,actly ho& to apply AES for varying p!rposes is very m!ch o!t of

scope for this short introd!ction%

1.& S"rong ke$ :

Encryption &ith AES is "ased on a secret +ey &ith 12- 192 or 234 "its% *!t if the +ey is

easy to g!ess it doesn7t matter if AES is sec!re so it is as critically vital to !se good and strong

+eys as it is to apply AES properly% ;reating1 good and strong +eys is a s!rprisingly diffic!lt

pro"lem and re0!ires caref!l design &hen done &ith a comp!ter% he challenge is that comp!ters

are notorio!sly deterministic "!t &hat is re0!ired of a good and strong +ey is the opposite :

!npredicta"ility and randomness% these are shared "y all encryption


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CHAPTER 2

E)ISTIN* +ODE,

2.1 Ad(anced Encr!"#on S"andard -AES:

AES is a specification for the encryptionof electronic data% It has "een adopted "y

the U%S% governmentand is no& !sed &orld&ide% he algorithm descri"ed "y AES is

asymmetric/+ey algorithm meaning the same +ey is !sed for "oth encrypting and decrypting the

data%

In the United States AES &as anno!nced "y#ational Instit!te of Standards and

echnology(#IS) as U%S% FIPSPU* 195 (FIPS 195) on #ovem"er 24 2$$1 after a five/year

standardi.ation process in &hich fifteen competing designs &ere presented and eval!ated "efore

it &as selected as the most s!ita"le (see Advanced Encryption Standard processfor more

details)% It "ecame effective as a Federal government standard on 'ay 24 2$$2 after approval "y

the Secretary of ;ommerce% It is availa"le in many different encryption pac+ages% AES is the

first p!"licly accessi"le and open cipherapproved "y the#ational Sec!rity Agency(#SA)

for top secretinformation (see Sec!rity of AES "elo&)%

riginally called R#/ndae% the cipher&as developed "yt&o *elgiancryptographers oan

6aemenandBincent i8men and s!"mitted "y them to the AES selection

processt&o *elgian cryptographers oan 6aemen andBincent i8men and s!"mitted "y them to

the AES selection process% he nameRijndael(6!tch pron!nciationC r inda lD C3D ) is a play on

the names of the t&o inventors%

Strictly spea+ing AES is the name of the standard and the algorithm descri"ed is a (restricted)

variant of i8ndael% o&ever in practice the algorithm is also referred to as AES (a case

of tot!m pro parte)%
http://en.wikipedia.org/wiki/Encryptionhttp://en.wikipedia.org/wiki/Federal_government_of_the_United_Stateshttp://en.wikipedia.org/wiki/Symmetric-key_algorithmhttp://en.wikipedia.org/wiki/United_Stateshttp://en.wikipedia.org/wiki/United_Stateshttp://en.wikipedia.org/wiki/National_Institute_of_Standards_and_Technologyhttp://en.wikipedia.org/wiki/National_Institute_of_Standards_and_Technologyhttp://en.wikipedia.org/wiki/National_Institute_of_Standards_and_Technologyhttp://en.wikipedia.org/wiki/Federal_Information_Processing_Standardhttp://en.wikipedia.org/wiki/Advanced_Encryption_Standard_processhttp://en.wikipedia.org/wiki/United_States_Secretary_of_Commercehttp://en.wikipedia.org/wiki/Cipherhttp://en.wikipedia.org/wiki/National_Security_Agencyhttp://en.wikipedia.org/wiki/Classified_informationhttp://en.wikipedia.org/wiki/Classified_informationhttp://en.wikipedia.org/wiki/Advanced_Encryption_Standard#Securityhttp://en.wikipedia.org/wiki/Cipherhttp://en.wikipedia.org/wiki/Belgiumhttp://en.wikipedia.org/wiki/Joan_Daemenhttp://en.wikipedia.org/wiki/Joan_Daemenhttp://en.wikipedia.org/wiki/Vincent_Rijmenhttp://en.wikipedia.org/wiki/Belgiumhttp://en.wikipedia.org/wiki/Joan_Daemenhttp://en.wikipedia.org/wiki/Vincent_Rijmenhttp://en.wikipedia.org/wiki/Wikipedia:IPA_for_Dutch_and_Afrikaanshttp://en.wikipedia.org/wiki/Wikipedia:IPA_for_Dutch_and_Afrikaanshttp://en.wikipedia.org/wiki/Wikipedia:IPA_for_Dutch_and_Afrikaanshttp://en.wikipedia.org/wiki/Wikipedia:IPA_for_Dutch_and_Afrikaanshttp://en.wikipedia.org/wiki/Advanced_Encryption_Standard#cite_note-4http://en.wikipedia.org/wiki/Advanced_Encryption_Standard#cite_note-4http://en.wikipedia.org/wiki/Totum_pro_partehttp://en.wikipedia.org/wiki/Encryptionhttp://en.wikipedia.org/wiki/Federal_government_of_the_United_Stateshttp://en.wikipedia.org/wiki/Symmetric-key_algorithmhttp://en.wikipedia.org/wiki/United_Stateshttp://en.wikipedia.org/wiki/National_Institute_of_Standards_and_Technologyhttp://en.wikipedia.org/wiki/National_Institute_of_Standards_and_Technologyhttp://en.wikipedia.org/wiki/Federal_Information_Processing_Standardhttp://en.wikipedia.org/wiki/Advanced_Encryption_Standard_processhttp://en.wikipedia.org/wiki/United_States_Secretary_of_Commercehttp://en.wikipedia.org/wiki/Cipherhttp://en.wikipedia.org/wiki/National_Security_Agencyhttp://en.wikipedia.org/wiki/Classified_informationhttp://en.wikipedia.org/wiki/Advanced_Encryption_Standard#Securityhttp://en.wikipedia.org/wiki/Cipherhttp://en.wikipedia.org/wiki/Belgiumhttp://en.wikipedia.org/wiki/Joan_Daemenhttp://en.wikipedia.org/wiki/Joan_Daemenhttp://en.wikipedia.org/wiki/Vincent_Rijmenhttp://en.wikipedia.org/wiki/Belgiumhttp://en.wikipedia.org/wiki/Joan_Daemenhttp://en.wikipedia.org/wiki/Vincent_Rijmenhttp://en.wikipedia.org/wiki/Wikipedia:IPA_for_Dutch_and_Afrikaanshttp://en.wikipedia.org/wiki/Advanced_Encryption_Standard#cite_note-4http://en.wikipedia.org/wiki/Totum_pro_parte


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2.2 De$cr#!"#on o0 "e c#!er:

AES is "ased on a design principle +no&n as as!"stit!tion/perm!tation net&or+%It is

fast in "othsoft&areand hard&are%C4DUnli+e its predecessor 6ES AES does not !se a Feistel

net&or+%

AES has a fi,ed"loc+ si.e of 12-"itsand a +ey si.e of 12- 192 or 234 "its &hereas

i8ndael can "e specified &ith "loc+ and +ey si.es in any m!ltiple of 2 "its &ith a minim!m of

12- "its% he "loc+si.e has a ma,im!m of 234 "its "!t the +eysi.e has no theoretical ma,im!m%

AES operates on a @G@ col!mn/ma8or ordermatri, of "ytes termed thestate(versions of

i8ndael &ith a larger "loc+ si.e have additional col!mns in the state)% 'ost AES calc!lations

are done in a special finite field%

he AES cipher is specified as a n!m"er of repetitions of transformation ro!nds that

convert the inp!t plainte,t into the final o!tp!t of cipherte,t% Each ro!nd consists of several

processing steps incl!ding one that depends on the encryption +ey% A set of reverse ro!nds are

applied to transform cipherte,t "ac+ into the original plainte,t !sing the same encryption +ey%

2.3 H#g%e(e% de$cr#!"#on o0 "e a%gor#"m:

1.


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#gure 2.1: A%gor#"m 0or AES Encr!"#on

% o!nds

1. S!"*ytesHa non/linear s!"stit!tion step &here each "yte is replaced &ith another

according to a loo+!p ta"le%

2. Shifto&sHa transposition step &here each ro& of the state is shifted cyclically a

certain n!m"er of steps%

3. 'i,;ol!mnsHa mi,ing operation &hich operates on the col!mns of the state

com"ining the fo!r "ytes in each col!mn%

4.

Addo!nd


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he ShiftRowsstep operates on the ro&s of the state> it cyclically shifts the "ytes in each

ro& "y a certain offset% For AES the first ro& is left !nchanged% Each "yte of the second ro& is

shifted one to the left% Similarly the third and fo!rth ro&s are shifted "y offsets of t&o and three

respectively% For the "loc+ of si.e 12- "its and 192 "its the shifting pattern is the same% In this

&ay each col!mn of the o!tp!t state of the ShiftRowsstep is composed of "ytes from each

col!mn of the inp!t state% (i8ndael variants &ith a larger "loc+ si.e have slightly different

offsets)% In the case of the 234/"it "loc+ the first ro& is !nchanged and the shifting for second

third and fo!rth ro& is 1 "yte "ytes and @ "ytes respectivelyHthis change only applies for the

i8ndael cipher &hen !sed &ith a 234/"it "loc+ as AES does not !se 234/"it "loc+s%

#g 2.3 S#0" ro4$ #n0orma"#on

2.5 TeMix Columns$"e!:

In the 'i,;ol!mns step the fo!r "ytes of each col!mn of the state are com"ined !sing

an inverti"le linear transformation% he'i,;ol!mns f!nction ta+es fo!r "ytes as inp!t and

o!tp!ts fo!r "ytes &here each inp!t "yte affects all fo!r o!tp!t "ytes% ogether

&ithShifto&s 'i,;ol!mns provides diff!sionin the cipher%

6!ring this operation each col!mn is m!ltiplied "y the +no&n matri, that for the 12- "it +ey is
http://en.wikipedia.org/wiki/Offset_(computer_science)http://en.wikipedia.org/wiki/Linear_transformationhttp://en.wikipedia.org/wiki/Diffusion_(cryptography)http://en.wikipedia.org/wiki/Offset_(computer_science)http://en.wikipedia.org/wiki/Linear_transformationhttp://en.wikipedia.org/wiki/Diffusion_(cryptography)


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he m!ltiplication operation is defined as m!ltiplication "y 1 means leaving !nchanged

m!ltiplication "y 2 means shifting "yte to the left and m!ltiplication "y means shifting to

the left and then performing ,or&ith the initial !nshifted val!e% After shifting a

conditional ,or&ith $,1* sho!ld "e performed if the shifted val!e is larger than $,FF%

In more general sense each col!mn is treated as a polynomial over *(28) and is then

m!ltiplied mod!lo ,

@

J1 &ith a fi,ed polynomial c(,) K $,$ L ,

J ,

2

J , J $,$2% he

coefficients are displayed in theirhe,adecimale0!ivalent of the "inary representation of "it

polynomials from *(2)C,D% he 'i,;ol!mns step can also "e vie&ed as a m!ltiplication "y

a partic!lar'6S matri,in a finite field% his process is descri"ed f!rther in the

article i8ndael mi, col!mns%

#g 2.& +#6 Co%umn$ #n0orma"#on
http://en.wikipedia.org/wiki/Xorhttp://en.wikipedia.org/wiki/Xorhttp://en.wikipedia.org/wiki/Xorhttp://en.wikipedia.org/wiki/Hexadecimalhttp://en.wikipedia.org/wiki/Hexadecimalhttp://en.wikipedia.org/wiki/MDS_matrixhttp://en.wikipedia.org/wiki/MDS_matrixhttp://en.wikipedia.org/wiki/Finite_fieldhttp://en.wikipedia.org/wiki/Rijndael_mix_columnshttp://en.wikipedia.org/wiki/Rijndael_mix_columnshttp://en.wikipedia.org/wiki/Xorhttp://en.wikipedia.org/wiki/Xorhttp://en.wikipedia.org/wiki/Hexadecimalhttp://en.wikipedia.org/wiki/MDS_matrixhttp://en.wikipedia.org/wiki/Finite_fieldhttp://en.wikipedia.org/wiki/Rijndael_mix_columns


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2.7 TeAdd RoundKey$"e!:

In the AddRoundKeystep the s!"+ey is com"ined &ith the state% For each ro!nd a s!"+ey

is derived from the main +ey!singi8ndaels +ey sched!le> each s!"+ey is the same si.e as the

state% he s!"+ey is added "y com"ining each "yte of the state &ith the corresponding "yte of the

s!"+ey !sing "it&ise M%

#g 2.' add around ke #n0orma"#on

2.8 O!"#m#9a"#on o0 "e c#!er:

n systems &ith 2/"it or larger &ords it is possi"le to speed !p e,ec!tion of this cipher

"y com"ining S!"*ytesand Shifto&s&ith'i,;ol!mns and transforming them into a se0!ence of
http://en.wikipedia.org/wiki/Key_(cryptography)http://en.wikipedia.org/wiki/Rijndael_key_schedulehttp://en.wikipedia.org/wiki/Rijndael_key_schedulehttp://en.wikipedia.org/wiki/Exclusive_orhttp://en.wikipedia.org/wiki/Key_(cryptography)http://en.wikipedia.org/wiki/Rijndael_key_schedulehttp://en.wikipedia.org/wiki/Exclusive_or


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AES has 1$ ro!nds for 12-/"it +eys 12 ro!nds for 192/"it +eys and 1@ ro!nds for 234/

"it +eys% *y 2$$4 the "est +no&n attac+s &ere on 5 ro!nds for 12-/"it +eys - ro!nds for 192/"it

+eys and 9 ro!nds for 234/"it +eys%

2.1; seeMS attac+ on "loc+ ciphers%

6!ring the AES process developers of competing algorithms &rote of i8ndael %%%&e

are concerned a"o!t CitsD !se%%%in sec!rity/critical applications% o&ever at the end of the AES

process *r!ce Schneier a developer of the competing algorithm &ofish &rote that &hile he

tho!ght s!ccessf!l academic attac+s on i8ndael &o!ld "e developed someday I do not "elieve

that anyone &ill ever discover an attac+ that &ill allo& someone to read i8ndael traffic%

n !ly 1 2$$9 *r!ce Schneier "logged a"o!t a related/+ey attac+on the 192/"it and

234/"it versions of AES discovered "y Ale, *iry!+ovand 6mitry


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6mitry


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inadvertently lea+ data% here are several s!ch +no&n attac+s on certain implementations of

AES%

In April 2$$3 6%% *ernsteinanno!nced a cache/timing attac+ that he !sed to "rea+ a

c!stom server that !sedpenSSs AES encryption%C2Dhe attac+ re0!ired over 2$$ million

chosen plainte,ts% he c!stom server &as designed to give o!t as m!ch timing information as

possi"le (the server reports "ac+ the n!m"er of machine cycles ta+en "y the encryption

operation)> ho&ever as *ernstein pointed o!t red!cing the precision of the server7s

timestamps or eliminating them from the server7s responses does not stop the attac+ the client

simply !ses ro!nd/trip timings "ased on its local cloc+ and compensates for the increased noise

"y averaging over a larger n!m"er of samples%

In cto"er 2$$3 6ag Arne svi+ Adi Shamirand Eran romer presented a paper

demonstrating several cache/timing attac+s against AES% ne attac+ &as a"le to o"tain an entire

AES +ey after only -$$ operations triggering encryptions in a total of 43 milliseconds% his

attac+ re0!ires the attac+er to "e a"le to r!n programs on the same system or platform that is

performing AES%

In 6ecem"er 2$$9 an attac+ on some hard&are implementations &as p!"lished that

!sed differential fa!lt analysisand allo&s recovery of +ey &ith comple,ity of %

In #ovem"er 2$1$ Endre *angerter 6avid N!llasch and Stephan


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doc!ment and prepare a mod!le for validation% After validation mod!les m!st "e re/s!"mitted

and re/eval!ated if they are changed in any &ay% his can vary from simple paper&or+ !pdates if

the sec!rity f!nctionality did not change to a more s!"stantial set of re/testing if the sec!rity

f!nctionality &as impacted "y the change%


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It is designed to prod!ce ro!nd +eys on each positive edge of the cloc+ &hen it is

ena"led% o&ever in the proposed &or+ the +ey generation architect!re does not re0!ire any

hard&are for shift operation and the port mapping "et&een +ey register and S/*o, is done

according to the re0!ired shift% ence the proposed &or+ offers the advantage in area% Also in the

proposed &or+ the "its are rearranged on data path from register to S/*o, and the ro!nd constant

re0!ired for each ro!nds are stored in ' and retrieved on each cloc+% Fig%%2 represents

proposed architect!re of +ey generation !nit%

Fig% %2% Architect!re of


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3.1 Encr!"#on:

he encryption mod!le ta+es 12- "it te,t to "e encrypted and receives ro!nd +ey from

+ey generation mod!le to do each ro!nd of encryption% Fig% 3 presents the proposed encryption

mod!le%

Start stopmi, terminate are control signal prod!ced "y the control !nit% he Tdone7

signal is provided to indicate that encryption is done% Architect!re is as sho&n in Fig% %@%

In the proposed &or+ for red!cing the hard&are of entire architect!re the control !nit of

encryption mod!le is not designed separately% he control !nit of +ey generation mod!le &hich

is a @/"it co!nter is designed to control the entire f!nctioning of encryption mod!le% he sharing

of control !nit "y "oth encryption and ro!nd +ey generation gives !ni0!e advantage of red!ction

in hard&are as compared to other implementations%

#g 3.3 Encr!"#on +odu%e


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#g 3.&: Pro!o$ed arc#"ec"ure o0 encr!"#on modu%e

In the last ro!nd i8andael algorithm s+ips 'i, ;ol!mn peration% o incorporate this

f!nctionality proposed design !se a '!ltiple,er and #A#6 gate as sho&n in Fig% %3%

#g 3.': Hard4are "o Sk#! +#6 Co%umn O!era"#on 0or ,a$" Round


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#A#6 gate and the @/"it co!nter (;ontroller) are !sed to set and reset selection line of

'!ltiple,er% For co!nt one to ten the selection line &ill "e in set condition and m!ltiple,er &ill

pass 'i, ;ol!mn o!tp!t% o&ever on last ro!nd co!nt &ill "e eleven so selection line &ill reset

and pass S!" *yte o!tp!t%

Shift o& operation is designed in s!ch a &ay that it does not ta+e any hard&are% After

o!nd


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#g 3.5: Pro!o$ed arc#"ec"ure o0 Decr!"#on modu%e

he decryption !nit also !ses same design approach for the entire architect!re and ta+es

2$ cloc+ cycles to decrypt the given cipher "ac+ to original te,t% Inverse S/*o, architect!re !ses

the same design of S/*o,% Entry of U is changed according to Inverse S!" *yte

transformation% 'i, ;ol!mn operation is implemented !sing 234M- '% Fo!r s!ch 's are

designed for the Nalois m!ltiplication of 9 11 1 and 1@% @/Inp!t M operation is designed "y

14,1 '% Architect!re of 6ecryption mod!le is same as encryption mod!le &ith all

complimentary f!nctions of encryption% 6ecryption !nit contains an e,tra register for storing

o!nd


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APP,ICATIONS:

=idely !sed for comp!ter and comm!nication net&or+%

Information sec!rity has aro!sed high attention%

Used in military political and diplomatic fields%

Also applied to common fields of people7s daily lives%

+ERITS:

e0!ire7s lo& space%

Speed of operation is high%

e0!ire7s lo& po&er cons!mption%

Easy to implement%


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'. INTRODUCTION TO ?,SI

Bery/large/scale integration (BSI) is the process of creating integrated circ!its "y

com"ining tho!sands of transistor/"ased circ!its into a single chip% BSI "egan in the 195$s

&hen comple, semicond!ctor and comm!nication technologies &ere "eing developed% he

microprocessor is a BSI device% he term is no longer as common as it once &as as chips have

increased in comple,ity into the h!ndreds of millions of transistors%

'.1 O(er(#e4:

he first semicond!ctor chips held one transistor each% S!"se0!ent advances added moreand more transistors and as a conse0!ence more individ!al f!nctions or systems &ere

integrated over time% he first integrated circ!its held only a fe& devices perhaps as many as ten

diodes transistors resistors and capacitors ma+ing it possi"le to fa"ricate one or more logic

gates on a single device% #o& +no&n retrospectively as small/scale integration (SSI)

improvements in techni0!e led to devices &ith h!ndreds of logic gates +no&n as large/scale

integration (SI) i%e% systems &ith at least a tho!sand logic gates% ;!rrent technology has moved

far past this mar+ and todays microprocessors have many millions of gates and h!ndreds of

millions of individ!al transistors%

At one time there &as an effort to name and cali"rate vario!s levels of large/scale

integration a"ove BSI% erms li+e Ultra/large/scale Integration (USI) &ere !sed% *!t the h!ge

n!m"er of gates and transistors availa"le on common devices has rendered s!ch fine distinctions

moot%

erms s!ggesting greater than BSI levels of integration are no longer in

&idespread !se% Even BSI is no& some&hat 0!aint given the common ass!mption that all

microprocessors are BSI or "etter%

As of early 2$$- "illion/transistor processors are commercially availa"le an

e,ample of &hich is Intels 'ontecito Itani!m chip% his is e,pected to "ecome more

commonplace as semicond!ctor fa"rication moves from the c!rrent generation of 43 nm


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processes to the ne,t @3 nm generations (&hile e,periencing ne& challenges s!ch as increased

variation across process corners)% Another nota"le e,ample is #BI6IA7s 2-$ series NPU%

his microprocessor is !ni0!e in the fact that its 1%@ *illion transistor co!nt

capa"le of a teraflop of performance is almost entirely dedicated to logic (Itani!ms transistorco!nt is largely d!e to the 2@'* cache)% ;!rrent designs as opposed to the earliest devices

!se e,tensive design a!tomation and a!tomated logic synthesis to lay o!t the transistors

ena"ling higher levels of comple,ity in the res!lting logic f!nctionality% ;ertain high/

performance logic "loc+s li+e the SA' cell ho&ever are still designed "y hand to ens!re the

highest efficiency (sometimes "y "ending or "rea+ing esta"lished design r!les to o"tain the last

"it of performance "y trading sta"ility)%

'.2 @a" #$ ?,SI

VLSI stands for "Very Large Scale Integration". This is the field which involves packing

more and more logic devices into smaller and smaller areas.

VLSI

1. Simply we say Integrated circuit is many transistors on one chip.

2. esign!manufacturing of etremely small# comple circuitry using modified

semiconductor material

$. Integrated circuit %I&' may contain millions of transistors# each a few mm in si(e

). *pplications wide ranging+ most electronic logic devices

'.3 H#$"or o0 Sca%e In"egra"#on:

late @$s ransistor invented at *ell a"s

late 3$s First I; (


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early 4$s Small Scale Integration (SSI)

1$s of transistors on a chip

late 4$s 'edi!m Scale Integration ('SI)

1$$s of transistors on a chip

early 5$s arge Scale Integration (SI)

1$$$s of transistor on a chip

early -$s BSI 1$$$$s of transistors on a

chip (later 1$$$$$s V no& 1$$$$$$s)

Ultra SI is sometimes !sed for 1$$$$$$s

SSI / Small/Scale Integration ($/1$2)

'SI / 'edi!m/Scale Integration (1$2/1$)

SI / arge/Scale Integration (1$/1$3)

BSI / Bery arge/Scale Integration (1$3/1$5)

USI / Ultra arge/Scale Integration (WK1$5)

'.& Ad(an"age$ o0 IC$ o(er d#$cre"e com!onen"$:

=hile &e &ill concentrate on integrated circ!its the properties of

integrated circ!its/&hat &e can and cannot efficiently p!t in an integrated circ!it/largely

determine the architect!re of the entire system% Integrated circ!its improve system characteristics

in several critical &ays% I;s have three +ey advantages over digital circ!its "!ilt from discrete

components

Si.e% Integrated circ!its are m!ch smaller/"oth transistors and &ires are shr!n+ to

micrometer si.es compared to the millimeter or centimeter scales of discretecomponents% Small si.e leads to advantages in speed and po&er cons!mption since

smaller components have smaller parasitic resistances capacitances and ind!ctances%

Speed% Signals can "e s&itched "et&een logic $ and logic 1 m!ch 0!ic+er &ithin a chip

than they can "et&een chips% ;omm!nication &ithin a chip can occ!r h!ndreds of times


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faster than comm!nication "et&een chips on a printed circ!it "oard% he high speed of

circ!its on/chip is d!e to their small si.e/smaller components and &ires have smaller

parasitic capacitances to slo& do&n the signal%

Po&er cons!mption% ogic operations &ithin a chip also ta+e m!ch less po&er% nceagain lo&er po&er cons!mption is largely d!e to the small si.e of circ!its on the chip/

smaller parasitic capacitances and resistances re0!ire less po&er to drive them%

'.' ?,SI and $$"em$:

hese advantages of integrated circ!its translate into advantages at the system level

Smaller physical si.e% Smallness is often an advantage in itself/consider porta"le

televisions or handheld cell!lar telephones%

o&er po&er cons!mption% eplacing a handf!l of standard parts &ith a single chip

red!ces total po&er cons!mption% ed!cing po&er cons!mption has a ripple effect on the

rest of the system a smaller cheaper po&er s!pply can "e !sed> since less po&er

cons!mption means less heat a fan may no longer "e necessary> a simpler ca"inet &ith

less shielding for electromagnetic shielding may "e feasi"le too%

ed!ced cost% ed!cing the n!m"er of components the po&er s!pply re0!irements

ca"inet costs and so on &ill inevita"ly red!ce system cost% he ripple effect of

integration is s!ch that the cost of a system "!ilt from c!stom I;s can "e less even

tho!gh the individ!al I;s cost more than the standard parts they replace%

Understanding &hy integrated circ!it technology has s!ch profo!nd infl!ence on the design

of digital systems re0!ires !nderstanding "oth the technology of I; man!fact!ring and the

economics of I;s and digital systems%

Applications

Electronic system in cars%

6igital electronics control B;s

ransaction processing system A'

Personal comp!ters and =or+stations


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'edical electronic systems%

EtcX%

'.5 A!!%#ca"#on$ o0 ?,SI:

Electronic systems no& perform a &ide variety of tas+s in daily life% Electronic

systems in some cases have replaced mechanisms that operated mechanically hydra!lically or

"y other means> electronics are !s!ally smaller more fle,i"le and easier to service% In other

cases electronic systems have created totally ne& applications% Electronic systems perform a

variety of tas+s some of them visi"le some more hidden

Personal entertainment systems s!ch as porta"le 'P players and 6B6

players perform sophisticated algorithms &ith remar+a"ly little energy%

Electronic systems in cars operate stereo systems and displays> they also

control f!el in8ection systems ad8!st s!spensions to varying terrain and

perform the control f!nctions re0!ired for anti/loc+ "ra+ing (A*S) systems%

6igital electronics compress and decompress video even at high/definition

data rates on/the/fly in cons!mer electronics%

o&/cost terminals for =e" "ro&sing still re0!ire sophisticated electronics

despite their dedicated f!nction%

Personal comp!ters and &or+stations provide &ord/processing financial

analysis and games% ;omp!ters incl!de "oth central processing !nits (;PUs)

and special/p!rpose hard&are for dis+ access faster screen display etc%

'edical electronic systems meas!re "odily f!nctions and perform comple,

processing algorithms to &arn a"o!t !n!s!al conditions% he availa"ility of

these comple, systems far from over&helming cons!mers only creates

demand for even more comple, systems%

he gro&ing sophistication of applications contin!ally p!shes the design and

man!fact!ring of integrated circ!its and electronic systems to ne& levels of comple,ity% And

perhaps the most ama.ing characteristic of this collection of systems is its variety/as systems


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"ecome more comple, &e "!ild not a fe& general/p!rpose comp!ters "!t an ever &ider range of

special/p!rpose systems% !r a"ility to do so is a testament to o!r gro&ing mastery of "oth

integrated circ!it man!fact!ring and design "!t the increasing demands of c!stomers contin!e to

test the limits of design and man!fact!ring

'.7 ASIC:

An Application/Specific Integrated ;irc!it (ASI;) is an integrated circ!it (I;)

c!stomi.ed for a partic!lar !se rather than intended for general/p!rpose !se% For e,ample a chip

designed solely to r!n a cell phone is an ASI;% Intermediate "et&een ASI;s and ind!stry

standard integrated circ!its li+e the 5@$$ or the @$$$ series are application specific standard

prod!cts (ASSPs)%

As feat!re si.es have shr!n+ and design tools improved over the years the ma,im!m

comple,ity (and hence f!nctionality) possi"le in an ASI; has gro&n from 3$$$ gates to over

1$$ million% 'odern ASI;s often incl!de entire 2/"it processors memory "loc+s incl!ding

' A' EEP' Flash and other large "!ilding "loc+s% S!ch an ASI; is often termed a

So; (system/on/a/chip)% 6esigners of digital ASI;s !se a hard&are description lang!age (6)

s!ch as Berilog or B6 to descri"e the f!nctionality of ASI;s%

Field/programma"le gate arrays (FPNA) are the modern/day technology for "!ilding a

"read"oard or prototype from standard parts> programma"le logic "loc+s and programma"leinterconnects allo& the same FPNA to "e !sed in many different applications% For smaller

designs andOor lo&er prod!ction vol!mes FPNAs may "e more cost effective than an ASI;

design even in prod!ction%

An application/specific integrated circ!it (ASI;) is an integrated circ!it (I;) c!stomi.ed

for a partic!lar !se rather than intended for general/p!rpose !se%

1. * Structured *SI& falls ,etween an -/* and a Standard &ell0,ased *SI&

2. Structured *SI&s are used mainly for mid0volume level design. The design task for

structured *SI&s is to map the circuit into a fied arrangement of known cells.


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5. INTRODUCTION TO )I,IN)

5.1 +#gra"#ng Pro/ec"$ 0rom Pre(#ou$ ISE So0"4are Re%ea$e$:

=hen yo! open a pro8ect file from a previo!s release the ISEY soft&are prompts yo! to

migrate yo!r pro8ect% If yo! clic+ *ac+!p and 'igrate or 'igrate nly the soft&are

a!tomatically converts yo!r pro8ect file to the c!rrent release% If yo! clic+ ;ancel the soft&are

does notconvert yo!r pro8ect and instead opens Pro8ect #avigator &ith no pro8ect loaded%

No"e: After yo! convert yo!r pro8ect yo! cannotopen it in previo!s versions of the ISE

soft&are s!ch as the ISE 11 soft&are% o&ever yo! can optionally create a "ac+!p of the

original pro8ect as part of pro8ect migration as descri"ed "elo&%

To +#gra"e a Pro/ec"

1% In the ISE 12 Pro8ect #avigator select #%e B O!en Pro/ec"%

2% In the pen Pro8ect dialog "o, select the %,ise file to migrate%

No"e Zo! may need to change the e,tension in the Files of type field to display %npl

(ISE 3 and ISE 4 soft&are) or %ise (ISE 5 thro!gh ISE 1$ soft&are) pro8ect files%

% In the dialog "o, that appears select >acku! and +#gra"eor +#gra"e On%%

@% he ISE soft&are a!tomatically converts yo!r pro8ect to an ISE 12 pro8ect%

No"e If yo! chose to *ac+!p and 'igrate a "ac+!p of the original pro8ect is created at

project_name_ise12migration%.ip%

3% Implement the design !sing the ne& version of the soft&are%

No"e Implementation stat!s is notmaintained after migration%


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1% Select #%e B O!en E6am!%e%

2% In the pen E,ample dialog "o,select the Sample Pro8ect #ame%

No"e o help yo! choose an e,ample pro8ect the Pro8ect 6escription field descri"es

each pro8ect% In addition yo! can scroll to the right to see additional fields &hich

provide details a"o!t the pro8ect%

% In the 6estination 6irectory field enter a directory name or "ro&se to the

directory%

@% ;lic+ O


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3. For EDIF or NGC/NGO projects only In the Im!or" EDI=N*C Pro/ec" !age

select the inp!t and constraint file for the pro8ect and clic+ Ne6"%

4. In the Pro/ec" Se""#ng$ !age set the device and pro8ect properties and clic+

Ne6"%

3% In the Pro/ec" Summar !age revie& the information and clic+ #n#$ to

create the pro8ect

Pro8ect #avigator creates the pro8ect file (project_name%,ise) in the directory yo!

specified% After yo! add so!rce files to the pro8ect the files appear in the ierarchy pane of the

4%5 De$#gn !ane%

Pro8ect #avigator manages yo!r pro8ect "ased on the design properties (top/level mod!le

type device type synthesis tool and lang!age) yo! selected &hen yo! created the pro8ect% It

organi.es all the parts of yo!r design and +eeps trac+ of the processes necessary to move the

design from design entry thro!gh implementation to programming the targeted Milin,Y device%

No"e For information on changing design properties see Cang#ng De$#gn Pro!er"#e$.

Zo! can no& perform any of the follo&ing

;reate ne& so!rce files for yo!r pro8ect%

Add e,isting so!rce files to yo!r pro8ect%

!n processes on yo!r so!rce files%

'odify process properties%

5.8 Crea"#ng a Co! o0 a Pro/ec":

Zo! can create a copy of a pro8ect to e,periment &ith different so!rce options and

implementations% 6epending on yo!r needs the design so!rce files for the copied pro8ect and

their location can vary as follo&s
http://var/www/apps/conversion/tmp/scratch_1/pn_db_npw_import_edif_ngc_project.htmhttp://var/www/apps/conversion/tmp/scratch_1/pn_db_npw_import_edif_ngc_project.htmhttp://var/www/apps/conversion/tmp/scratch_1/pn_db_npw_device_properties.htmhttp://var/www/apps/conversion/tmp/scratch_1/pn_db_npw_project_summary.htmhttp://var/www/apps/conversion/tmp/scratch_1/pn_r_design_panel.htmhttp://var/www/apps/conversion/tmp/scratch_1/pn_p_changing_design_properties.htmhttp://var/www/apps/conversion/tmp/scratch_1/pn_db_npw_import_edif_ngc_project.htmhttp://var/www/apps/conversion/tmp/scratch_1/pn_db_npw_device_properties.htmhttp://var/www/apps/conversion/tmp/scratch_1/pn_db_npw_project_summary.htmhttp://var/www/apps/conversion/tmp/scratch_1/pn_r_design_panel.htmhttp://var/www/apps/conversion/tmp/scratch_1/pn_p_changing_design_properties.htm


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6esign so!rce files are left in their e,isting location and the copied pro8ect

points to these files%

6esign so!rce files incl!ding generated files are copied and placed in a

specified directory%

6esign so!rce files e,cl!ding generated files are copied and placed in a

specified directory%

;opied pro8ects are the same as other pro8ects in "oth form and f!nction% For e,ample yo! can

do the follo&ing &ith copied pro8ects

pen the copied pro8ect !sing the File W pen Pro8ect men! command%

Bie& modify and implement the copied pro8ect%

Use the Pro8ect *ro&ser to vie& +ey s!mmary data for the copied pro8ect and

then open the copied pro8ect for f!rther analysis and implementation as descri"ed in

6.9 U$#ng "e Pro/ec" >ro4$er

Alternatively yo! can create an archive of yo!r pro8ect &hich p!ts all of the pro8ect

contents into a \IP file% Archived pro8ects m!st "e !n.ipped "efore "eing opened in Pro8ect

#avigator% For information on archiving see Crea"#ng a Pro/ec" Arc#(e.

To Crea"e a Co! o0 a Pro/ec"

1% Select #%e B Co! Pro/ec"%

2% In the ;opy Pro8ect dialog "o, enter the Namefor the copy%

No"e he name for the copy can "e the same as the name for the pro8ect as long as yo!

specify a different location%

% Enter a directory ,oca"#onto store the copied pro8ect%

@% ptionally enter a @ork#ng d#rec"or%

*y defa!lt this is "lan+ and the &or+ing directory is the same as the pro8ect directory%

o&ever yo! can specify a &or+ing directory if yo! &ant to +eep yo!r ISEY pro8ect

file (%,ise e,tension) separate from yo!r &or+ing area%

3% ptionally enter a De$cr#!"#onfor the copy%

he description can "e !sef!l in identifying +ey traits of the pro8ect for reference later%
http://var/www/apps/conversion/tmp/scratch_1/ise_c_project_browser.htmhttp://var/www/apps/conversion/tmp/scratch_1/ise_c_project_archive.htmhttp://var/www/apps/conversion/tmp/scratch_1/ise_c_project_archive.htmhttp://var/www/apps/conversion/tmp/scratch_1/ise_c_project_browser.htmhttp://var/www/apps/conversion/tmp/scratch_1/ise_c_project_archive.htm


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4% In the So!rce options area do the follo&ing

Select one of the follo&ing options


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;lic+ O


38/55

7. INTRODUCTION TO ?ERI,O*

In the semicond!ctorand electronic designind!stry ?er#%ogis a hard&are description

lang!age(6) !sed to model electronic systems% Verilo !D" not to "e conf!sed

&ithB6(a competing lang!age) is most commonly !sed in the design verification and

implementation ofdigitallogic chips at the register/transfer levelofa"straction% It is also !sed in

the verification ofanalogand mi,ed/signal circ!its%

O(er(#e4

ard&are description lang!ages s!ch as Berilog differ from soft&areprogramming

lang!ages"eca!se they incl!de &ays of descri"ing the propagation of time and signal

dependencies (sensitivity)% here are t&o assignment operators a "loc+ing assignment (K) and a

non/"loc+ing (^K) assignment% he non/"loc+ing assignment allo&s designers to descri"e a

state/machine !pdate &itho!t needing to declare and !se temporary storage varia"les (in any

general programming lang!age &e need to define some temporary storage spaces for the

operands to "e operated on s!"se0!ently> those are temporary storage varia"les)% Since these

concepts are part of Berilogs lang!age semantics designers co!ld 0!ic+ly &rite descriptions of

large circ!its in a relatively compact and concise form% At the time of Berilogs introd!ction

(19-@) Berilog represented a tremendo!s prod!ctivity improvement for circ!it designers &ho&ere already !sing graphical schematic capt!resoft&are and specially/&ritten soft&are programs

to doc!ment and sim!late electronic circ!its%

he designers of Berilog &anted a lang!age &ith synta, similar to the ; programming

lang!age&hich &as already &idely !sed in engineering soft&are development% Berilog is case/
http://en.wikipedia.org/wiki/Semiconductor_industryhttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Electronics#Electronic_systemshttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Register-transfer_levelhttp://en.wikipedia.org/wiki/Abstraction_(computer_science)http://en.wikipedia.org/wiki/Abstraction_(computer_science)http://en.wikipedia.org/wiki/Analog_circuithttp://en.wikipedia.org/wiki/Mixed-signal_integrated_circuithttp://en.wikipedia.org/wiki/Mixed-signal_integrated_circuithttp://en.wikipedia.org/wiki/Programming_languagehttp://en.wikipedia.org/wiki/Programming_languagehttp://en.wikipedia.org/wiki/Schematic_capturehttp://en.wikipedia.org/wiki/Electronic_circuit_simulationhttp://en.wikipedia.org/wiki/Electronic_circuit_simulationhttp://en.wikipedia.org/wiki/C_(programming_language)http://en.wikipedia.org/wiki/C_(programming_language)http://en.wikipedia.org/wiki/C_(programming_language)http://en.wikipedia.org/wiki/Case-sensitivehttp://en.wikipedia.org/wiki/Case-sensitivehttp://en.wikipedia.org/wiki/Semiconductor_industryhttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Electronics#Electronic_systemshttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Register-transfer_levelhttp://en.wikipedia.org/wiki/Abstraction_(computer_science)http://en.wikipedia.org/wiki/Analog_circuithttp://en.wikipedia.org/wiki/Mixed-signal_integrated_circuithttp://en.wikipedia.org/wiki/Programming_languagehttp://en.wikipedia.org/wiki/Programming_languagehttp://en.wikipedia.org/wiki/Schematic_capturehttp://en.wikipedia.org/wiki/Electronic_circuit_simulationhttp://en.wikipedia.org/wiki/C_(programming_language)http://en.wikipedia.org/wiki/C_(programming_language)http://en.wikipedia.org/wiki/Case-sensitive


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sensitive has a "asicpreprocessor (tho!gh less sophisticated than that of A#SI ;O;JJ) and

e0!ivalent control flo&+ey&ords(ifOelse for &hile case etc%) and compati"le operator

precedence% Syntactic differences incl!de varia"le declaration (Berilog re0!ires "it/&idths on

netOreg typesCclarification neededD) demarcation of proced!ral "loc+s ("eginOend instead of c!rly "races

_`) and many other minor differences%

A Berilog design consists of a hierarchy of mod!les% 'od!les encaps!late desin

#ierarc#y and comm!nicate &ith other mod!les thro!gh a set of declared inp!t o!tp!t and

"idirectional ports% Internally a mod!le can contain any com"ination of the follo&ing

netOvaria"le declarations (&ire reg integer etc%) conc!rrent and se0!ential statement "loc+s

and instances of other mod!les (s!"/hierarchies)% Se0!ential statements are placed inside a

"eginOend "loc+ and e,ec!ted in se0!ential order &ithin the "loc+% *!t the "loc+s themselves are

e,ec!ted conc!rrently 0!alifying Berilog as adataflo& lang!age%

Berilogs concept of &ire consists of "oth signal val!es (@/state 1 $ floating

!ndefined) and strengths (strong &ea+ etc%)% his system allo&s a"stract modeling of shared

signal lines &here m!ltiple so!rces drive a common net% =hen a &ire has m!ltiple drivers the

&ires (reada"le) val!e is resolved "y a f!nction of the so!rce drivers and their strengths%

A s!"set of statements in the Berilog lang!age is synthesi.a"le% Berilog mod!les that

conform to a synthesi.a"le coding style +no&n as (register/transfer level) can "e

physically reali.ed "y synthesis soft&are% Synthesis soft&are algorithmically transforms the

(a"stract) Berilog so!rce into a net list a logically e0!ivalent description consisting only of

elementary logic primitives (A#6 # flip/flops etc%) that are availa"le in a

specific FPNAor BSItechnology% F!rther manip!lations to the net list !ltimately lead to a

circ!it fa"rication "l!eprint (s!ch as aphoto mas+ setfor anASI;or a"it streamfile for

anFPNA)%

H#$"or

>eg#nn#ng

Berilog &as the first modern hard&are description lang!age to "e invented% It &as created

"y Phil 'oor"yandPra"h! Noeld!ring the &inter of 19-O19-@% he &ording for this process

&as A!tomated Integrated 6esign Systems (later renamed to Nate&ay 6esign A!tomationin
http://en.wikipedia.org/wiki/Case-sensitivehttp://en.wikipedia.org/wiki/Preprocessorhttp://en.wikipedia.org/wiki/Control_flowhttp://en.wikipedia.org/wiki/Keyword_(computer_programming)http://en.wikipedia.org/wiki/Operator_precedencehttp://en.wikipedia.org/wiki/Operator_precedencehttp://en.wikipedia.org/wiki/Wikipedia:Please_clarifyhttp://en.wikipedia.org/wiki/Wikipedia:Please_clarifyhttp://en.wikipedia.org/wiki/Dataflow_languagehttp://en.wikipedia.org/wiki/Dataflow_languagehttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Netlisthttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/VLSIhttp://en.wikipedia.org/wiki/Mask_sethttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Bitstreamhttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/Phil_Moorbyhttp://en.wikipedia.org/w/index.php?title=Prabhu_Goel&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=Prabhu_Goel&action=edit&redlink=1http://en.wikipedia.org/wiki/Gateway_Design_Automationhttp://en.wikipedia.org/wiki/Case-sensitivehttp://en.wikipedia.org/wiki/Preprocessorhttp://en.wikipedia.org/wiki/Control_flowhttp://en.wikipedia.org/wiki/Keyword_(computer_programming)http://en.wikipedia.org/wiki/Operator_precedencehttp://en.wikipedia.org/wiki/Operator_precedencehttp://en.wikipedia.org/wiki/Wikipedia:Please_clarifyhttp://en.wikipedia.org/wiki/Dataflow_languagehttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Netlisthttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/VLSIhttp://en.wikipedia.org/wiki/Mask_sethttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Bitstreamhttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/Phil_Moorbyhttp://en.wikipedia.org/w/index.php?title=Prabhu_Goel&action=edit&redlink=1http://en.wikipedia.org/wiki/Gateway_Design_Automation


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19-3) as a hard&are modeling lang!age% Nate&ay 6esign A!tomation &as p!rchased

"y ;adence 6esign Systemsin 199$% ;adence no& has f!ll proprietary rights to Nate&ays

Berilog and the Berilog/M the 6/sim!lator that &o!ld "ecome the de/facto standard (of

Berilog logic sim!lators) for the ne,t decade% riginally Berilog &as intended to descri"e and

allo& sim!lation> only after&ards &as s!pport for synthesis added%

?er#%og'

=ith the increasing s!ccess of B6at the time ;adence decided to ma+e the lang!age

availa"le for open standardi.ation%;adence transferred Berilog into the p!"lic domain !nder

the pen Berilog International (BI) (no& +no&n asAccellera) organi.ation% Berilog &as later

s!"mitted to IEEEand "ecame IEEE Standard 14@/1993 commonly referred to as Berilog/93%

In the same time frame ;adence initiated the creation of Berilog/Ato p!t standards

s!pport "ehind its analog sim!lator Spectre% Berilog/A &as never intended to "e a standalone

lang!age and is a s!"set of Berilog/A'S&hich encompassed Berilog/93%

?er#%og 2;;1

E,tensions to Berilog/93 &ere s!"mitted "ac+ to IEEE to cover the deficiencies that

!sers had fo!nd in the original Berilog standard% hese e,tensions "ecame IEEEStandard 14@/

2$$1 +no&n as Berilog/2$$1%

Berilog/2$$1 is a significant !pgrade from Berilog/93% First it adds e,plicit s!pport for

(2s complement) signed nets and varia"les% Previo!sly code a!thors had to perform signed

operations !sing a&+&ard "it/level manip!lations (for e,ample the carry/o!t "it of a simple -/

"it addition re0!ired an e,plicit description of the *oolean alge"ra to determine its correct

val!e)% he same f!nction !nder Berilog/2$$1 can "e more s!ccinctly descri"ed "y one of the

"!ilt/in operators J / O WWW% A generateOendgenerate constr!ct (similar to B6s

generateOendgenerate) allo&s Berilog/2$$1 to control instance and statement instantiation

thro!gh normal decision operators (caseOifOelse)% Using generateOendgenerate Berilog/2$$1 can

instantiate an array of instances &ith control over the connectivity of the individ!al instances%

File IO has "een improved "y several ne& system tas+s% And finally a fe& synta, additions

&ere introd!ced to improve code reada"ility (e%g% al&ays b named parameter override ;/style

f!nctionOtas+Omod!le header declaration)%
http://en.wikipedia.org/wiki/Cadence_Design_Systemshttp://en.wikipedia.org/wiki/Logic_simulatorhttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/Standardizationhttp://en.wikipedia.org/wiki/Standardizationhttp://www.ovi.org/http://en.wikipedia.org/wiki/Accellerahttp://en.wikipedia.org/wiki/Accellerahttp://en.wikipedia.org/wiki/IEEEhttp://en.wikipedia.org/wiki/Verilog-Ahttp://en.wikipedia.org/wiki/Spectre_Circuit_Simulatorhttp://en.wikipedia.org/wiki/Verilog-AMShttp://en.wikipedia.org/wiki/IEEEhttp://en.wikipedia.org/wiki/Cadence_Design_Systemshttp://en.wikipedia.org/wiki/Logic_simulatorhttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/Standardizationhttp://www.ovi.org/http://en.wikipedia.org/wiki/Accellerahttp://en.wikipedia.org/wiki/IEEEhttp://en.wikipedia.org/wiki/Verilog-Ahttp://en.wikipedia.org/wiki/Spectre_Circuit_Simulatorhttp://en.wikipedia.org/wiki/Verilog-AMShttp://en.wikipedia.org/wiki/IEEE


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42/55

Some of the typical feat!res of an B that disting!ish it from a ard&are 6escription

ang!age s!ch as Berilog or B6 are

;onstrained/random stim!l!s generation

F!nctional coverage

igher/level str!ct!res especially "8ect riented Programming

'!lti/threading and interprocess comm!nication

S!pport for 6 types s!ch as Berilog7s @/state val!es

ight integration &ith event/sim!lator for control of the design

here are many other !sef!l feat!res "!t these allo& yo! to create test "enches at a

higher level of a"straction than yo! are a"le to achieve &ith an 6 or a programming lang!age

s!ch as ;%

System Berilog provides the "est frame&or+ to achieve coverage/driven verification (;6B)%

;6B com"ines a!tomatic test generation self/chec+ing test"enches and coverage metrics to

significantly red!ce the time spent verifying a design% he p!rpose of ;6B is to

Eliminate the effort and time spent creating h!ndreds of tests%

Ens!re thoro!gh verification !sing !p/front goal setting%

eceive early error notifications and deploy r!n/time chec+ing and error analysis to

simplify de"!gging%

E6am!%e$

E,1 Ahello &orld programloo+s li+e this

modu%emain>#n#"#a%

beg#n

Rdisplay(ello &orld)>

Rfinish>end

endmodu%e

E,2 A simple e,ample of t&o flip/flopsfollo&s

modu%etoplevel(cloc+reset)> #n!u"cloc+> #n!u"reset>
http://en.wikipedia.org/wiki/Hello_world_programhttp://en.wikipedia.org/wiki/Hello_world_programhttp://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Hello_world_programhttp://en.wikipedia.org/wiki/Flip-flop_(electronics)


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regflop1>

regflop2>a%4a$b (!o$edgereset or!o$edgecloc+)

#0(reset) beg#n flop1 ^K $> flop2 ^K 1> end e%$e beg#n flop1 ^K flop2> flop2 ^K flop1> endendmodu%e

he ^K operator in Berilog is another aspect of its "eing a hard&are description

lang!age as opposed to a normal proced!ral lang!age% his is +no&n as a non/"loc+ing

assignment% Its action doesnt register !ntil the ne,t cloc+ cycle% his means that the order of the

assignments are irrelevant and &ill prod!ce the same res!lt flop1 and flop2 &ill s&ap val!es

every cloc+%

he other assignment operator K is referred to as a "loc+ing assignment% =hen K

assignment is !sed for the p!rposes of logic the target varia"le is !pdated immediately% In the

a"ove e,ample had the statements !sed the K "loc+ing operator instead of ^K flop1 andflop2 &o!ld not have "een s&apped% Instead as in traditional programming the compiler &o!ld

!nderstand to simply set flop1 e0!al to flop2 (and s!"se0!ently ignore the red!ndant logic to set

flop2 e0!al to flop1%)

E, An e,ample co!ntercirc!it follo&s

modu%e6iv2$, (rst cl+ cet cep co!nt tc)>// &I&"E 'Di(ide)*y)2$ Co+nter ,it# ena*les'// ena*le CE- is a cloc. ena*le only

// ena*le CE& is a cloc. ena*le and// ena*les t#e &C o+tp+t// a co+nter +sin t#e Verilo lan+ae

!arame"ersi.e K 3>!arame"erlength K 2$>#n!u"rst>// ese inp+ts/o+tp+ts represent
http://en.wikipedia.org/wiki/Counterhttp://en.wikipedia.org/wiki/Counter


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#n!u"cl+>// connections to t#e mod+le#n!u"cet>#n!u"cep>ou"!u"Csi.e/1$D co!nt>

ou"!u"tc>regCsi.e/1$D co!nt>// 0inals assined

// ,it#in an al,ays// 1or initial*loc.

// m+st *e of type re

4#retc>// Ot#er sinals are of type ,ire// e al,ays statement *elo, is a parallel

// e3ec+tion statement t#at

// e3ec+tes any time t#e sinals// rst or cl. transition from lo, to #i#

a%4a$b (!o$edgecl+ or!o$edgerst) #0(rst)// is ca+ses reset of t#e cntr co!nt ^K _si.e_1"$``> e%$e #0(cet VV cep)// Ena*les *ot# tr+e beg#n #0(co!nt KK length/1) co!nt ^K _si.e_1"$``> e%$e co!nt ^K co!nt J 1"1>

end

// t#e (al+e of tc is contin+o+sly assined// t#e (al+e of t#e e3pression

a$$#gntc K (cet VV (co!nt KK length/1))>endmodu%e

E6&: An e6am!%e o0 de%a$:

%%%

rega " c d>4#ree>%%%a%4a$b(" ore) beg#n a K " V e> " K a "> 3 c K ">


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d K 4 c e> end

he al&ays cla!se a"ove ill!strates the other type of method of !se i%e% the al&ays cla!se

e,ec!tes any time any of the entities in the list change i%e% the " or e change% =hen one of these

changes immediately a is assigned a ne& val!e and d!e to the "loc+ing assignment " is

assigned a ne& val!e after&ard (ta+ing into acco!nt the ne& val!e of a%) After a delay of 3 time

!nits c is assigned the val!e of " and the val!e of c e is t!c+ed a&ay in an invisi"le store% hen

after 4 more time !nits d is assigned the val!e that &as t!c+ed a&ay%

Signals that are driven from &ithin a process (an initial or al&ays "loc+) m!st "e of type reg%

Signals that are driven from o!tside a process m!st "e of type &ire% he +ey&ord reg does not

necessarily imply a hard&are register%

7.3 Con$"an"$

he definition of constants in Berilog s!pports the addition of a &idth parameter% he "asic

synta, is

^4idt# in *itsW^*ase letterW^n+m*erW

E,amples

12h12 / e,adecimal 12 (!sing 12 "its)

2$d@@ / 6ecimal @@ (!sing 2$ "its / $ e,tension is a!tomatic)

@"1$1$ / *inary 1$1$ (!sing @ "its)

4o55 / ctal 55 (!sing 4 "its)

7.& Sn"e$#9ab%e Con$"ruc"$

here are several statements in Berilog that have no analog in real hard&are e%g%

Rdisplay% ;onse0!ently m!ch of the lang!age can not "e !sed to descri"e hard&are% he

e,amples presented here are the classic s!"set of the lang!age that has a direct mapping to real

gates%

// 5+3 e3amples ) ree ,ays to do t#e same t#in

// e first e3ample +ses contin+o+s assinment


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4#reo!t>

a$$#gno!t K sel ? a ">

// t#e second e3ample +ses a proced+re

// to accomplis# t#e same t#in

rego!t>

a%4a$b(a or" orsel)

beg#n

ca$e(sel)

1"$ o!t K ">

1"1 o!t K a>

endca$e

end

// Finally ) yo+ can +se if/else in a

// proced+ral str+ct+re

rego!t>

a%4a$b(a or" orsel)

#0(sel)

o!t K a>

e%$e

o!t K ">

he ne,t interesting str!ct!re is a transparent latch> it &ill pass the inp!t to the o!tp!t

&hen the gate signal is set for pass/thro!gh and capt!res the inp!t and stores it !pon transition

of the gate signal to hold% he o!tp!t &ill remain sta"le regardless of the inp!t signal &hile the

gate is set to hold% In the e,ample "elo& the pass/thro!gh level of the gate &o!ld "e &hen

the val!e of the if cla!se is tr!e i%e% gate K 1% his is read if gate is tr!e the din is fed to

latcho!t contin!o!sly% nce the if cla!se is false the last val!e at latcho!t &ill remain and is

independent of the val!e of din%

E67 // &ransparent latc# e3ample

rego!t>

a%4a$b(gate ordin)

#0(gate)
http://en.wikipedia.org/wiki/Transparent_latchhttp://en.wikipedia.org/wiki/Transparent_latch


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high @) cl+ goes high again 3) reset goes lo& follo&ed "y 4) set going lo&% Ass!me no set!p and

hold violations%

In this e,ample the al&ays b statement &o!ld first e,ec!te &hen the rising edge of reset

occ!rs &hich &o!ld place 0 to a val!e of $% he ne,t time the al&ays "loc+ e,ec!tes &o!ld "ethe rising edge of cl+ &hich again &o!ld +eep 0 at a val!e of $% he al&ays "loc+ then e,ec!tes

&hen set goes high &hich "eca!se reset is high forces 0 to remain at $% his condition may or

may not "e correct depending on the act!al flip flop% o&ever this is not the main pro"lem &ith

this model% #otice that &hen reset goes lo& that set is still high% In a real flip flop this &ill ca!se

the o!tp!t to go to a 1% o&ever in this model it &ill not occ!r "eca!se the al&ays "loc+ is

triggered "y rising edges of set and reset / not levels% A different approach may "e necessary for

setOreset flip flops%

#ote that there are no initial "loc+s mentioned in this description% here is a split

"et&een FPNA and ASI; synthesis tools on this str!ct!re% FPNA tools allo& initial "loc+s

&here reg val!es are esta"lished instead of !sing a reset signal% ASI; synthesis tools dont

s!pport s!ch a statement% he reason is that an FPNAs initial state is something that is

do&nloaded into the memory ta"les of the FPNA% An ASI; is an act!al hard&are

implementation%

7.5 Initial Vs Always:

here are t&o separate &ays of declaring a Berilog process% hese are the a%4a$and

the #n#"#a%+ey&ords% he a%4a$+ey&ord indicates a free/r!nning process% he #n#"#a%+ey&ord

indicates a process e,ec!tes e,actly once% *oth constr!cts "egin e,ec!tion at sim!lator time $

and "oth e,ec!te !ntil the end of the "loc+% nce an a%4a$"loc+ has reached its end it is

resched!led (again)% It is a common misconception to "elieve that an initial "loc+ &ill e,ec!te

"efore an al&ays "loc+% In fact it is "etter to thin+ of the #n#"#a%/"loc+ as a special/case of

the a%4a$/"loc+ one &hich terminates after it completes for the first time%

//E3amples

#n#"#a%

beg#n a K 1>// ;ssin a (al+e to re a at time $ 1>// 4ait < time +nit " K a>// ;ssin t#e (al+e of re a to re *


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enda%4a$b(a or")// ;ny time a or * C!;NGE: r+n t#e processbeg#n

#0(a)

c K "> e%$e d K ">end// Done ,it# t#is *loc.: no, ret+rn to t#e top 1ie t#e = e(ent)controla%4a$b(!o$edgea)// R+n ,#ene(er re a #as a lo, to #i# c#ane a ^K ">

hese are the classic !ses for these t&o +ey&ords "!t there are t&o significant additional

!ses% he most common of these is an a%4a$+ey&ord &itho!t the F-...sensitivity list% It is

possi"le to !se al&ays as sho&n "elo&

a%4a$

beg#n// ;l,ays *eins e3ec+tin at time $ and NEVER stops

cl+ K $>// 0et cl. to $

1>// 4ait for < time +nit

cl+ K 1>// 0et cl. to // 4ait < time +nit

end// >eeps e3ec+tin ) so contin+e *ac. at t#e top of t#e *ein

he a%4a$+ey&ord acts similar to the ; constr!ct 4#%e-1 G..in the sense that it &ill

e,ec!te forever%

he other interesting e,ception is the !se of the #n#"#a%+ey&ord &ith the addition of

the 0ore(er+ey&ord%

7.6 Race Condition

he order of e,ec!tion isnt al&ays g!aranteed &ithin Berilog% his can "est "e

ill!strated "y a classic e,ample% ;onsider the code snippet "elo&

#n#"#a%

a K $>#n#"#a%

" K a>#n#"#a%

beg#n


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1> Rdisplay(Bal!e aK" Bal!e of "K"a")> end

=hat &ill "e printed o!t for the val!es of a and "? 6epending on the order of e,ec!tion of the

initial "loc+s it co!ld "e .ero and .ero or alternately .ero and some other ar"itrary !ninitiali.ed

val!e% he Rdisplay statement &ill al&ays e,ec!te after "oth assignment "loc+s have completed

d!e to the 1 delay%

5%5 O!era"or$

#ote hese operators are notsho&n in order of precedence%

*it&ise

ogical

ed!ction


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Arithmetic

elational

Shift


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7.8 System Tasks:

System tas+s are availa"le to handle simple IO and vario!s design meas!rement f!nctions% All

system tas+s are prefi,ed &ith to disting!ish them from !ser tas+s and f!nctions% his section

presents a short list of the most often !sed tas+s% It is "y no means a comprehensive list%

Rdisplay / Print to screen a line follo&ed "y an a!tomatic ne&line%

R&rite / =rite to screen a line &itho!t the ne&line%

Rs&rite / Print to varia"le a line &itho!t the ne&line%

Rsscanf / ead from varia"le a format/specified string% (Berilog/2$$1)

Rfopen / pen a handle to a file (read or &rite)

Rfdisplay / =rite to file a line follo&ed "y an a!tomatic ne&line%

Rf&rite / =rite to file a line &itho!t the ne&line%

Rfscanf / ead from file a format/specified string% (Berilog/2$$1)

Rfclose / ;lose and release an open file handle%

Rreadmemh / ead he, file content into a memory array%

Rreadmem" / ead "inary file content into a memory array%

Rmonitor / Print o!t all the listed varia"les &hen any change val!e%

Rtime / Bal!e of c!rrent sim!lation time%

Rd!mpfile / 6eclare the B;6 (Bal!e ;hange 6!mp) format o!tp!t file name%

Rd!mpvars / !rn on and d!mp the varia"les%
http://en.wikipedia.org/wiki/Value_change_dumphttp://en.wikipedia.org/wiki/Value_change_dump


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REERENCES

C1D %Zang %6ing #%i and Z%M%N!oTFPNA/"ased design and implementation of red!ced

AES algorithm IEEE Inter%;onf% ;hal Envir Sci ;om Engin(;ES;E)%Bol%$2 Iss!e%3/4 pp%45/

5$ !n 2$1$%

C2D A%'%6eshpande '%S%6eshpande and 6%#%


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C4D i"eratori%'%tero%F%*onadero%%;% and ;astineira%% TAES/12- ;ipher%igh Speed o&

;ost FPNA Implementation IEEE ;onf% So!thern Programma"le

ogic(SP)vol%$@iss!e%$5pp%193/19-!n% 2$$5%

C5D A"delhalim%'%*% Aslan%%

Documentation 122

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