DØ Collaboration Meeting October 10, 2003 1 DØ RunIIb Trigger Upgrade Vivian O’Dell, FNAL for...
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Transcript of DØ Collaboration Meeting October 10, 2003 1 DØ RunIIb Trigger Upgrade Vivian O’Dell, FNAL for...
DØ Collaboration MeetingOctober 10, 2003
1
DØ RunIIb Trigger Upgrade
Vivian O’Dell, FNALfor the DØ Trigger Upgrade Group
DØ Collaboration MeetingOctober 10, 2003
2
Run IIb Trigger Upgrades
Strategy and Motivation Latest Luminosity Predictions Basic trigger upgrade strategy
Technical progress
Installation/Commissioning plans
Summary
DØ Collaboration MeetingOctober 10, 2003
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Run IIb Luminosity Projections
0
50
100
150
200
250
300
3 4 5 6 7 8 9 10Start of Fiscal Year
~1.6e32
~2.8e32Accelerator draft plan:Peak luminosities
Pea
k Lu
min
osity
(x1
030cm
-2se
c-1)
You are herePeak FY03 ~4.5e31
DØ Collaboration MeetingOctober 10, 2003
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Core Trigger Menu Simulations
Total L1 bandwidth budget= ~3 kHz
Total rate: ~15kHz ~30kHz ~3.2kHz
Additional headroom available from
• topological cuts available in upgraded L1cal
•Higher mu pT threshold with upgraded CTT
T r i g g e r E x a m p l e P h y s i c s C h a n n e l s
L 1 R a t e ( k H z )
( n o u p g r a d e ) L = 1 E 3 2
L 1 R a t e ( k H z )
( n o u p g r a d e ) L = 2 E 3 2
L 1 R a t e ( k H z ) ( w i t h
u p g r a d e ) E M ( 1 E M T T > 1 0 G e V )
eW , S U S Y ,
jjeWH
0 . 6 5 1 . 3 0 . 7
D i - E M ( 1 E M T T > 7 G e V , 2 E M T T > 5 G e V )
Z e e , W , S U S Y
Z H e e j j
0 . 2 5 0 . 5 0 . 1
M u o n ( m u o n p T > 1 1 G e V + C F T T r a c k )
W W H j j
3 6 0 . 4
D i - M u o n s ( 2 m u o n s p T > 3 G e V + C F T T r a c k s )
Z J
Z H j j
0 . 2 0 . 4 < 0 . 1
E l e c t r o n + J e t s ( 1 E M T T > 7 G e V , 2 H a d T T > 5 G e V )
W H e + j e t s t t e + j e t s
0 . 4 0 . 8 0 . 2
M u o n + J e t ( m u o n p T > 3 G e V , 1 H a d T T > 5 G e V )
W H + j e t s t t + j e t s
< 0 . 1 < 0 . 1 < 0 . 1
J e t + M E T ( 2 T T > 5 G e V , M i s s i n g E T > 1 0 G e V )
bbZH , S U S Y
1 . 1 2 . 1 0 . 8
M u o n + E M ( m u o n s p T > 3 G e V + C F T t r a c k + 1 E M T T > 5 G e V )
H W W , Z Z < 0 . 1 < 0 . 1 < 0 . 1
S i n g l e I s o l a t e d T r a c k ( 1 I s o l a t e d C F T t r a c k , p T > 1 0 G e V )
H W 8 . 5 1 7 1 . 0
D i - T r a c k ( 1 i s o l a t e d t r a c k s p T > 1 0 G e V , 2 t r a c k s p T > 5 G e V , 1 m a t c h e d w i t h E M e n e r g y )
H S U S Y
0 . 6 0 . 6 < 0 . 1
1E32 2E32 2E32
DØ Collaboration MeetingOctober 10, 2003
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Ingredients of the Trigger Upgrade
Level 1 Calorimeter trigger upgrade
sharpens turn-on trigger thresholds more topological cuts
Calorimeter track-match fake EM rejection tau trigger
L1 Tracking trigger upgrade improved tracking rejection esp. at higher occupancies inputs to Calorimeter track-mathc
Level 2 L2 Processor upgrades for more complex algorithms Silicon Track Trigger expansion
More processing power use trigger inputs from new silicon layer 0
Upgrade/maintain DAQ/Online systems
DØ Collaboration MeetingOctober 10, 2003
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The L1Cal Team
Saclay ADFs/ADF Timing/Splitters Physicists: J.Bystricky, P.LeDu*, E.Perez Engineers: D.Calvet, Saclay Staff
Columbia/Nevis TABs/GABs/VME-SCL Physicists: H.Evans*, J.Parsons, J.Mitrevski Engineers: J.Ban, B.Sippach, Nevis Staff
Michigan State Framework/Online Software Physicists: M.Abolins* Engineers: D.Edmunds, P.Laurens
Northeastern Online Software Physicists: D.Wood
Fermilab Test Waveform Generator Engineers: G.Cancelo, V.Pavlicek, S.Rapisarda
* L1Cal Project Leaders
DØ Collaboration MeetingOctober 10, 2003
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Run IIa Limitations
Poor Et-res. (Jet,EM,MEt) slow turn-on curves
5 Gev TT thresh 80% eff. for 40 GeV jets
low thresholds unacceptable rates at L = 21032
2.1(L = 2e32)
ZH vvbbJet Trigger2 TT>5 GeV+ MEt>10 GeV
1.3W evEM Trigger1 TT>10 GeV
Rate (kHz)Phys. ChanTrigger
L1 Rate Limit<5 kHz
L1 Rate Limit<5 kHz
DØ Collaboration MeetingOctober 10, 2003
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Run IIb Solutions (2)
Solution for Rates: Sliding Windows Algorithm
Et cluster local max. search on 4032 () TT grid
Jet, EM & Tau algo’s Better calc of missing Et Topological Triggers Jet, EM clust output for
matching with L1 Tracks Benefits
2.5–3 Jet Rate reduction at constant efficiency
ZHvvbb Rate: 2.10.8 kHz
Similar gains for EM & Tau MEt, Topological Triggers
under study
X RoI ET Cluster
Region
Data Needed for Declustering
Cand. RoI center
O O O O O
O O O O O
O O O O
O O O O O
O O O O O
RoI center used for compares
Jet Algo
X
RoI / EM cluster
EM Isolation
Had Isolation
EM Algo
X
RoI / Tau cluster
EM + Had Isolation
Tau Algo
DØ Collaboration MeetingOctober 10, 2003
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Technical progress: L1Cal
ADC+digital filteringClustering
Global sums &topological
DØ Collaboration MeetingOctober 10, 2003
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Signal Splitter
Access to Real TT Data using “Splitter” Boards
designed/built by Saclay
active split of analog signals at CTFE input
4 TTs per board installed: Jan. 2003
Splitter Data no perturbation of Run
IIa L1Cal signals allows tests of digital
filter algorithm with real data
DØ Collaboration MeetingOctober 10, 2003
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~1300 components on both sides of a 14-layer class 6 PCB
VME interface& glue logic
Channel LinkSerializers
Core FPGAlogic
DC/DCconverters
AnalogSection andADCs
VME Digital Out Analog In
ADF Prototype
DØ Collaboration MeetingOctober 10, 2003
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TAB Prototype
power
Channel Link Receivers (x30)Sliding Windows
Chips (x10)
L2/L3 Output (optical)
VME/SCL
Output to GAB
Output to Cal-Track (x3)
AD
F Inputs (x30)
Global Chip
Internal Functions ~Fully TestedInternal Functions ~Fully Tested
DØ Collaboration MeetingOctober 10, 2003
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VME/SCL Board
New Comp. of TAB/GAB system
proposed: Feb 03
change control: Mar 03 Interfaces to
VME (custom protocol) not enough space on TAB
for standard VME D0 Trigger Timing (SCL) (previously part of GAB)
Why Split off from GAB simplifies system design &
maintenance allows speedy testing of
prototype TAB Prototype at Nevis: May 12
main VME & SCL functionality tested & working
serial out x9(VME & SCL)
VME interface
SCL interface
local osc’s & f’out (standalone runs)
Fully TestedFully Tested
DØ Collaboration MeetingOctober 10, 2003
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TAB/GAB Test Card
TAB/GAB Data Rates TAB: LVDS 424 MHz
(channel link) GAB: LVDS 636 MHz
(stratix)
Test Card at Nevis Start Designmid-Aug Board at Nevis 29-
Sep Cost ~$2K
Status ADF-to-TAB xmit tested
before integration Will test TAB-to-GAB
before sending out GAB for fabrication
Channel Link
TAB(ADF sim)
power
VME / SCL
Cyclone
Stratix S10LVDS
xmit/rcvr TAB(GAB in sim)
Loopback
DØ Collaboration MeetingOctober 10, 2003
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Prototype Integration Tests
Want to start “System Tests” asap need to check cross-group links early
First Tests with Prototypes starting now SCL VME/SCL TAB, ADF BLS Data (split) ADF TAB Flexible, staged schedule allows components to be
included as they become available
Set up semi-permanent Test Area (thanks to J. Anderson’s group at FNAL)
outside of Movable Counting House connection to SCL, split data signals allows L1Cal tests without disturbing Run IIa data
taking
DØ Collaboration MeetingOctober 10, 2003
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Technical progress: L1Cal-Track Trigger
University of Arizona
J. Steinberg D. Tompkins C. Leeman N. Wallace B. Gmyrek K. Johns E. Varnes
Exploit new L1Cal trigger
Improve Run IIa matching granularity x8
Needed in triggers for Higgs searches
electrons in WH and H W*W modes
taus in H and H+
Fake EM rejection is improved by ~x2
Fake rejection is improved by ~x10
DØ Collaboration MeetingOctober 10, 2003
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Hardware Progress
Block diagram of new Univeral Flavor Board: only really new board needed for L1 cal-trackFlavor board (daughter)
MTCxx (mother)
DØ Collaboration MeetingOctober 10, 2003
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L1CalTrack Status
MTCxx (Trigger Cards) Preproduction design complete Layout and final checks in progress Goal is to submit in November 03
UFB (Flavor Board) Prototypes in hand Boundary scan and downloading OK Receiver/transmitter testing in progress L1MU “05” algorithm implemented in Stratix
EP1S20F780C7 (simulated but not tested) H algorithm implementation in progress
MTCM (Crate Manger) Not started, but only minimal changes to the
existing design
DØ Collaboration MeetingOctober 10, 2003
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L1CalTrack Status
Infrastructure VME crates, processors, power supplies, cables in
hand L1CTT to L1CalTrack cables being installed this
weekend (not terminated) Rack space in MCH1 identified (but not settled)
Commissioning Plan is to use spare L1MU cards in L1CalTrack
crates to establish communication with TF and L3 Replace spares with L1CalTrack cards as available
Simulator Work has started writing the L1CalTrack package
and integrating it into the D0 Trigger Simulator
DØ Collaboration MeetingOctober 10, 2003
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L1CTT Upgrade
Boston Univ M. Narain G. Redner S. Wu
Fermilab M. Johnson J. Olson F. Borcherding
Notre Dame M. Hildreth
Manchester L. Han T. Wyatt
Kansas G. Wilson
Brown R. Partridge
Indiana K. Stevenson
DØ Collaboration MeetingOctober 10, 2003
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Technical Progress: L1Central Tracking
Trigger Tracking trigger
rates sensitive to occupancy
Upgrade stategy: Narrow tracker
roads by using individual fiber hits (singlets) rather than pairing adjacent fibers (doublets)
Cal-track matching
DØ Collaboration MeetingOctober 10, 2003
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L1 CTT Implementation
Digital Front End Axial (DFEA) daughter cards get replaced with new layout with larger FPGA’s (Xilinx Virtex-II XC2V6000)
Only 80 daughter cards get replaced; rest of Run IIa system remains intact
Baseline algorithms compiled; occupy ~40% of the resources of the XC2V6000’s.
4.1
25”
7.8”
40 m
m(1
.57
”)
4.1
25”
7.8”
40 m
m(1
.57
”)
DFEA layout with new FPGA footprints
DØ Collaboration MeetingOctober 10, 2003
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Run IIb L1CTT Progress
Implemented prototype firmware (Boston U) Includes equation files from all 4
momentum bins pT>10 GeV, 5<pT<10 GeV, 3<pT<5 GeV, 1.5<pT<3
GeV
Resources used: DFEA logic is implemented in two FPGAs
Prototype DFEA:
•10/17/03 prototype PCB returned
•10/31/03 first prototype assembled.
•11/30/03 prototype fully tested
DØ Collaboration MeetingOctober 10, 2003
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L2eta Upgrade
6U boardCompact PCI
9U board64 bit
<2MHzVME
FPGA
EC
L D
rive
rs
128 bits~20 MHzMBus
32 bits66 MHz (max)Local bus64 bits
33 MHzPCI
J1
J2
J3
J5
J4
PLX9656
UII
Dri
vers
Dri
vers
Clk(s)/roms
•Run IIb strategy: purchase additional, more powerful commercial processors as late as reasonably possible.
DØ Collaboration MeetingOctober 10, 2003
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Silicon Track Trigger for Run IIb
STT upgrade needed to accommodate new L0?
New L0 fits within baseline Run IIb upgrade
even without L0, increase processing power for higher occupancy
Modest STT upgrade requires small quantity of same boards that are used in Run IIa.
Readout layers 0,1,2,3,5
Technical Progress: VME Transition
Modules procured Concern about
obsolescence
Other procurements awaiting Layer 0 decision
DØ Collaboration MeetingOctober 10, 2003
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Installation
Words here about trigger installation want to install as early as possible
most benefits want to install during machine shutdown
where do we need the most access
also repeat a little what we have in “the document” on installation
DØ Collaboration MeetingOctober 10, 2003
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Summary
Lots of trigger progress and potential Trigger workshop this weekend
(Saturday/Sunday) url
trigger upgrade is being redefined in light of run2b prospects
installation schedule new project approval will be happening in the next
month workshop this weekend
DØ Collaboration MeetingOctober 10, 2003
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Backup slides follow
DØ Collaboration MeetingOctober 10, 2003
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Fake rate vs.luminosity
Even at modest occupancies, the high-pT single track trigger would fire at >15 kHZ
Nominal 2E32
@ 396 ns
(1 high pT track) (1 high+1 medium
pT)
4E32 @ 396 ns
Green points = Run IIa CTT
Red points = Run IIb CTT
DØ Collaboration MeetingOctober 10, 2003
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Run IIb L1CTT: Granularity
Use full fiber resolution to restrict roads
Run IIa Run IIb
DØ Collaboration MeetingOctober 10, 2003
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L1CalTrack System
Uses largely same hardware as existing L1muon modest cost and effort required