DLD LAB MANUAL · 2019-08-17 · A breadboard is a prototyping board made of insulated material...

LABORATORY MANUAL

Department of Computer Science and Engineering

Digital Logic Lab (REC-351) Manual (CS, III SEM)

Department of Computer Science & Engineering

Sr.

No.

Title of experiment

Corresponding CO

1.

Verification of Logic Gates. C207.1

2. Implementation of given logical function using universal

Logic gates.

C207.1

3.

Design and implementation of Adders and Subtractors C207.2

4.

Design and implementation of Code Converters C207.2

5.

Design and implementation of Magnitude Comparators C207.2

6.

Design and implementation of 4 bit Parallel Adder/ Subtractor C207.2

7.

Design and implementation of encoders and decoders C207.2

8. Design and implementation of Multiplexers and De-

Multiplexers

C207.2

9.

Design and implementation of shift registers (SISO,SIPO,PISO,PIPO)

C207.3

10.

Design and implementation of Synchronous Counters C207.3

11.

Design and implementation of Asynchronous Counters

Design and implementation of Synchronous Counters

C207.3

12. Design and implementation of R-S Latch and D Latch C207.4

Content Beyond Syllabus

1.

Design and implementation of seven segment display

Decoder.

C207.2

LIST OF EXPERIMENTS



INTRODUCTION

Introduction to electronic lab components or equipment’s Basic purpose of this electronic lab

components article is to introduce you with electronics lab components and their use in

electronics lab experiments. In electronic circuit lab, the primary piece of equipment that you

will be dealing with is the Trainer Board. A trainer board is essentially a collection of most of the

electronic lab components that are typically required when working with logic circuits. There is

trainer boards present in the lab. All equipped with the following.

1. Breadboard

2. Power Supply for ICs

3. Logic Switches

4. LED output

5. Seven Segmented Display

6. Clock

Electronics lab components: 1. The Breadboard:

A breadboard is a prototyping board made of insulated material with a perforated top in

which wires and components can be inserted. The perforations in the board are connected in a

special manner through internal wiring at the bottom of the board. The fact that wires and

components are inserted, and not soldered, means they can be easily removed, replaced or

have their interconnections altered easily.

2. Power Supply for ICs

In electronics lab components, the components that you will be dealing with mostly are

Integrated Circuits (ICs). There are several different types of ICs, each with its unique

functionality like7400, 7402,7404,7408,7432 and 7486 etc. ICs are active elements. This

means that they require to be “powered up” before they can be used. Therefore, every IC, no

matter what its functionality, will always have two special pins labelled Vcc and Ground (or

Gnd). Ground is to be connected to the Gnd supply of the trainer board while Vcc is to be

connected to the 5V supply.

http://microcontrollerslab.com/ups-uninterruptible-power-supply-circuit-diagram/

http://microcontrollerslab.com/light-emitting-diode-working/



3. Logic Switches

Logic switches are the basic building blocks of electronics lab components. The inputs to

a logic circuit are composed of a collection of ON/OFF signals. An ON signal (or logic ‘1’) is

generated by applying +5V to an input pin while an OFF signal (or logic ‘0’) is generated by

applying 0V to an input pin. When the switch is closed (by moving the switch down), it

outputs +5V while when the switch is opened (by moving it up), the output of the same pin is

now 0V. This is called “Positive Logic Connection”.

4. LED output

The outputs of logic circuits, like the inputs, are composed of ON/OFF signals. They can be

verified by using the LEDs available on the trainer boards. LED stands for Light Emitting

Diode; a two terminal device only conducts in one direction, as is the case with a typical

diode. They convert electrical energy into light energy. To test an output of an IC, connect it

directly to the input terminal of an LED made available on the trainer board. If an LED turns

on, then the output state at that pin is ON (+5V). If it remains off, then the pin is in

OFF state (0V).

5. Seven Segmented Display

The seven-segmented display allows outputs to be viewed in decimal form. It takes 4 inputs

(binary) and, depending on their state, turns on LEDs in the display to show the corresponding

digit. For example, if the input to the display is 0111, then the display will show the

number 7.

6. Clock

The trainer board provides a square wave that oscillates between a minima of 0V and a

maxima of 5V. This is called a clock. The clock is used to drive “sequential” logic devices,

which you will come across in the later labs. Essentially, this clock is used for the same

purpose as the clock in you computers. The trainer board provides the option of varying the

frequency of this clock, but the amplitude is fixed.



PREFACE

This laboratory manual is designed to have students experience on how to use & deploy

Electronics projects using Digital Trainer Kit. The idea of writing this lab manual came when

we realized that our students do not have a single, properly structured lab manual which

makes them aware of about Digital lab how to use Digital component & Digital trainer kit

efficiently. This Manual is therefore an attempt to fill this gap in the knowledge of the

students. Though all the efforts have been made to make this manual error free, yet some

errors might have crept in inadvertently. Suggestions from the readers for the improvement of

the manual are most welcomed.

This practical manual will be helpful for students of Computer Science & Engineering for

understanding the course from the point of view of applied aspects. Though all the efforts

have been made to make this manual error free, yet some errors might have crept in

inadvertently. Suggestions from the readers for the improvement of the manual are most

welcomed.



DO’S AND DONT’S

DO’s

1. Conform to the academic discipline of the department.

2. Enter your credentials in the laboratory attendance register.

3. Read and understand how to carry out an activity thoroughly before coming to the

laboratory.

4. Ensure the uniqueness with respect to the methodology adopted for carrying out the

experiments.

5. Shut down the machine once you are done using it.

DONT’S

1. Eatables are not allowed in the laboratory.

2. Usage of mobile phones is strictly prohibited.

3. Do not open the system unit casing.

4. Do not remove anything from the computer laboratory without permission.

5. Do not touch, connect or disconnect any plug or cable without your faculty/laboratory

technician’s permission.



GENERAL SAFETY INSTRUCTIONS

1. Know the location of the fire extinguisher and the first aid box and how to use them in

case of an emergency.

2. Report fires or accidents to your faculty /laboratory technician immediately.

3. Report any broken plugs or exposed electrical wires to your faculty/laboratory

technician immediately.

4. Do not plug in external devices without scanning them for computer viruses.


Digital Logic Lab (REC-351) Manual (CS, III SEM) Page 14

DIGITAL LOGIC DESIGN LAB FILE (REC 351)

Name

Roll No.

Section- Batch


Digital Logic Lab (REC-351) Manual (CS, III SEM) 15 | P a g e

INDEX

Experiment

No.

Experiment

Name

Date of

Conduction

Date of

Submission

Faculty

Signature



EXPERIMENT 1

VERIFICATION OF LOGIC GATES

Aim: Verification of the truth tables of logic gates using TTL ICs.

Equipment Required & Component Required:

SL.No. Equipment/Components Specification Quantity

1 Digital IC Trainer kit - 1

2 Digital Multimeter 1

3

Digital ICs

7400, 7402, 7404,

7408, 7432, 7486.

1 each

4

Patch cords

-

6

Theory:

• Details of IC used and pin configurations.

• Working of logic gates.



1. OR GATE:

OR Gate Symbol TRUTH TABLE (OR GATE)

PIN DIAGRAM:

2. AND GATE: AND Gate Symbol TRUTH TABLE (AND GATE)

INPUT A INPUT B OUTPUT Y

0 0 0

0 1 1

1 0 1

1 1 1

A B Y

0 0 0

0 1 0

1 0 0

1 1 1



PIN DIAGRAM:

3. NOT GATE: NOT Gate Symbol TRUTH TABLE (NOT GATE)

PIN DIAGRAM:

INPUT A OUTPUT

Y

0 1

1 0



4. EX-OR GATE

EX –OR Gate Symbol TRUTH TABLE (X-OR GATE)

PIN DIAGRAM:

5. NOR GATE

NOR Gate Symbol TRUTH TABLE (NOR GATE)

PIN DIAGRAM:

INPUT

A INPUT

B OUTPUT

Y

0 0 0

0 1 1

1 0 1

1 1 0


0 0 1

0 1 0

1 0 0

1 1 0



6. NAND GATE:

NAND GATE Symbol TRUTH TABLE (NAND GATE)

PIN DIAGRAM:

Pre- Experiment Questions:-


0 0 1

0 1 1

1 0 1

1 1 0



1. Explain the different types of logic gates?

2. Give the truth table of all the basic gates.

3. Which gates are known as universal Gates? And why?

4. Draw the basic logic gate circuits.



Procedure:

1. Identify the pin no’s of the given IC.

2. From the IC No. Find out the type of gate.

3. Check for the proper working of the gate.

4. Connect the circuit as per circuit diagram.

5. For all combination of input condition. Tabulate the output voltage by connecting a

voltmeter at the output end.

6. Verify it with truth Table.

7. Repeat the above procedure for all gates.

Result & Conclusion: All Logic gates are verified.

Post Experiment Questions: -

1. How do you implement the gates using diodes?

2. Implement the basic gates using universal gates.

3. What do you understand the word IC?

4. Write the Boolean equation of Basic gates.

EXPERIMENT 2



IMPLEMENTATION OF GIVEN LOGICAL FUNCTION USING UNIVERSAL LOGIC

GATES

Aim: Implementation of given logical function using universal logic gates (NAND &

NOR).

Equipment required & Component required:

SL.No. Equipments Specification Quantity



SL.No. Components Specification Quantity

1 Digital IC 7400 7402 2 each

2 Patch cords - As many

required

Theory:

• Details of IC used and pin configurations.

• Boolean functions

A: Constructing Basic gates using NAND gates.



B: Constructing Basic gates using NOR gates

Pre-Experiment Questions:

Q1. How many gates can be made with Universal gate?

Q2 .Explain AND-OR-INVERT GATE.

Q3.Explain OR-AND-INVERT GATE.

Q4.Why NAND & NOR gate is called universal gates.

Procedure:

• Identify the pins.

• Connect the circuit as per circuit diagram.

• Obtain outputs with various input combinations.

• Verify it with the Boolean function using truth table

Result & Conclusion: All logical function have been implemented & verified through truth

table.

Post Experiment Questions:-

1. Implement EX-OR gate using universal gates.

2. What are universal gates?

3. Why are they called universal gates?



EXPERIMENT 3

DESIGN AND IMPLEMENTATION OF ADDERS AND SUBTRACTORS

Aim: Design and implementation of Adders & Subtractors.

Equipment & Components Required:

SL.

No.

Equipments

Specification

Quantity



3. Components Required:

SL.

No.

Components

Specification

Quantity

1

Digital ICs

7400, 7402,

7404,

7408, 7432,

7486.

1 each

2

Patch cords

-

6

Theory:

a) To design and implement half adder and half subtractor using logic gates

HALF ADDER

CIRCUIT DIAGRAM TRUTH TABLE

INPUT A

INPUT B OUTPUTS

S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1



HALF SUBTRACTOR (TRUTH TABLE)

CIRCUIT DIAGRAM

F

ULL ADDER

b) To design and implement full adder and full subtractor using logic gates

CIRCUIT DIAGRAM

INPUT A

INPUT B OUTPUTS

D B

o 0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0



TRUTH TABLE OF FULL ADDER

INPUTS OUTPUTS

B

CIN

S

COUT

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

0 0 1 0

0

1

0

1

1 0 0 1

1

1

1

1

FULL SUBTRACTOR

CIRCUIT DIAGRAM

TRUTH TABLE

INPUTS OUTPUTS

A B BIN D BOUT

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

1 0 0 1 0




Q1 Explain the truth table of half subtractor.

Q2 How many Ex-OR, and OR gate can be used to make a half

subtractor?

Q3 Differentiate between half adder and full adder.

Q4 Differentiate between half subtractor and full subtractor.

Procedure:





Result & Conclusion: All logical circuits have been implemented & verified through truth

table.

Post-Experiment Question:

Q1What are the applications of half subtractor?

Q2What are the application of full subtractor?

Q3How many AND, OR and EX-OR gate are required to configure the full

adder?

Q4How many output are required for the implementation of a subtractor.



EXPERIMENT 4

DESIGN AND IMPLEMENTATION OF CODE CONVERTERS

Aim: Design and implementation of code converters.


SL.

No.

Equipments

Specification

Quantity



Components Required:

SL.

No.

Components

Specification

Quantity

1

Digital ICs

7400, 7402, 7404,

7408, 7432, 7486.

1 each

2

Patch cords

-

6

Theory:

A) Design Binary to Grey Code Converter

TRUTH TABLE:

| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0



1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

K-Map for G3:

K-Map for G2

K-Map for G1:



K-Map for G0:

BINARY TO GRAY CODE CONVERTOR

GRAY CODE TO BINARY CONVERTOR

TRUTH TABLE:



Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1



LOGIC DIAGRAM:



BCD TO EXCESS-3 CONVERTOR

TRUTH TABLE:

| BCD input | Excess – 3 output |

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x x

E3 = B3 + B2 (B0 + B1)



LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

X1 X2 X3 X4 A B C D

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1



A = X1 X2 + X3 X4 X1

K-Map for B:



K-Map for C:

K-Map for D:



LOGIC DIAGRAM:


Q1: Explain the design procedure for combinational circuit.

Q2: Enlist various code convertor method.

Q3: Which gate is used for gray to binary conversion.

Procedure







Result & Conclusion: All code converter have been implemented & verified through truth

table.

Post -Experiment Questions:

Q:1 What is combinational logic?

Q:2 Design a 4 bit gray code convertor.

Q.3 Design a BCD to Gray code Converter.



EXPERIMENT 5

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATORS

Aim: Design and implementation of magnitude comparators.






1

Digital ICs

7400, 7402, 7404,

7408, 7432, 7486.

1 each

2

Patch cords

-

6

THEORY: The comparison of two numbers is an operator that determine one number is greater

than, less than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determine their relative magnitude. The outcome of the

comparator is specified by three binary variables that indicate whether A>B, A=B (or) A<B.

A = A3 A2 A1 A0

B = B3 B2 B1 B0

The equality of the two numbers and B is displayed in a combinational circuit designated by the

symbol (A=B).

This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits

starting from most significant position. A is 0 and that of B is 0.We have A<B, the sequential

comparison can be expanded as

A>B = A3B31 + X3A2B21 + X3X2A1B 11 + X3X2X1A0B01

A<B = A31B3 + X3A21B2 + X3X2A1 1B1 + X3X2X1A0 1B0 The same circuit can be used to compare the relative magnitude of two BCD digits.

Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)



x3 x2 x1 x0

A1 A0 B1 B0 A > B A = B A < B

0 0 0 0 0 1 0

0 0 0 1 0 0 1

0 0 1 0 0 0 1

0 0 1 1 0 0 1

0 1 0 0 1 0 0

0 1 0 1 0 1 0

0 1 1 0 0 0 1

0 1 1 1 0 0 1

1 0 0 0 1 0 0

1 0 0 1 1 0 0

1 0 1 0 0 1 0

1 0 1 1 0 0 1

1 1 0 0 1 0 0

1 1 0 1 1 0 0

1 1 1 0 1 0 0

1 1 1 1 0 1 0



LOGIC DIAGRAM:

Pre-Experiment Question:

Q:1 What is magnitude comparators.

Q:2 Draw and explain 4 bit magnitude comparator.

Q:3 Differentiate between 2 bit,3 bit and 4 bit comparators.

Q:4 how many inputs are required for a magnitude comparator.

Procedure:









Result & Conclusion: Magnitude comparators have been implemented & verified through

truth table.


Q:1. Design a 8 bit comparator using two 7485Ics.

Q:2 Design a 5 bit comparator using IC-7485.

Q:3 Explain the use of comparator.

Q:4 How many inputs & outputs are required in magnitude comparators.



EXPERIMENT NO. 6 : DESIGN OF 4-BIT ADDER AND SUBTRACTOR

AIM: To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1

2. EX-OR GATE IC 7486 1

3. NOT GATE IC 7404 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can

be constructed with full adders connected in cascade, with the output carry from each full adder

connected to the input carry of next full adder in chain. The augends bits of ‘A’ and the addend

bits of ‘B’ are designated by subscript numbers from right to left, with subscript 0 denoting the

least significant bits. The carries are connected in chain through the full adder. The input carry to

the adder is C0 and it ripples through the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data

input ‘B’ and the corresponding input of full adder. The input carry C0 must be equal to 1 when

performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one common binary

adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When

M=1, it becomes subtractor. 4 BIT BCD ADDER:



Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from

a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than

19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in

BCD and should appear in the form listed in the columns.ABCD adder that adds 2 BCD digits

and produce a sum digit in BCD. The 2 decimal digits, together with the input carry, are first

added in the top 4 bit adder to produce the binary sum.

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM: 4-BIT BINARY ADDER



LOGIC DIAGRAM: 4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:

4-BIT BINARY ADDER/SUBTRACTOR



TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1


Q1 Explain the truth table of parallel subtractor.

Q2 Differentiate between 4 bit parallel adder and full adder.

Q3 What is the need of parallel ADDER/SUBTRACTOR?

Procedure:





Result & Conclusion: All logical circuits have been implemented & verified through truth

table.


Q1What are the applications of parallel adder?

Q2What are the application of parallel subtractor?

Q3How many AND, OR and EX-OR gate are required to configure the parallel

adder?



.

EXPERIMENT 7

DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS

Aim: Design and implementation of encoders and decoders






1

Digital ICs

7400, 7402,

7404,

7408, 7432,

7486.

1 each

2 Patch cords - 6

Theory:

ENCODER: An encoder is a digital circuit that perform inverse operation of a decoder. An encoder has 2n

input lines and n output lines. In encoder the output lines generates the binary code corresponding

to the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three

output that generate the corresponding binary code. In encoder it is assumed that only one input

has a value of one at any given time otherwise the circuit is meaningless. It has an ambiguila that

when all inputs are zero the outputs are zero. The zero outputs can also be generated when D0 =

1. DECODER:

A decoder is a multiple input multiple output logic circuit which converts coded input into coded

output where input and output codes are different. The input code generally has fewer bits than

the output code. Each input code word produces a different output code word i.e there is one to

one mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded

information is present as n input producing 2n possible outputs. 2n output values are from 0

through out 2n – 1.



a) Encoder using logic gates:

LOGIC DIAGRAM FOR ENCODER:

INPUT OUTPUT

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0

0 0 1 0 0 0 0 0 1 1

0

0 0 0 1 0 0 0 1 0 0

0

0 0 0 0 1 0 0 1 0 1

0

0 0 0 0 0 1 0 1 1 0

0

0 0 0 0 0 0 1 1 1 1



(b). Decoder using logic gates

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

LOGIC DIAGRAM FOR DECODER:

Pre experimental questions:

Q1: Difference between Encoder and Decoder.

Q2: Explain priority Encoder.



Q3: Which gates are building gates of Encoder.

Q4: Which IC is used in decoder.

Procedure:



Result & Conclusion: Decoder & Encoder have been implemented & verified through

truth table.

Post experimental question:

Q:1 Design a 5 to 32 decoder using one 2 to 4 and four 3 to 8 decoder IC’S.

Q:2 Write a note on BCD to decimal decoder.

Q:3 How invalid BCD code is converted into valid BCD code.

Q:4 Write the application of Encoder/Decoder.



EXPERIMEN 8

DESIGN AND IMPLEMENTATION OF MULTIPLEXERS AND

DE- MULTIPLEXERS

Aim: Design and implementation of Multiplexers and De-multiplexers

Equipments & Components Required:




3. Components Required:


1

Digital ICs

7400, 7402,

7404,

7408, 7432,

7486.

1 each

2 Patch cords - 6

Theory:

MULTIPLEXER: Multiplexer means transmitting a large number of information units over a smaller number of

channels or lines. A digital multiplexer is a combinational circuit that selects binary information

from one of many input lines and directs it to a single output line. The selection of a particular

input line is controlled by a set of selection lines. Normally there are 2n input line and n selection

lines whose bit combination determine which input is selected. DEMULTIPLEXER: The function of Demultiplexer is in contrast to multiplexer function. It takes information from

one line and distributes it to a given number of output lines. For this reason, the demultiplexer is

also known as a data distributor. Decoder can also be used as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select

lines enable only one gate at a time and the data on the data input line will pass through the

selected gate to the associated data output line.



a) 4:1 MULTIPLEXER

FUNCTION TABLE:

S1 S0 INPUTS Y

0 0 D0 → D0 S1’ S0’

0 1 D1 → D1 S1’ S0

1 0 D2 → D2 S1 S0’

1 1 D3 → D3 S1 S0

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

TRUTH TABLE:

LOGIC DIAGRAM

S1 S0 Y = OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3



FOR MULTIPLEXER:

b) 1 to 4 DEMULTIPLEXERS:

FUNCTION TABLE:

S1 S0 INPUT

0 0 X → D0 = X S1’ S0’

0 1 X → D1 = X S1’ S0

1 0 X → D2 = X S1 S0’

1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0



BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXERS:

TRUTH TABLE:

INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

LOGIC DIAGRAM FOR DEMULTIPLEXER



Pre-Experiment questions:

Q1. Difference between multiplexer & demultiplexer.

Q2. What are the applications of multiplexer

Q3.What are the applications of Demultiplexer.

Procedure:



3. Verify it with truth Table.

Result & Conclusion: All Multiplexer have been implemented & verified through truth table.

Post-Experiment questions:

Q:1 Explain the working of 8:1 Mux.

Q:2 Design a 8:1 Mux using two 4:1 Mux.

Q:3 Design 16:1 Mux. Using five 4:1 Mux.

Q:4 How many select lines are in 4:1,8:1 & 16:1 Multiplexer



EXPERIMENT 9

DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS (SISO, SIPO, PISO and

PIPO)

Aim: Design and implementation of shift registers

(i) Serial in serial out Shift Register

(ii) Serial in parallel out Shift Register

(iii) Parallel In Serial out

(iv) Parallel in Parallel out

Equipments & Components Required:




Sl.No. COMPONENT SPECIFICATION QTY.

1. D Flip Flop IC 7474 2

3. IC Trainer Kit - 1

4. Patch Cords - 15

Theory: A register is capable of shifting its binary information in one or both directions is

known as shift register. The logical configuration of shift register consist of a D-Flip flop

cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive

common clock pulses which causes the shift in the output of the flip flop. The simplest possible

shift register is one that uses only flip flop. The output of a given flip flop is connected to the

input of next flip flop of the register. Each clock pulse shifts the content of register one bit

position to right.



LOGIC DIAGRAM

(i) SERIAL IN SERIAL OUT:

TRUTH TABLE:

Serial in Serial out

CLK

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1

ii) SERIAL IN PARALLEL OUT



LOGIC DIAGRAM

TRUTH TABLE:

OUTPUT

CLK DATA

QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1



PARALLEL IN SERIAL OUT:

LOGIC DIAGRAM:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1



PARALLEL IN PARALLEL OUT

LOGIC DIAGRAM:

TRUTH TABLE

DATA INPUT OUTPUT

CLK

DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0


Q:1 State the features of IC 7495.

Q:2 State the features of IC 74195.

Q:3 what are different type of shift registers.

Q:4 How can parallel data can be taken out of a shift register simultaneously.?

Procedure:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.



3. Observe the output and verify the truth table.

Result: All Shift registers have been implemented & verified through truth table.

Post-Experiment Questions

Q:1 How can we use shift registers in serial communications? Explain.

Q:2 List the ICs which are used as 8 bit SISO, SIPO, PISO, PIPO modes and as a

bidirectional shift register.

Q:3 What do you mean by parallel load of a shift register.

Q:4 Which shift register has Q and Output of one stage is not connected with input of next

stage.



Experiment 10

DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER

Aim: Design and implementation of Synchronous Counters

Equipment Required & Components Required:





1

Digital ICs

7400, 7402, 7404,

7408, 7432, 7486.

1 each

2 Patch cords - 6 Theory: A counter is a register capable of counting number of clock pulse arriving at its clock

input. Counter represents the number of clock pulses arrived. An up/down counter is one that is

capable of progressing in increasing order or decreasing order through a certain sequence. An

up/down counter is also called bidirectional counter. Usually up/down operation of the counter is

controlled by up/down signal. When this signal is high counter goes through up sequence and

when up/down signal is low counter follows reverse sequence.

a) 3bit synchronous up/down counter

STATE DIAGRAM



K MAP

CHARACTERISTICS TABLE:

Q Qt+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0



LOGIC DIAGRAM:


Q1: What is difference between synchronous& asynchronous counters?

Q2: What is the significance of state assignments?

Q:3 What is meant by Mod counter.

Q:4 Which flip flop’s are used for designing & implementing synchronous counter.

Procedure:



Result & Conclusion: All counters have been implemented & verified through truth table.


Q1: What are races & cycles?

Q2: What are the steps for the design of synchronous & asynchronous counters?

Q3: Which counter is used for removal of internal propagation delay?

Q4: How many different states does a 3-bit synchronous counter have?



Experiment 11

DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS COUNTER

Aim: Design and implementation of Asynchronous Counters

Equipment Required & Components Required:





1

Digital ICs

7400, 7402, 7404,

7408, 7432, 7486.

1 each

2 Patch cords - 6

Theory: A counter is a register capable of counting number of clock pulse arriving at its clock

input. Counter represents the number of clock pulses arrived. A specified sequence of states

appears as counter output. This is the main difference between a register and a counter. There are

two types of counter, synchronous and asynchronous. In synchronous common clock is given to

all flip flop and in asynchronous first flip flop is clocked by external pulse and then each

successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second

stage is triggered by output of first stage. Because of inherent propagation delay time all flip

flops are not activated at same time which results in asynchronous operation.

a) 4 BIT RIPPLE COUNTER



TRUTH TABLE:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:



b) MOD - 10 RIPPLE COUNTER

TRUTH TABLE:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1



LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:


Q1: What is difference between synchronous& asynchronous counters?

Q2: What is the significance of state assignments?

Q:3 What is meant by Ripple counter.

Q:4 Which flip flop’s are used for designing & implementing asynchronous counter.

Procedure:



Result & Conclusion: All counters have been implemented & verified through truth table.


Q1: What are races & cycles?

Q2: What are the steps for the design of synchronous & asynchronous counters?

Q3: Which counter is used for removal of internal propagation delay?

References



1. Digital Electronics circuit Book by R.P.Jain.

2. Digital Design: Principle & Practice Fourth Edition by John.F.Wakerly.

3. Foundation of Digital electronics and Logic Design Book by Asish Kumar De,Souvik

Sarkar, and Subir Kumar Sarkar.

DLD LAB MANUAL · 2019-08-17 · A breadboard is a prototyping board made of insulated material...

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