The values of the outputs depend on the input and the previous states.

SEQUENTIAL SYSTEM

The values of the outputs depend only on inputs

COMBINATIONAL SYSTEM

The FF is in the lower section, so that the clock and reset connects to it.

As the lower section is sequential, process is required.

SEQUENTIAL DESIGN SYSTEM

PROCESS (reset, clock) BEGIN IF (reset= '1' ) THEN pr_state <= state0; ELSIF (clock ‘EVENT AND clock= '1')THEN pr_state <= nx_state; END IF; END PROCESS;

SEQUENTIAL DESIGN SYSTEM

The code has two things: assignment output and set the next state.

Don‘t assignment to signal made in the transition of another signal,so that doesn‘t infer.

COMBINATIONAL DESIGN SYSTEM

PROCESS (input, pr_state) BEGIN CASE pr_state IS when state0 => IF (input=…) THEN output <= <value>; nx_state <= state1; ELSE … END IF END CASE; END PROCESS;

COMBINATIONAL DESIGN SYSTEM

TEMPLATE

In this case, it use‘s a Mealy machine. The signals are synchronous, so that the

output has that bring up to date only when exist a clock pulse.

For to do a synchronous Mealy machine, the output are storage also.

STYLE OF DESIGN 2

PROCESS (reset, clock) BEGIN IF (reset= '1' ) THEN pr_state <= state0; ELSIF (clock ‘EVENT AND clock= '1')THEN output <= temp; pr_state <= nx_state; END IF; END PROCESS;

SEQUENTIAL DESIGN SYSTEM

PROCESS (pr_state) BEGIN CASE pr_state IS when state0 => temp <= <value>; IF (condition) THEN nx_state <= state1; END IF; when state1 => temp <= <value>; IF (condition) THEN nx_state <= state2; END IF; END CASE; END PROCESS; END <arch name>;

COMBINATIONAL DESIGN SYSTEM

TEMPLATE

SISTEMAS DIGITALES I

Carlos Yamid Paiba DíazAnderson Julián Barrera Moreno