Digital Product Testing

8/6/2019 Digital Product Testing

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ALL

ABOUT

DIGITAL


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PRODUCTS.

BY

Ramki

.

INTRODUCTION:

Two popular technologies are widely used to produce

Ics namely TTL (Transistor-Transistor Logic) & CMOS( Complementary Metal Oxide Semiconductor).Cmos has


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now became the most opted for new circuits as it can pack more circuitry into a given chip area.

The majority of the computers circuitry is

comprised of the digital logic. This circuitry makes thelogical decisions which results in YES / NO or True/False. Simple digital circuits or the logic blocks can

be combined together to form a very complex logicfunctions. Examples of the basic logic circuits areInverters (Not), AND, OR, NAND, NOR GATES &FLIP FLOPS.

Digital products have only 3 states namely logic 0,logic 1 & z-state. In this book let us concentrate more onhow do we test & characterize these digital products.

VARIOUS TESTS PERFORMED :

The various tested that are performed in the digitallogic products are as follows:


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1. Continuity tests.2. Functional tests3. Vil tests

4. Vih tests5. Iccqc tests6. Iccqt test7. Vol Tests/Ronl tests8. Voh tests /Ronh tests9. Iil tests10. Iih tests11. Iozl tests12. Iozh tests13.Tplh tests14.Tphl tests15.Tpzl test16.Tpzh tests17.Setup & Hold tests.

In case of the Lcxh products we will have some tests like:18. Bus hold leakage tests.19. Bus hold sustaining current test.20. Power off leakage tests.

OPEN SHORT TEST:

The open/short test verifies that the contact is being made to all the signal pins & that no signal pin isshorted to another signal or power/ground pins.


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Test Methodology:(DC method)

Ground all the device pins including the power & ground pins.Connect the PMU to a single device pin.Force the current which will forward bias

one of the protection diodes.Force the current in the range of -100 to

-200UA.

Measure the drop .Typical value measures0.65V.If the value measures less than 0.2V the

device is failed in short test.If the device measures greater than 1.5v the

device is failed in open test.If it measures between 0.2 1.5 V the

device passes the open/short test.Both Power pin & the ground pin can also be subjected tothis test, but as their structure is entirely different from thatof the signal pin, test the power pin for the good devices &accordingly set their limits.

Although the above DC static method in performing this test is quite convincing test methodology, but still as the cost of every device depends on test time. Inorder to reduce the test time this test is performed based onthe Functional vectors.Test Methodology:(Functional method)


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Define all the signal pins as inputs and forceVil (zero volts).The 0 in the vector file instructs

the tester to perform this function on each pin.Define the first signal pin as an output to betested, turn off the tester drive on that pin, andcompare the output for pass/fail. The Z character instructs the tester to perform this function on thefirst pin to be tested.

Turn the driver back on for the pin tested inthe last cycle & repeat the step 2 for the next pintested.

Continue until all the signal pins are tested.

Sample vector Pattern for open/short test:

00000 -> Ground all the pinsz0000 -> Tested for the pin 10z000 -> Tested for the pin 200z00 -> Tested for the pin 3

000z0 -> Tested for the pin 40000z -> Tested for the pin 5


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FAIL-OPEN (>1.5V)

PASS REGION(0.2-1.5V )

FAIL-SHORT (


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The functional test verifies whether the devicecorrectly performs the intended logical functions. To

accomplish this test vectors or truth tables are created. Theability of the truth table to detect the faults is called the fault coverage . The heart of the functional test comprises of the Test vectors combined with the test timings. Themajority of the test resources are utilized while performingthis test.

Before performing this test the exact values for the following items must be carefully examined:

1. DUT power levels.2. Input levels.3. Output levels.4. Output current loading.5. Cycle time used for test.6. Clocks/setups/holds/controls.

7. Wave shapes of the input signals.8. When outputs will be sampled within cycle?9. Start/Stop points within a vector file.

The test vector file represents input & output logic statesneeded to test the DUT. The test program contains theinformation needed to control the test hardware in a manner

that will create all the necessary voltages, waveforms &timings. As the functional test executes, the test systemsupplies the input data to the DUT & monitors the DUToutputs on a cycle by cycle, pin by pin basis. If any output

pin fails to meet the expected logic state, voltage or timing,the result of the functional test is a failure.


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Refer to the Appendix (1) for the various levels used both by the sending & the receiving drivers.

Test Methodology:

Define the required parameters mentionedalready.

Note all the input, output & timing parametersare set to their worse case conditions & thefunctional sequence is executed.

Apply Vcc Max (Maximum tolerance of supplyvoltage).

Perform Vil test keeping the parameter Vil asstringent & Vih as relaxed.

Perform Vih test keeping the parameter Vih asstringent & vil as relaxed.

Monitor the output signals during test.Fails test if any output level is different from

expected.Repeat the above sequences by applying Vcc

Min.

COMPARATOR LOGIC FOR THE NORMAL OUTPUT LEVELS

PASS REGION (VOH > 1.6V) - LOGIC 1

FAIL REGION (1.4V < VOL/VOH< 1.6V)


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PASS REGION (VOL


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DPS1 5.25V/10V 8.7MA/50MA -1MA +45MA PASS

Test Methodology:

Use DPS OR PMU to apply Vcc (max).

Set Pass/fail limits.Set all inputs low/high or execute reset sequence.Stop Pattern.Wait 1 to 5 ms (Set Pmu delay).Measure current flowing into the supply pins.Fails ICC if measured current is outside of the

limits.


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ICC STATIC CURRENT TEST:

Static indicates that the DUT is not active duringthe test. The static ICC test insures that the DUT will notconsume more current than the value stated in the devicespecification, when the DUT is preconditioned to its lowestcurrent consumption logic state. This measurement isextremely important for the battery operated devices. It isalso a very good way to identify the processing problemswith CMOS devices.

The ICC static test measures the total current flowinto the Vcc pin. It is performed by executing the testvector pattern that preconditions the device to a knownstate, typically the state that draws the least amount of Vcccurrent. The device is then held in a static condition & theamount of current flowing into the Vcc pins is measured.

The measured current is then compared to the ICC statictest specification. The following parameters influence thetest results & therefore must be specified in the devicespecification: VIL, VIH, VCC, and Vector Sequence &Output loading.

Note if the expected ICC current is very small,additional delay time (settling time) may be required beforemaking the current measurement. External by-passcapacitors on the test hardware can affect the measuredresults. In some cases it may even becomes to use a relay todisconnect the by-pass capacitor to make an accuratemeasurement.


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SAMPLE DATALOG OF STATIC IDD/ICC CURRENT USING PMU

PIN FORCE/RNG MEAS/RNG MIN MAX RESULTVCC1 5.25V/10V 19.20NA/25UA +1UA PASS

Test Methodology:

Use DPS or PMU to apply Vcc (max).Execute the preconditioning patternStop pattern.Wait 1 to 5 ms (Set Pmu delay).Measure the current flowing into the VCC Pins.Fails this test if measured current is greater than

ICC spec.

The various factors that affect the CMOS IDD currents are:input levels, input pull up & pull down resistors, Vcclevels, Vector sequences, Output current loading & Outputcapacitor loading.

PMU TEST LIMITS:

FAIL (MEASURES > ICCSPEC)


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PASS (MEASURES < ICCSPEC)

When a failure occurs remove the device from the testsocket & return the test. The static IDD test should passwith an open socket. If it fails, the current is beingconsumed by something other than the DUT. So eliminatethe sections of the test hardware until the source of the

problem is found.


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ICC DYNAMIC CURRENT TEST:

Dynamic indicates that the DUT is active (beingclocked or with its internal devices changing logic states)during the test. The dynamic ICC test insures that the DUTwill not consume more current than the value stated in thedevice specification while the Dut is actively performing its

functions. Dynamic ICC is the operating ICC of the device.The dynamic ICC test measures the total current

flow into the VCC pins, normally at the maximumoperating frequency of the DUT. The resultant currentmeasured is then compared to the ICC dynamic testspecification. The following parameters influence the testresults & therefore must be specified in the devicespecification: VIL, VIH, VCC, Vector Sequence, testfrequency & Output loading.

When measuring the dynamic ICC currents the delaytime of the PMU may need to be adjusted someexperimenting may be required. The dynamic ICC Testshould produce consistent results when the test is repeated.

SAMPLE DATALOG OF DYNAMIC IDD/ICC CURRENT USING DPS

PIN FORCE/RNG MEAS/RNG MIN MAX RESULTVCC1 5.25V/10V 12.20MA/25MA 18UA PASS


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Test Methodology:

Use DPS or PMU to apply Vcc (max).Execute the preconditioning patternWait 1 to 5 ms (Set Pmu delay).Measure the current flowing into the VCC Pins.Fails this tests if measured current is greater than

Icc spec.Stop Pattern.


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VOL /IOL TEST:

VOL represents the maximum voltage produced byan output, when the output is in the low (L) state. IOL testrepresents the current sinking capabilities of an outputwhen the output is in low state.

The VOL / IOL test measures the resistance of an

output pin when the output is in logic 0 state. This testinsures that the resistance of the output meets the design

parameters & guarantees that the output will provide thespecified IOL current without exceeding the Vol voltage. Inother words, the device output pins must sink at least aspecified minimum amount of current & stay in the correctlogic state.

These VOL/IOL parameters may be verified either statically or dynamically. To perform a static test, thedevice is preconditioned to set the outputs to logic 0 states.The DC measurement system (PMU) is then connected tothe pin under test, the IOL current is forced & the resultantvoltage is measured & compared to the VOL specification.If the voltage measured is greater than the VOL limit thetest fails. This process is repeated for each pin until all the

pins have been verified in the low state.

SAMPLE DATALOG OF DYNAMIC VOL/IOL TEST USING PMU

PIN FORCE/RNG MEAS/RNG MIN MAX RESULTPIN1 64.0mA/20mA 130MV/RNG2 400mV PASS


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PIN2 64.0mA/20mA 430MV/RNG2 400mV FAILPIN2 64.0mA/20mA 130MV/RNG2 400mV PASSPIN2 64.0mA/20mA 120MV/RNG2 400mV PASSPIN2 64.0mA/20mA 530MV/RNG2 400mV FAIL

Test Methodology:

Apply the voltage Vcc (min).Precondition the output to logic 0.Using PMU, force the IOL current per

specification.Wait 1 to 5 ms.Measure the resultant voltage.Fails the VOL test if the measured voltage is

greater than the spec limit.

PMU TEST LIMITS:

FAILS(VOLTAGEMEASURED > SPEC LIMIT)PASS(VOLTAGEMEASURED < SPEC LIMIT)

Note: 1.Applying the voltage of Vcc (min) is the worst case condition.2. IOL is the positive current.

In case some of the pins might get failed marginally, insuch instances try to insert a device in a DUT and check for


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SAMPLE DATALOG OF DYNAMIC VOH/IOH TEST USING PMU

PIN FORCE/RNG MEAS/RNG MIN MAX RESULT

PIN1 -15.0mA/20mA 3.250V/RNG2 2.400V PASSPIN2 -15.0mA/20mA 2.200V/RNG2 2.400V FAILPIN3 -15.0mA/20mA 3.300V/RNG2 2.400V PASSPIN4 -15.0mA/20mA 3.250V/RNG2 2.400V PASSPIN5 -15.0mA/20mA 2.100V/RNG2 2.400V FAIL

Test Methodology:

Apply the voltage Vcc (min).Precondition the output to logic 1.Using PMU, force the IOH current per

specification.Wait 1 to 5 ms.Measure the resultant voltage.Fails the VOH test if the measured voltage is

less than the spec limit.

PMU TEST LIMITS:

PASS(VOLTAGEMEASURED > SPEC LIMIT)FAILS(VOLTAGEMEASURED < SPEC LIMIT)

Note: 1.Applying the voltage of Vcc (min) is the worst case condition.2. IOH is the negative current.


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3. A voltage clamp must be set.

INPUT CURRENT TESTS (IIL/IIH TEST): IIL is the current in an input when it is forcedlow. IIH is the current in an input when it is forced high.The IIL test measures the resistance from an input pin toVCC.The IIH test measures the resistance from an input

pins to ground.This test insures that the resistance of the input

meets the design parameter that the input will not drawmore than the specified IIL/IIH current. It is also the bestway to identify the processing problems in CMOS devices.There are several methods to perform the IIL/IIH inputcurrent test as follows:

1. Serial/Static Test Method2. Parallel Test Method

3. Ganged Test Method

1.Serial /Static Test Method:


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To perform the IIL test, VCC (max) isapplied and all the input pins are preconditioned to logic 1using the functional pin drivers (VIH). The DC

measurement system (PMU) then forces each input low &the resulting current is measured & compared to the IILcurrent limit as per the test spec. This process is repeatedon each pin until all the inputs have been tested. Similarlyfor the IIH test VCC (max) is applied and all the input pinsare preconditioned to logic 0 using the functional pindrivers (VIL).Then the resulting current is measured oneach individual pins.

Test Methodology(IIL TEST):

Apply the voltage Vcc (max).Precondition all the inputs to logic 1 with

the pin drivers.Using PMU, force the individual pins to

OV.Wait 1 to 5 mSec.Measure the resultant current.Fails IIL if measured current is less than the

spec limit (+/- 700NA).

Test Methodology(IIH TEST):


the pin drivers.


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Using PMU, force the individual pins toVCC (max).

Wait 1 to 5 mSec.

Measure the resultant current.Fails IIH if measured current is less than the


ADVANTAGE:This serial test has the ability to measure the

individual current flow of each pin, and also to test for pinto pin leakage. Since the pin under test receives a differentvoltage from all other pins ,any leakage path between theinputs will be found.

DISADVANTAGE:

The disadvantage of this test is the test time requiredto measure each pin individually.

1.Parallel Test Method:

Some test systems have the capability to performthe parallel leakage measurements. It means that all themeasurements are made simultaneously, but on anindividual basis. This is performed by using the PMU per

pin circuitry located on the pin electronics card. All inputsare forced to the logic 1 & the current flow of each pin ismeasured in parallel (Simultaneously).All inputs are thenforced to a logic 0 & the current flow of each pin is againmeasured in parallel.


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Test Methodology(IIL TEST):

Apply the voltage Vcc (max).

Precondition all the inputs to logic 1 withthe pin drivers.Using PMU per pin, force each pin to OV.Wait 1 to 5 mSec.Measure the resultant current.Fails IIL if measured current is less than the




the pin drivers.Using PMU per pin, force each pin to VCC

(max).Wait 1 to 5 mSec.Measure the resultant current.Fails IIH if measured current is less than the


ADVANTAGE:


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This Parallel method has the ability to performthese tests quickly & yet the individual current flow of each

pin is measured.

DISADVANTAGE:Pin to Pin leakage between the inputs is more

difficult to detect because all inputs are held at the samevoltage level when the current measurements are made.This Method requires the test system to have per pin PMUarchitecture.

Note: In Sentry, STS - This test cannot be performed asthey dont have the per pin architecture. But in Mct,Andowe can perform this test.

3.Ganged Test Method:Some test systems have the ability to

perform the leakage measurements. Ganged measurementmeans the measurements is made by connecting a singlePMU to all the inputs at one time & measuring the totalcurrent flow. All the inputs are forced to logic 1 & the totalcurrent flow is measured. All the inputs are then forced tologic 0 & the total current flow is measured. The results of the current measurements are compared to the limits set inthe test program & a pass/fail decision is made.

The current limit of this test is fixed the sameas that of the individual pin as per the design eachindividual pin measures zero current & hence the sum of


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the current flow is also zero. If in case, this test fails the program should be written in such a way that it performsthe serial test. This Ganged test must not be performed for

The resistive inputs because the sum of the leakage currentfor all the pins will be greater than the spec limit for anindividual pin.

Test Methodology (IIL TEST):Apply the voltage Vcc (max).Precondition all the inputs to logic 1 with

the pin drivers.Using PMU, force all the pins to 0V.Wait 1 to 5 mSec.Measure the resultant current.Fails IIL if measured current is less than the

spec limit (+/- 700NA).If fails retest using serial method.



the pin drivers.

Using PMU, force all inputs to VCC (max).Wait 1 to 5 mSec.Measure the resultant current.Fails IIH if measured current is less than the



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SAMPLE DATALOG OF SERIAL IIH TEST USING PMU @ VCC(MAX) [SAY 5.5V]:

PIN FORCE/RNG MEAS/RNG MIN MAX RESULT

PIN1 0V/RNG2 0A /1UA -700.0NA 700NA PASSPIN2 0V/RNG2 4UA /1UA -700.0NA 700NA FAILPIN3 0V/RNG2 0A /1UA -700.0NA 700NA PASSPIN4 0V/RNG2 0A /1UA -700.0NA 700NA PASSPIN5 0V/RNG2 2UA /1UA -700.0NA 700NA FAIL

PMU TEST LIMITS:

FAILS(IIL/IIH> 700NA)

PASS(-700NA


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IOZL test measures the resistance from the output pin toVDD when the output is in the high impedance state. Thistest insures that the resistance of the output, when it is

turned off, meets the design parameters & guarantees thatthe output will not draw more than the specifiedIOZL/IOZH current.

To perform the IOZ test, Vcc is applied & a pattern isexecuted which preconditions the device pins to their highimpedance state. The DC measurement system (PMU)forces both high & low voltage onto each pin (one at atime) & the resulting current is measured. The measuredcurrent is then compared to the IOZ spec limit in the testspecification. This process is repeated on each pinindividually until all the high Z-pins have been tested.

This test can also be performed by the previouslyexplained 3 methods:1. Serial/static method2. Parallel method

3. Ganged methodTest Methodology:

Apply the voltage Vcc (max).Precondition all the outputs to tri state.Using PMU, force 0V.Wait 1 to 5 mSec.

Measure the resultant current.Fails IOZ if it measures above the spec

limit.Repeat with PMU forcing VDD (max).


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Fails IOZ if it measures above the speclimit.

SAMPLE DATALOG OF SERIAL IOZ TEST USING PMU @ VCC(MAX) [SAY 5.5V]:

PIN FORCE/RNG MEAS/RNG MIN MAX RESULTPIN1 5.50V/RNG2 0A /1UA -700.0NA 700NA PASSPIN1 0.00V/RNG2 4UA /1UA -700.0NA 700NA FAILPIN2 5.50V/RNG2 0A /1UA -700.0NA 700NA PASSPIN2 0.00V/RNG2 0A /1UA -700.0NA 700NA PASSPIN3 5.50V/RNG2 2UA /1UA -700.0NA 700NA FAILPIN3 0.00V/RNG2 2UA /1UA -700.0NA 700NA FAIL

PMU TEST LIMITS:

FAILS(IOZ> 700NA)

PASS(-700NA


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parameters when subjected to the worse case loadingconditions & guarantees that an output when shorted iscapable of sourcing a predefined amount of current.

The general rule to avoid hot switching is to have both sides of the relay at the same voltage before openingor closing of the relays.

Test Methodology:

Apply Vcc (max).Precondition output to logic 1.Using PMU, force 0V.Wait 1 to 5 mSec.Measure the resultant current.Fails if it measures outside the spec limit.

SAMPLE DATALOG OF SERIAL IOS TEST USING PMU:

PIN FORCE/RNG MEAS/RNG MIN MAX RESULTPIN1 0.00V/RNG2 -53.2MA /100MA -85.0MA -35.0MA PASSPIN2 0.00V/RNG2 -23.2MA /100MA -85.0MA -35.0MA FAILPIN3 0.00V/RNG2 -43.2MA /100MA -85.0MA -35.0MA PASSPIN4 0.00V/RNG2 -63.2MA /100MA -85.0MA -35.0MA PASS

BUS HOLD LEAKAGE TEST:

This test is the same input leakage test for the bus holdinputs in which as there is input resistor (Terminator) thiswill draw more current hence only Serial method of testingis used with the limits +/- 8ua .


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POWER OFF LEAKAGE TEST:

This is the test that is performed in ideal condition. Inthis test we force the voltage at VCC as 0V which means

both the Vcc & Vee are at 0V, the current flowing atthis condition with the input voltage of 4.5-5.5 V ismeasured.This test is performed mostly in Lvc, Alvc, Vcx devices.

Test Methodology:

Apply the voltage 0v.Using PMU, force the individual pins to 4.5-

5v.Wait 1 to 5 mSec.

Measure the resultant current.Fails Ioff if measured current is less than the


AC TESTS:


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The purpose of the AC testing is to guarantee that thedevice meets all of its timing specifications. Ac testing is

performed by setting up the appropriate timing values &

signal formats as defined in the Ac specification. Before we proceed to the test methodology to conductAc tests in the digital devices, the terminology of theFollowing tests should be understood:

1. Setup time test.2. Hold time test.3. Propagation delay test.4. Clock width test.5. Maximum frequency test.6. Output enable test.7. Output disable test.

1.SETUP TIME :


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Setup time is the minimum amount of time thatthe data must be present before a reference signalreaches a certain voltage point.

Features:The purpose of this parameter is to

guarantee that the input can be read (or latched )within a minimum amount of time before areference signal occurs.

Performed only for the input pins.Setup time can be a negative number Setup time = (reference signal result of the

binary search).

2.HOLD TIME :

Hold time is the minimum amount of time thatthe data must be present after a reference signalreaches a certain voltage point.


guarantee that the input can be read (or latched)within a minimum amount of time after a referencesignal occurs.

Performed only for the input pins.Hold time can be a negative number Hold time = (result of the binary search -

reference signal).4. PROPAGATION DELAY :


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It is the amount of time between

the transition of one signal & the resulting transition of

another signal, measured at a specific voltage (Usually at1.5v). Most of these measurements are made from an inputsignal to the output signal.


guarantee that the output signal can occur within aspecified time after the occurrence of a referencesignal.

Performed only on the output pins.Can only be a positive number.

5. MINIMUM CLOCK WIDTHS :

The minimum amount of time which theclock can remain in the logic 0 state is Minimum clock lowtime. The minimum amount of time which the clock canremain in the logic 1 is Minimum clock high time.


guarantee that the minimum operational values for clock low & clock high timings.


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The test results can only be a positivenumber.

6. MAXIMUM FREQUENCY :The maximum operating frequency is usually

the inverse of the sum of the minimum clock low & clock high times. When performing any test that requires themovement or the adjustments of a clock edge make certainthat all timing relationships to the clock edges are properlymaintained.


guarantee that the maximum device operating

frequency.The test results can only be a positive

number.

7. OUTPUT ENABLE TIME :Output enable time is the time it takes an output

to switch from a high impedance state to driving validlogic levels. The time is measured from a control signal toa switching output. This test requires that the outputs beconnected to a load with a reference voltage set at anintermediate level.


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Features:The purpose of this parameter is to gurantee

that the high impedance output can drive valid

output levels within a specified amount of timefrom occurrence of a reference signal.The test results can only be a positive

number.

8. OUTPUT DISABLE TIME :Output disable time is the time it takes an output

to switch from driving valid logic levels to a highimpedance state, as measured from a control signal. Thetime is measured from a control signal to a switchingoutput. This test requires that the outputs be connected to aload with a reference voltage set at an intermediate levels.

The output causes the bus to be pulled to the intermediatelevel once the output drivers turn off.

Features:The purpose of this parameter is to gurantee

that the high impedance output can drive validoutput levels within a specified amount of time

from occurrence of a reference signal.The test results can only be a positivenumber.


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P.S: High impedance state means a state which has thevoltage greater than vol & less than voh .

9. SIGNAL FORMAT :

The signal formatting allows us to guarantee thatall the AC parameters are tested to the specification.Signalformats when combined with the vector data,edge

placements & input levels, define the wave shape of theinput signals to the DUT.Various Signal Formats Used:

NRZ : Non return to zero represents the actual data storedin the vector memory & contains no edge timing. NRZdata changes only at the beginning of each cycle.

DNRZ : Delayed Non return to zero represents the data

stored in the vector memory, but the point within the cyclewhere the data makes a transition is defined to be a valueother than the start of the cycle. DNRZ will change after a

predefined delay period only if the vector data has changed between the current cycle & the previous cycle.

RZ : Return to zero provides a positive pulse when vector data is logic 1 & no pulse when the vector data is logic 0.This format can provide a positive clock when all thevector data for the pin is logic 1.

RO : Return to one provides a negative pulse when thevector data is logic 0 & no pulse when the vector data is


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logic 1. This format can provide a negative clock when allthe vector data for the pin is logic 0.

SBC : Surround by compliment can provide 3 edgetransitions per cycle. This signal format creates a complexsignal based on the vector data. This format is the onlyformat that will guarantee both setup & hold time in asingle execution of test vectors. This is also called as XOR.

Refer to the timing diagram for various formats in the fig.

10. DEVELOPING THE INPUT SIGNAL TIMINGS :

Once the cycle time has been determined,the placement of the clock & the control signals within thecycle can be defined. There are generally 2 types of inputsignals control signals & data signals . Control signalsdetermine the point in time when data signals will be read

into the internal logic of the device. Data signals providedata or instructions to the device.

Determine the active edges of the clock or thecontrol signals and the amount of setup & hold timerequired on the data signals.This information will helpdefine the edge placement(timing) of each input signalwithin the test cycle.

Next determine the signal format required for eachinput signal. Clock signals are usually RZ(positive pulse)or RO(negative pulse) formats. Data signals & /OE areusually in NRZ format. Data signals that have the setup 7hold time parameters requires SBC format.


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Input signals are created by combining datafrom several areas within the test system. The waveform atthe test head is the result of the test vector,edge placement

timing,format definition & VIL/H values as shown in thefigure.

11. DEVELOPING THE OUPUT SIGNAL TIMINGS

Output signal transitions are often controlled by a clock or control signal edge. Review the devicetiming diagram & determines the active edge of the clock or control signals which cause the output signals to

change. Determine the amount of the propagation delaytime needed before the output reaches a valid logic level.This point within the cycle is where the output strobeshould be placed for the particular signal.

The output strobe can be a point in time or a window intime depending on the test system hardware capabilities.When the output strobe occurs the output signal for theDUT is sampled. The signal must be equal to or greater than the VOH voltage if the test vector defines theexpected output as logic 1. The signal must be equal to or less than the VOL if the test vector defines the expectedoutput as logic 0.


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across RL & the current flow thro RL into the deviceoutput is 1.95mA loading the device output when driving alogic 0.

When the device output drives a logic 1(2.4v) D4 becomes reverse biased & eliminates the current loadingeffect. For this eg. The AC load provides a current loadonly for a logic 0; when the device drives a logic 1 the loadis essentially removed.

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