Digital Logic Review

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Version 6.3/26/11 For Academic Use Only in Accordance with Licence-to-Use, seereadme.pdf

Digital Logic Review

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Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Digital Logic - the bottom line 2.1

Digital Signal Processing (DSP) with FPGAs has the usual digital logic

bottom line - logic gates!

In this session we revisita few fundamentals:

Number Systems;

Boolean algebra;

Combinational Systems;

Sequential Systems;

Synchronous/Asynchronous Systems;

Counters review;

Synchronous Sequential Systems Design techniques.
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Logic Levels and Number Systems 2.2

Decimal Numbers - Base 10, based, or course on our ten fingers!Using two logic levels gives two distinct states

HI and LO

or 1 and 0or True and False

and hence can be used to represent binary numbers (base 2). For

electronic systems typically TTL voltage levels assigned

Logic (or digit) 0 = 0 voltsLogic (or digit) 1 = 5 volts
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Noise Margin 2.3

In modern logic the logic 1 is likely to 3.3 volts.

Recalling that , then going from 5 volts to 3.3 volts represents apower drop from 5 x 5 = 25 to , or a reducing powerrequirements by more than 50%.

Although lower voltage is lower power consumption the potential noisemargin is higher:

P V2

3.3 3.3 10.89=

VIH (min)

VIL (max)

Logic 1(HI)

Logic 0(LO)

Not

allowed

Input5v

3v

2v

0v

VOH (min)

VOL (max)

Logic 1 (HI)

Logic 0 (LO)

Not

allowed

Output5v

4.4v

0.33v0v

VNL VIL(max) VOL(max)=

VNH VOH(min) VIH(min)=


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Decimal to Binary 2.4

To convert from binary to decimal we can set up a table of powers of two:Convert 10101102to decimal

= 64 +16 + 4 + 2 = 8610

The binary point can also be represented:

Convert 11.1011 to decimal

= 2 + 1 + 0.5 + 0.125 + 0.0625 = 3.687510

27 26 25 24 23 22 21 20

128 64 32 16 8 4 2 1

0 1 0 1 0 1 1 0

21 20 2-1 2-2 2-3 2-4

2 1 0.5 0.25 0.125 0.0625

1 1 1 0 1 1

T


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Decimal to Binary Conversion 2.5

Inverse of Binary to Decimal is easiest to accomplish via successive

subtraction method.

For example, convert 27910 to binary (base 2).Recall powers of two are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512....

279 - 512 = -ve 0

279 - 256 = +23 1

23 - 128 = -ve 0

23 - 64 = -ve 023 - 32 = -ve 0

23 - 16 = +7 1

7 - 8 = -ve 0

7 - 4 = +3 13 - 2 = +1 1

1 - 1 = 0 1

i.e. 27910 = 1000101112

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Binary Arithmetic 1 2.6

From our decimal point of view, easy to show that for binary:

0 + 0 = 0 (zero)0 + 1 = 1 (one)

1 + 0 = 1 (one)1 + 1 = 10 (two) i.e. zero carry one)1+1+1 = 11 (three) i.e. one carry one)

Hence forAddition:

1011 +11+ 1101 +1311000 +24

....and forSubtraction:

11101 +29-01011 -1110010 +18

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Binary Arithmetic 2 2.7

Multiply 1011 by 1001 (11 x 9 = 99)

Divide 11001 by 101 (25/5 = 5)

10111001

1011

000000001011+

1100011

101 11001

101

101

101

101

N t Top


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Binary Numbers Range 2.8

In many applications wordlengths of a power of 2 are used

e.g., 4(a nibble), 8(a byte), 16(a word), 32,.....

The numerical range of an N bit number is:

0 2N- 1

For 8 bit numbers range is 0 28- 1 = 255

For 16 bit numbers range is 0 216- 1 = 65536

The range of binary numbers chosen for a specific application must be

sufficient to represent all numerical values likely to be encountered.

If a calculation in a binary system has a result outwith the permissiblerange, then this is overflow.

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Signed Binary Numbers 2.9

2s complement notation is the most common means of representing

signed (+ve or -ve) number.

In 2s comp. the MSB (most significant bit) has a -ve weighting.

Consider 8 bit 2s complement number representation:

101011012 = -128 + 32 + 8 +4 +1 = -8310

For an Nbit 2s complement representation numerical range is:

-2N-1 2N-1 - 1

e.g. for 8 bit 2s complement, range is -128 to +127.

-27 26 25 24 23 22 21 20

-128 64 32 16 8 4 2 1

1 0 1 0 1 1 0 1

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Arithmetic with 2s Complement 2.10

When using 2s complement, we just add as normal. However for fixed wordlength problems, we detect overflow if a result is

outside of the fixed wordlength.

For example if 8 bit numbers are used, then the operands and resultmust lie in the range -128 to +127.

For example

Adding +ve and -ve will never overflow!

Adding +ve and +ve if a -ve result then overflowAdding -ve and -ve if a +ve result then overflow

1011011101111111

1 00110110+

Discard final 9th bit carry

(-73) + 127 = 54011001000100000010100100

+

MSB bit indicate -ve result!

100 + 64 = 164

OverflowNo overflow

Top

H d i l
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Hexadecimal 2.11

Hexadecimal or Hex is Base 16.

Simply used because binary notation is prone to written error byhumans, converting to decimal is inconvenient.

Hex provides an easy-to-calculate-from-binarycompact representationof binary values.

The (sixteen) Hex digits are:

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

Binary equivalents are all 4 bits, i.e. 0000 (0) to 1111 (F).

Notes: Top


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Hexadecimal Example 2.12

Hex to decimal can be accomplished via a tabular technique:

A10416 = (A x 4096) + (1 x 256) + 4 = 4122010

Easy to convert to binary: A10416 = 1010 0001 0000 01002A 1 0 4

Simply replace Hex digits with 4 bit binary equivalents.

Checking.....

1010 0001 0000 0100 = 32768 + 8192 + 256 + 4 = 4122010

163 162 161 160

4096 256 16 1

A 1 0 4

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Q ti 1


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Questions 1 2.13

Convert 10510 to binary.

Convert the binary number 100111101 to decimal.

What is range of 10 bit 2s complement numbers?

Convert the 8 bit 2s complement value 10010001 to decimal.

Convert the 8 bit 2s complement value 01110001 to decimal.

Add the 8 bit 2s complement values 11111111 + 11111110 together.Does this result overflow?

If 16 bit binary 2s complement numbers are used, what is the decimal

and binary equivalent of FFFF16?

Octal is base 8. Why might octal be of use for digital systems?

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Logic Elements 2.14

NOT

AND

OR

EOR

0 11 0

A

B

B

A

0 0 0

0 1 11 0 11 1 1

X Y ZX

Y Z

0 0 00 1 01 0 01 1 1

E F GGE

F0 0 00 1 11 0 11 1 0

P Q RP

Q R

B A= Z A B+=

G EF= R P Q+=

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The Universal Gate


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The Universal Gate 2.15

The Not-AND (NAND) gate can be used to create all other gates:

The OR gate is produced as:

Algebraically:

Question: Is a NOR (NOT-OR) a universalgate?

X

YZ X

YZ

Z AB A B+= =

Notes: Top


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Boolean Algebra 2.16

The representation of logical circuits can be done with Booleanexpressions as above, and the manipulation of Boolean expressionsperformed using the laws of Boolean algebra.

Boolean variables can have one of two values: 0 or 1.

Laws: Complementation:

Involution:

Union/Intersection

Indempotency

Absorption

Association

Distribution

De-Morgans

A A+ 1= AA 0=

A A=

A 0+ A= 1+ 1=

A A+ A= AA A=

A A B+( ) A= A AB+ A=

A B C+( )+ A B+( ) C+=

A BC+ A B+( ) A C+( )=

A B+( ) AB= AB( ) A B+=

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Boolean Circuit Representation


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Boolean Circuit Representation 2.17

Any combinational circuitusing digital logic components can be written

in Boolean algebra.

A combinational circuitdoes not include feedback or memory.

A

B

CD

Y

X

X AB=

Y AB C +( )D ABCD A B+( )CD ACD BCD+= = = =

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Standard Boolean Forms 2.18

Sum of Products (SOP) or an OR of ANDs

e.g.

Product of Sums (POS) or an AND of ORs

e.g.

Y A B C , ,( ) ABC ABC AB+ +=

AND

OR

AND AND

P X Y Z , ,( ) X Y Z+ +( ) X Y+( )=OR

AND

OR

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Two Level Gate Implementations 2 19


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Two Level Gate Implementations 2.19

Standard form SOP can be implemented in a two level AND/OR

configuration (POS can be implemented in two level OR/AND):

If all product terms contain all variables then this is often referred toas sum of minterms orcanonical sum of products.

Y A B C , ,( ) ABC ABC AB+ +=

A

C

B

A

CB

A

B

Y

Y A B C , ,( ) ABC ABC AB C C+( )+ +=

ABC ABC ABC ABC+ + +=

Notes: Top


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Boolean Expressions and Truth Tables 2.20

Boolean expressions can be easily converted into truth tables usingbinary values for each term in the expression when written in thestandard form.

For example

F A B C , ,( ) ABC ABC ABC ABC+ + +=

minterm

0 0 0 1 0 1 1 1 0 1 1 1

0 5 6 7, , ,( )=

shorthand form

0 0 0

0 0 10 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1

00

0

0

1

1

1

A B C F

truth table

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Review Examples 2 21


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Review Examples 2.211. Implement the following Boolean functions using simple AND, OR and NOT logic gates (do not simplify the functions):

(a) F =AB + ABC + CD (b) F = A BC + ABC + A B

(c) F = A + ABC + ABC (d) F = X Y Z(W + YZ) + ZW + X Y

2. Reduce the following expressions, using Boolean algebraic methods. State the relevant law or postulate used at each step.

(a)X.X.Y (b)X + X + Y (c) (X + X).B

(d) B+ B.A (e) Y.(Y+X) (f) (A+B).(A+C)

3. Using only the theory of Boolean algebra and algebraic manipulation, simplify the following Boolean expressions to a

minimum number of literals:(a)A + BC + (B + C)(B + A) (b)A + ABC + B

(c)AB D(A + BD) + DA + B C(d) (XY) + X Y + Z(X + YZ) + X Y

4. Using only the theory of Boolean algebra and algebraic manipulation, simplify the following Boolean expressions to a

minimum number of literals:

(a) X + XYZ + (Y + Z)(Y + X) (b)A + ABC + BC(c)XY Z(W + Y Z) + ZW + X Y(d) (XY) + XY + Z(X + YZ) + X Y

(e) WXYZ + WXYZ + WX YZ + WXY Z

5. A particular applications requires a 6 input NAND gate. You only have available an unlimited number of 2 input NAND

gates. Using these gates find a design for the 6 input NAND.

Notes: Top

K h M


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Karnaugh Maps 2.22

Karnaugh or K-maps are a form of truth table where (for small numbersof variables!) the minimisation of a standard SOP Boolean expression iseasy to see.

Adjacent squares only differ by one variable. Hence we can groupvertically or horizontally neighbouring squares (or pairs of squares,.....)

and eliminate one variable.

00 01 11 10

10

11

01

00

AB

CD

- - - 1

- - - 1

- - 1 1

1 1 1 1

ABCD ABCD+

ACD B B+( )=

ACD=ABCD ABCD+

ABC D D+( )=

ABC=

ACD ACD+

AC=

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K-Map Example 2 23


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K Map Example 2.23

00 01 11 10

10

11

01

00AB

CD

1 0 0 1

0 0 0 1

0 1 1 0

0 1 1 0

AD

Y A B C D, , ,( ) 0 2 6 9 11 13 15, , , , , ,( )=

Y ABCD ABCD ABCD ABCD ABCD ABCD ABCD+ + + + + +=

ACDABD

Y AD ABD ACD+ +=

Notes: Top

5 V i bl K M


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5 Variable K-Map 2.24

Above 5 variable K-map is difficult to use and we should revert to formalmethods.

00 01 11 10

10

11

01

00AB

CD

- - - 1

- - - -

- - -

- - - -

E 0=

00 01 11 10

10

11

01

00AB

CD

- - - 1

- - - -

- - - -

- - - -

E 0=

ABCD E E+( ) ABCD=

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Combinational Logic 2 25


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Combinational Logic 2.25

The NAND gate can be conveniently used to represent SOP Boolean

expressions.

Transformation achieved by using De-Morgans law:

Y ABC ABC AB+ +=

A

CB

A

CB

A

B

Y

A

CB

A

CB

A

B

Y

Y ABC ( ) ABC( ) AB( )=

X Y+ XY=

Notes: Top

NAND O l I l t ti


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NAND Only Implementation 2.26

Arbitrary logic circuits can be converted to NAND only using Booleanalgebraic manipulation, or the somewhat easier graphical manipulationwherepairs of inverters are added appropriately.

We convert the following circuit to NAND only:

A

B

E

C

D

Z

A

B

E

C

D

Z

F FF

Top

Examples 2.27


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p6. For each of the following functions give (i) the Karnaugh map representation, (ii) the truth table representation, and (iii) the

circuit diagram representation:

(a)H(W,X,Y,Z) = (1,3,5,7,9,11)(b)F(X,Y,Z) = XY + YZ + XYZ

(c)G(R,S,T) = (R+ S)(S + T) + R(ST+ T)

7. Convert the following circuit to (a) a NAND gate only implementation, and (b) a NOR gate only implementation. (Simply

addpairs of inverters where appropriate.) Confirm your answers by an algebraic analysis of the circuit.

A

B

C

D

E

Z

Notes: Top

MSI Components The Full Adder (FA)


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MSI Components - The Full Adder (FA) 2.28

Arithmetic is workhorse of most digital systems.

The simple Full Adder (FA):

Adds two bits + one carry in bit, to produce sum and carry out

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 11 1 0

1 1 1

0 0

0 1

0 1

1 0

0 1

1 01 0

1 1

A BCin Cout Sout Sout ABC ABC ABC ABC+ + +=

A B C =

Cout ABC ABC ABC ABC+ + +=

AB AC BC+ +=

Cout Cin

A B

Sout

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Parallel Adder 2.29


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Two four bit numbers (range 0-15) give up to five bit result (0-30).

Gate Count: 4 x 6 two input gates per FA cell.

A3 B3

S3

A2 B2

S2

A1 B1

S1

A0 B0

S0

0

S4

A3A2A1A0

B3 B2 B1 B0

S4 S3 S2 S1 S0

C3 C2 C1 C0

C0C1C2C3

LSBMSB

+0 carry in

Notes: Top

Parallel Adder Latency


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Parallel Adder Latency 2.30

The parallel adder is also known as a carry-ripple (through) adder.

In the worst case where a carry ripples from the LSB to the MSB(consider 0001 + 1111 = 10000) then the digit S4 is only valid after 4 FAdelays, i.e.

A carry lookahead addercan be used to speed up the carry ripply bydesigning few gate delays is the carry propagation line. However this

requires more hardware/gates.

4FA

10

0

10

0

10

0

11

0

0

1

1111

FAFAFAFA

Top

Parallel Subtractor I 2.31


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Using 2s complement a number can be negated by the process of:

Invertall bits then add 1

E.g. for 8 bit 2complement: 3 = 0000 0011and -3 = 1111 1100 +1 = 1111 1101

Performing this process with the parallel adder input circuitry producesa subtractorD A B A B( )+= =

1C4

A3 B3 A2 B2 A1 B1 A0 B0

D3 D2 D1 D0

Discard

add 1

Invert4 bit2s comp

Notes: Top

Parallel Subtractor II 2 32


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Parallel Subtractor II 2.32

For an Nbit subtractor, constrained to Nbit 2s complement results.

Overflow can be easily checked by noting the sign bits A3 and B3, andchecking that the result is consistent.

e.g. if adding two +ve values gives -ve result - overflow.

Can combine adder and subtractor to give controllable circuitK = 1 Subtract, & K = 0 Add. (K - Kontrol bit)

A3 A2 A1B1

A0

MUX

B0

MUX

B2

MUX

B3

MUX

K

0 10 10 10 1

Top

Serial Adder 2.33


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We can save on hardware, but increase latency time by using a

synchronous serial adder:

S0

Delay

clkPrime with K= 0 or 1

MUX

0 1

K= 0 or 1 (add or subtract)

S1 S2 SN-1

A0 A1 A2 AN-1B0 B1 B2 BN-1

time

time

Latency = Nx tclk

....

....

....

tclk

Notes: Top

Binary Multiplication 2 34


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Binary Multiplication 2.34

Consider the 4 bit multiply operations:

This can be mapped to produce a full parallel adder where the partialproducts, C, D, E, and F are each produced and added to the previouspartial product sum

i.e. C+D, then (C+D) + E, then (C+D+E) + F

1 0 1 11 0 0 1

1 0 1 10 0 0 0

0 0 0 01 0 1 1+

1 1 0 0 0 1 1

11x9

99

a3 a2 a1 a0b3 b2 b1 b0

c3 c2 c1 c0d3 d2 d1 d0

e3 e2 e1 e0f3 f2 f1 f0

p7 p6 p5 p4 p3 p2 p1 p0

Top

Parallel Multiplier Circuit 2.35


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The dotted path shows the maximum latency.

0

0

0

0

0

000 a0a1

b3

a2a3

b0

b2

b1

p0p7 p6 p5 p4 p3 p2 p1

Binary Multiplier:P= A xB

a

aout

bbout

s

sout

cout = z.c + s.z + s.c

ccout

z = a.bbout = b

aout = a

sout = (s z) c

FA

FA is full adder

z

Notes: Top

Serial Multiplier Circuit 2 36


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Serial Multiplier Circuit 2.360

0

0

0

0

000 a0a1

b3

a2a3

b0

b2

b1

0

a0a1a2a3

b0b1 b2b3One clock Delay

pi

timing cuts

Projectiondirection

Top

Flip Flops 2.37


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Introducing feedback into a circuit, introduces the possibility that

current output/state (at time, t) can influence the next output/state(at time t+). This produces a sequential system.

Feedback at the device level is integrated via standard flip-flops.

Simple form of memory element in the SR (Set/Reset) latch:

R

S

Q

Q

0 0 0

0 0 10 1 0

0 1 1

1 0 01 0 1

1 1 0

1 1 1

0

10

0

11

S R Q(t) Q(t+)

Not allowed by

Q t +( ) S RQ t ( )+ SR 1=

Characteristic Equationdefinition of S and R

Notes: Top

Gated SR Latch 2.38


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Gated SR Latch 2.38

Can set up an Enable (EN) line that only allows the inputs to be latched

when EN = 1:

R

S

Q

Q

EN

EN

S

R

Q

Q

Symbol

Top

Gated D Latch 2.39


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Connecting together S and R as shown, we can produced a data orD-

type latch:

D

EN

EN

D Q

Q

Symbol

0 0 0

0 1 01 0 1

D Q(t) Q(t+)

1 1 1

Q

Q

Notes: Top

Edge Triggered Flip Flops 2.40


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g gg p p

Enabled latches/FFs are transparent when EN = 1.

It is desirable to make the FFs more edge triggered, with a specific (butsmall) set up time and hold time.

A simple model of an edge detector that could be used at the EN(enable) input of a latch is:

F

time

timetime

Propagation delay of inverter, inv

00

0

clk

clk

Edge Detect

Top

Positive Edge Triggered D-type 2.41


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Using an edge detector circuit we can produce a positive edge (+ve)triggered D type FF:

D

clk

D Q

Q

Symbol

0 0 0

0 1 01 0 1

D Q(t) Q(t+)

1 1 1

EdgeDetectclk

Q

Q

Notes: Top

Negative Edge Triggered D-type 2.42


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g g gg yp

Using an edge detector circuit we can also produce a positive edge

(+ve) triggered D-type FF:

D

Q

Q

clk

D Q

Q

Symbol

0 0 0

0 1 0

1 0 1

D Q(t) Q(t+)

1 1 1

EdgeDetectclk

Top

JK Flip Flop 2.43


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The JK flip flop (J - SET, K - Klear) is similar to the SR, expect that thecondition ofJ = K = 1 has a defined operation.

J = K = 1 then FF output will toggle (from state 0 to 1 or 1 t o 0 ).

The Jand Kinputs are synchronous (controlled by the clock):

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 11 1 0

1 1 1

0

1

0

0

1

11

0

J K Q(t) Q(t+)

Q t +( ) JQ t( ) KQ t( )+=

Characteristic Equation

clk

J Q

Q

Symbol

K

Notes: Top

JK Asynchronous Inputs 2.44


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The JK often has two asynchronous inputs (i.e. not controlled or affected

by the clock input):

Asserted LO inputs, e.g. P = 0 forces Q = 1,C = 0 forces Q = 0

regardless of clk input.

clk

J Q

QK

Preset

(Pre)Clear

P

C

Top

Flip Flop Key Operating Characteristics 2.45

LO t HI ti d lt


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LO to HI propagation delayHI to LO propagation delay

Minimum pulse width for clock, preset, preclear

Setup and hold times are defined for edge triggered FFs. Inputs mustbe held fixed during and or output is likely to beunpredictable.

tplhtphl

tsetup

thold

time0

clk

time0

J

tsetup thold

ViolationOK

time0

Q ??????

tplh

Setup

Notes: Top

Metastability 2.46


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A flip-flop enters a metastable state when its timing requirements (setup

and hold times) are violated

The period of metastability lasts for a short time and then a 0or1 outputis settled upon... however...

The value of this output is non deterministic - which can potentially

destroy the functionality of the entire design!

Clock

Setup

Time

Hold

Time

Data must not change during

setup and hold times.

ActiveClockEdge

Clock

No violations

Setup violation

Hold violation

0 1 0

0 ?

?0

M

M

A period of metastability follows a setup or

hold violation. The output then settles to a

random value.

Top

Metastability Details 2.47

Whil i th t t bl t t th lt b h b t


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While in the metastable state, the voltage may be somewhere betweenthose required for the two valid states. Another possibility is for theoutput to oscillate between the two states for some period of time.

In both cases, the period of metastability ends with one of the two validstates... however the eventual output value may be incorrect.

The time taken to resolve the eventual output (correctly or otherwise!)also constitutes an extra and undesirable delay in the output.

Metastability is encountered when dealing with signals which areasynchronous to the clock. Some areas which are potentiallyvulnerable to metastability effects are:

External inputs

Crossing clock domains

Resets

Notes: Top

Metastability Solutions 2.48


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Prior to applying an asynchronous input to a synchronous system, one

or more synchronising flip-flops may be used.

A common approach is to use two cascaded flip-flops to reduce thechance of metastability. In this case Y, a potentially metastable output

from Flip-flop A, should have settled down before Flip-flop B samples it.

There is still some small chance of failure, which is calculable.

D Q D QSynchronous

Design

Asynchronous

Input X Y Z

Clock

Synchroniser

A B

Top

JK for Frequency Division 2.49

The JK can be used for simple frequency division


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The JK can be used for simple frequency division

Setting J = K = 1 (toggle mode):

Input clock frequency is divided by 2.

clkJ Q

QKtime0

clk

1

1

time0

Q

0

0 1 0 1 0

1 0 1

10

Notes: Top

Ripple or Asynchronous Counter 2.50


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Cascade JKs in toggle mode to produce a 0-15 ripple counter:

clk

J Q

QK

1

1

J Q

QK

1

1

J Q

QK

1

1

J Q

QK

1

1

Fill in the timing diagram:

D

BCD

C

B

A

clk

time

0 1 0 1 010 1 0

A

LSB

MSB

TopState Diagram 2.51

The state diagram for the above 0 15 counter is (state = ABCD)


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The state diagram for the above 0-15 counter is (state = ABCD)

0011

0001

0101

0110

01111000

10011010

1011

1100

1101

1110

0000

0010

0100

1111

Notes: Top

Count Direction 2.52


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Using +ve edge triggers gives a downcounter for ABCD:

clk

J Q

QK

1

1

J Q

QK

1

1

J Q

QK

1

1

J Q

QK

1

1

Fill in the timing diagram:

D

BCD

C

B

A

clk

time

0 1 0 1 010 1 0

A

TopTransition States 2.53

Because this type of counter is asynchronous (i e no sync clock for all


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Because this type of counter is asynchronous (i.e. no sync clock for allFFs) then due to propagation delay there will be transition states:

clk

1

1

JQ

Q K

1

1

JQ

Q K

1

1

JQ

Q K

1

1

B CA

000

001

010

100

011101

110

111

010000

000

100

110100

Duration of transition statesfunction of propagation delay

Notes: Top

Resettable Decade Counter 2.54


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On reaching state ABCD = 1010 (ten) then the counter resets to zero.

Problems? Transitions states, and reset state (1010 exists for a veryshort time).

clk

J Q

QK

1

1

J Q

QK

1

1

J Q

QK

1

1

J Q

QK

1

1

BCD A

A

C

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