CLASS GRADING HOMEWORKS PROJECTS REVIEW OF DIGITAL LOGIC.
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Transcript of CLASS GRADING HOMEWORKS PROJECTS REVIEW OF DIGITAL LOGIC.
• CLASS
• GRADING
• HOMEWORKS
• PROJECTS
• REVIEW OF DIGITAL LOGIC
Digital Design using Digital Design using VHDL and VerilogVHDL and Verilog
Marek Perkowski
Department of Electrical and Computer Engineering
Portland State University
IntroductionIntroduction• Administration
• About Review
• RASSP Program
• Why VHDL?
• Flip-Flops (see ECE 271 class slides)
• Shift Registers
• Generalized Register
• Pipelined Sorter
AdministrationAdministration• Instructor: Prof. Marek A. Perkowski
• Course Information– My home page http://ee.pdx.edu/~mperkows– Computer Engineering web site
•http://ece.pdx.edu
AdministrativeAdministrative
• Office– FAB room 160-05
• Office Hours– Fridays 6 pm - 10 pm - meetings in FAB, room 150– Other Times by Appointment
• Office Phone– (503)725-5411 (Answering Machine)
AdministrativeAdministrative• Email
• Students with Disabilities– If you need special assistance, please inform me soon so
that we can work something out.
• There is a milestone chart available on the class web site.
GradingGrading• HW 35%
– Assignments are on the web, may be changed. If changed, I will inform you. Usually these are mini-projects. You may be asked to present them in class.
• Final Project 65%– You will present it in class
• No exams
GradingGrading• Attendance at Lecture
– Not graded, but recommended.– Attendance at Friday meetings not graded, come if you
can.
• Makeup Exams– Makeup homeworks or exams are not given. – Project should be completed before end of the class
HomeworksHomeworks• Homeworks Require Use of VHDL
• Always you have to simulate the circuit
• You may be asked to synthesize it also.
• Mentor Graphics Tools– contact support (cat)support (cat) people– use any lab that is available. Work at home.– use addpkg– We use Modelsim for simulation and LeonardoSpectrum
for synthesis. Synthesis is mandatorymandatory for the project.
SlidesSlides• My slides are based on at least 5 books, slides from
Internet and my industrial experience, on top of teaching this class since 1989. You can learn all you need if you read slides in detail.
• Not always I will cover all slides in class. In such case you have to complete reading slides for this week at home.
• You can learn a lot from previous homeworks and projects that are posted.
RequiredRequired and Additional Textbooks and Additional Textbooks
• Required and recommended– VHDL and FPLDs. Zoran Salcic. CD ROM included.
Kluwer Academic Publishers– see my web page
• Additional– The Designer’s Guide to VHDL
• Peter J. Ashenden• Morgan-Kaufman• ISBN 1-55860-270-4 (paperback)• LOC TK7888.3.A863• Dewey Decimal 621.39’2--dc20• 1996
ResourcesResources• IEEE Standard 1076-1993
– find using search engines on WWW
• Use my WWW Page resources, too much to digest.
• IEEE Interactive VHDL Tutorial– On-line on Computer Engineering Home page– http://cpe.gmu.edu – password protected
ResourcesResources• Our Book
• Cypress Semiconductor (Warp release 5.x)– PC-based– $99 with textbook– Oriented towards Their PLD & FPGA devices– VHDL Subset simulator
• Xilinx FPGA– Student edition– Schematic, FSM, VHDL
Honor CodeHonor Code• You Are Encouraged to Collaborate With Other
Students in Projects.
• Final VHDL code for each Homework should be done by yourself.
• In Final Project, each file should have at the top student name of the student responsible for this part of code.
Remind the class….Remind the class….
• Your webpagewebpage• List of your names with interests and experiences. Previous
design projects that you have done.– Any experience in robotics?– Any experience in pipelined and systolic processors?– Any experience with image processing?– Previous VHDL or Verilog projects.– C++ experience– Other languages like LISP, Prolog, Basic, etc.– I will intentionally repeat the most important parts of material or
ideas. I believe in real understanding of material by students and good understanding of fundamentals is most important for me.
– You have to understand the combinational logic, flip-flops, registers, state diagrams, pipelining, ALU, etc.
Homework 1Homework 11. Simple Satisfiability Machine 2. Simple Petric Function Oracle based machine3. Any type of Sorter4. Fibonacci sequence generator5. GCD6. LCM7. Any other controller from CU and DP.8. Any other oracle, SEND+MORE=MONEY, graph
coloring, etc.
These are just examples, more projects will be added, you can propose your own project.
Projects for year 2008 Projects for year 2008 TransformsTransforms
1. Hough Transforms2. Radon Transforms3. Fast Fourier Transform4. Hadamard5. Haar6. Adding7. Arithmetic8. Gabor
These are just examples, more projects will be added, you can propose your own project.
Projects for year 2008 Projects for year 2008 OraclesOracles
1. Graph Coloring (optimized)
2. FPRM learning
3. Logic Puzzles
4. Error Correcting codes design
5. Traveling Salesman
6. Any other oracles with practical use
These are just examples, more projects will be added, you can propose your own project.
Projects for year 2008 Cellular Projects for year 2008 Cellular Automata and RoboticsAutomata and Robotics
1. Mandelbrot Set with quaternions and octonions2. Robot Vision with morphological algebras3. Galois Field Arithmetics for robot vision4. Neural Net for a robot5. PID controller for a robot6. Sum of Product minimization for a robot7. Decision trees in hardware for robot8. Car model control9. Logic Decomposition
These are just examples, more projects will be added, you can propose your own project.
Projects for year 2008 Cellular Projects for year 2008 Cellular Automata and RoboticsAutomata and Robotics
1. Hidden Markov Model
2. Kalman Filter for robot
3. Particle Filter for robot obstacle avoidance
4. Genetic Algorithm in hardware
These are just examples, more projects will be added, you can propose your own project.
Projects for year 2008 Projects for year 2008 RoboticsRobotics
1. Speech Recognition for a robot (new)
2. Rough Set Machine (continuation - Torrey Lewis)
3. Convolutional Image Processor (continuation)
4. Controller of a Robot (new)
5. Evolvable Hardware (new)
These are just examples, more projects will be added, you can propose your own project.
ReviewReview
•Mealy and Moore
•Registered Output
•Rabin-Scott
Digital System RepresentationDigital System Representation
Basic Logic FunctionsBasic Logic Functions
Logic Synthesis Using AND, Logic Synthesis Using AND, OR and NOT gatesOR and NOT gates
Function Minterms and Function Minterms and MaxtermsMaxterms
Discuss generator of all functions of certain type, use MUX as example
Example: 3-variable functionExample: 3-variable function
Example: 3-variable functionExample: 3-variable function
NAND, NOR, and De NAND, NOR, and De Morgan’s TheoremMorgan’s Theorem
Realizing Sum of Products (SOP) using Realizing Sum of Products (SOP) using NAND/NANDNAND/NAND
Realizing Product of Sums Realizing Product of Sums (POS) using NOR/NOR(POS) using NOR/NOR
Digital System Design: AdderDigital System Design: Adder
Iterative Structure of AdderIterative Structure of Adder
Full AdderFull Adder
Full Adder Full Adder RealizationRealization
Implementation Using MultiplexersImplementation Using Multiplexers
Binary Decoder CircuitsBinary Decoder Circuits
A 2-to-4 Decoder with EnableA 2-to-4 Decoder with Enable
FA implementation using DecodersFA implementation using Decoders
D Flip-FlopD Flip-Flop
Sequential (Bit-Serial) AdderSequential (Bit-Serial) Adder
Sequential AdderSequential Adder
Behavioral Model of Sequential AdderBehavioral Model of Sequential Adder
To discuss on white-boardTo discuss on white-board• Sorting data flow
– Pipelined circuit from it– Butterfly combinational circuit from it– Sequential controller from it
• The concepts:– Combinational circuit– Finite State machine– Shifting circuits, starting from Moebius Counter. (Johnson)– Cooperating FSMs.– Iterative Circuit– Pipelined circuit– Systolic circuit– Cellular automaton
For students to rememberFor students to remember• SOP and POS• Nand, Nor and De Morgan• Multiplexer• Decoder • Adder• Iterative circuit for adder• Other iterative circuits• D flip-flop• Flip-flop and register without and with enable.• Use of enable in other circuits• Sequential versus parallel circuits – trade-off.
Some materials from Some materials from AlnuweiriAlnuweiri