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EE141 – Fall 2005

Tu & Th 11-12:30203 McLaughlin

Digital Integrated Circuits

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What is This Class About?

Introduction to Digital Integrated Circuits• Introduction: Issues in digital design• CMOS devices and manufacturing technology• The CMOS inverter• Combinational logic structures• Propagation delay, noise margins, power• Sequential logic gates; timing• Arithmetic building blocks• Interconnect: R, L and C• Memories and array structures• Design methods

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What will You Learn?

Understanding, designing, and optimizing digital circuits with respect to different quality metrics:

• Power dissipation

• Speed

• Reliability

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Interludium: Administrativia

Instructor

Dejan Markovicdejan@eecs.berkeley.eduOffice hours: 511 CoryWed 10:00-12:00pm

Ke LuDiscussion + labkelu@berkeley.eduOffice Hours: TBD

Lynn WangDiscussion + labting0918@eecs.berkeley.eduOffice Hours: TBD

TAs

ReaderTBD

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The Web-Site

Class and lecture notesAssignments and solutionsLab and project informationExamsMany other goodies …

The sole source of informationhttp://bwrc.eecs.berkeley.edu/Classes/ee141

Save a tree!

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Class Admission

The class is over-enrolled!• 72 enrolled, 30 waitlisted, 60 rejected

Waitlist priority• Graduating seniors• Grad students (prelim)• Other grad students, Juniors

We can accommodate ~75 students

Make sure your name is on the class roll!

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Discussions and Labs

Discussion sessions• Mo 1-2pm, 203 McLaughlin• Mo 5-6pm, 293 Cory• Pick any of the two

(they are covering the same material)

Labs (353 Cory)• Mo 3-6pm• Tu 3:30-6:30pm class poll: move to Wed?• Th 3:30-6:30pm• Pick the one that fits you the best

(pending availability) and STICK TO IT!

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TAmtng

ProblemSets Due

* Discussion sessions will cover identical material

Your EE141 Week at a Glance

Mon

Tue

Wed

Thu

Fri

Lec(Dejan)

203 McLaughlin

Lec(Dejan)

203 McLaughlin

OH(Dejan)511 Cory

Lab (Ke) 353 CoryDISC*(Lynn)

293 Cory

DISC*(Ke)203

McLaughlin

9 10 11 12 1 2 3 4 5 6 7

Lab(Lynn/Ke)

353 Cory

Lab(Lynn)353 Cory

OH(TA1)

TBD

OH(TA2)

TBD?

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Class Organization

9 homework assignments

2 design projects

Labs: 5 software, 1 hardware

Exams: 2 midterms, final• Midterm 1: Th October 6, 6:30-8:00pm • Midterm 2: Th November 10, 6:30-8:00pm• Final: Th December 15, 5-8pm

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Grading Policy

Homeworks: 10%Labs: 10%Projects: 20%Midterms: 30%Final: 30%

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Class Material

Textbook: Digital Integrated Circuits: A Design Perspective, by J. Rabaey, A. Chandrakasan, B. Nikolic, 2nd Edition, (Prentice Hall 2002)

Lab manuals• Available on the web-page

Check web-page for the availability of toolshttp://bwrc.eecs.berkeley.edu/Classes/ee141

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Software

Cadence software only!• Phased out the Micromagic software• Online documentation and tutorials

HSPICE and IRSIM for simulation

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Getting Started

Assignment 1: Getting SPICE to work • see web-page• also “The SPICE Book”, by A. Vladimirescu

No discussion sessions or labs this week• First discussion sessions in Week 2• First software lab in Week 3

EE141 – Fall 2005Lecture 1

Introduction

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Introduction

Why is designing digital ICs different today than it was before?

Will it change in the future?

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The First Computer (1832)

The Babbage Difference Engine• 25,000 parts• cost: £17,470

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ENIAC – The First Electronic Computer (1946)

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The Transistor Revolution

First transistorBell Labs (1948)

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The First Integrated Circuits

Bipolar logic(1960’s)

ECL 3-input GateMotorola (1966)

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Intel 4004 Microprocessor (1971)

2,300 transistors (12mm2)108 KHz operation (10µm)

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Evolution in Transistor Count

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Intel Pentium 4 Microprocessor

Intel (2000) 42 M transistors (217mm2)1.5 GHz operation (0.18µm)

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What Happened over 30 Years?

42 M transistors1.5 GHz operation

1971 2000

2,300 transistors108 KHz operation ~15,000 x

Comparison (automotive): Travel from San Francisco to New York in 13 sec!

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Moore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months

He made a prediction that semiconductor industry will double its effectiveness every 18 months

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Moore’s Law

16151413121110

9876543210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LOG

2 OF

THE

NU

MB

ER O

FC

OM

PON

ENTS

PER

INTE

GR

ATE

D F

UN

CTI

ON

Source: Electronics, April 19, 1965.

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Evolution in Complexity

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Microprocessor Examples

Moore’s Law• Number of transistors• Logic density• Die size• Frequency• Power

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40048008

80808085 8086 (P1)

286 (P2)386 (P3)

486 (P4)Pentium® (P5)

Pentium Pro (P6)

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tran

sist

ors

(MT)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years

Moore’s Law in Microprocessors

Source:S. Borkar(Intel)

Pentium 4

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Pentium (R)Pentium Pro (R) 486

386i860

1

10

100

1000

1.5µ

1.0µ

0.8µ

0.6µ

0.35µ

0.25µ

0.18µ

0.13µ

Logi

c D

ensi

ty

2x trend

Logi

c Tr

ansi

stor

s/m

m2

Pentium II (R)

Moore’s Law – Logic Density

Shrinks and compactions meet density goals• New micro-architectures drop density

Source: Intel

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Die Size Growth

40048008

80808085

8086286

386486 Pentium ®

Pentium Pro

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law

Source:S. Borkar(Intel)

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Frequency

Pentium ProPentium ®

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Freq

uenc

y (M

hz)

Doubles every2 years

Source:S. Borkar(Intel)

Lead Microprocessor frequency doubles every 2 yearsLead Microprocessor frequency doubles every 2 years

Pentium 4

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386486

Pentium(R)

Pentium Pro(R)

Pentium(R) IIMPC750

604+604

601, 603

21264S

2126421164A

2116421064A

21066

10

100

1,000

10,000

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

Mhz

1

10

100

Gat

e D

elay

s/ C

lock

IntelIBM Power PCDECGate delays/clock

Processor freq scales by 2X per

generation

Processor Frequency Trend

Source:V. De, S. BorkarISLPED’99

Frequency doubles each generation• Number of gates/clock reduce by 25%

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Power

Pentium ProPentium ®

486386

2868086

808580808008

4004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Pow

er (W

atts

)

Source:S. Borkar(Intel)

Lead Microprocessor power continues to increaseLead Microprocessor power continues to increase

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Processor Power

386 386

486 486

Pentium(R) Pentium(R) MMX

Pentium Pro (R)

Pentium II (R)

1

10

100

1.5µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ

Max

Pow

er (W

atts

) ?

Lead processor power increases every generation• Compactions provide higher performance at lower power

Source: Intel

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Power will be a Problem

5KW 18KW

1.5KW 500W

400480088080

80858086

286386

486Pentium ®

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Pow

er (W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

Source:S. Borkar(Intel)

Pentium Pro

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Power Density will Increase

400480088080

8085

8086

286 386486

Pentium ®Pentium Pro

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (W

/cm

2 )

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low TempPower density too high to keep junctions at low Temp

Source:S. Borkar(Intel)

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Power Delivery Challenges

Pentium ProPentium®

486386286

8086

80858080

800840040.01

0.10

1.00

10.00

100.00

1,000.00

1970 1980 1990 2000 2010Year

Icc

(am

p)

Pentium ProPentium ®

486386

286

8086

80858080

80084004

1.E-041.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07

1970 1980 1990 2000 2010Year

L(di

/dt)/

Vdd

High supply currents at low voltage:Challenges: IR drop and L(di/dt) noiseHigh supply currents at low voltage:

Challenges: IR drop and L(di/dt) noise

Source: S. Borkar (Intel)

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Not Only Microprocessors

Digital Cellular Market(Phones Shipped)

Analog Baseband

Digital Baseband(DSP + MCU)

PowerManagement

Small Signal RF

PowerRF

CellPhone

(889)(836)(776)(703)64851343516248Units (M)200820072006200520042003200019981996Year

Sources: Gartner Dataquest, CTIA, Strategy Analytics

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Other Wireless Devices

CellTx

TV

PAN

LAN

WAN

700M

30M

180,464,003 subscribers in US

Computation ⇔ Communication

95% by 2006

Throughput ↑, Complexity ↑, Power ↑Throughput ↑, Complexity ↑, Power ↑

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Productivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000Logic Tr./ChipTr./Staff Month.

xxx

xxx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Logi

c Tr

ansi

stor

per

Chi

p(M

)

0.01

0.1

1

10

100

1,000

10,000

100,000

Prod

uctiv

ity(K

) Tra

ns./S

taff

-Mo.

Com

plex

ity

Complexity outpaces design productivityComplexity outpaces design productivity

Source: Sematech

Today

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∝ DSM ∝ 1/DSM

?

Challenges in Digital Design

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and there’s a lot of them!

“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock Distribution

Everything looks a little different

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n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

Design Abstraction Levels

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Why Scaling?

Technology shrinks by 0.7 per generationWith every generation can integrate 2x more functions per chip; chip cost does not increase significantlyCost of a function decreases by 2xHow to design chips with more and more functions?Design engineering population does not double every two years…Need to understand different levels of abstraction

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2010 Outlook

Performance 2x / 16 months• 1 T instructions/s• 20-30 GHz clock

Complexity• No of transistors: 1 Billion• Die area: 40mm x 40mm

Power• 10kW!• Leakage: 1/3 of total Power

P. Gelsinger, µProcessors for the New Millennium, ISSCC 2001

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Next Class

Introduce basic metrics for design of integrated circuits – how to measure delay, power etc.

Brief intro to IC manufacturing and design