EE141- Spring 2005 Digital Integrated...
Transcript of EE141- Spring 2005 Digital Integrated...
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EE141EE141-- Spring 2005Spring 2005Digital Integrated Digital Integrated CircuitsCircuits
Lecture 25Lecture 25Power distributionPower distributionResistive interconnectResistive interconnectMemoryMemory
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Administrative StuffAdministrative StuffPoster presentations next Th.
Sign up for time slot in 511 CoryPoster template on web-site
Homework 8 posted Fridaydue next Fr. May 6, 5pm
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Class MaterialClass Material
Today’s lecturePower distributionRC Interconnect optimizationMemory
– SRAM– ROM
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Power Power DistributionDistribution
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Impact of ResistanceImpact of ResistanceWe have already learned how to drive RC interconnectImpact of resistance is commonly seen in power supply distribution:
IR dropVoltage variations
Power supply is distributed to minimize the IR drop and the change in current due to switching of gates
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RI Introduced NoiseRI Introduced Noise
M1
X
I
R9
RDV
f pre
DV
VDD
VDD 2 DV9
I
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Resistance and the Power Resistance and the Power Distribution ProblemDistribution Problem
Source: Cadence
•• Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction•• Heavily influenced by packaging technologyHeavily influenced by packaging technology
BeforeBefore AfterAfter
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Power DistributionPower DistributionLow-level distribution is in Metal 1Power has to be ‘strapped’ in higher layers of metal.The spacing is set by IR drop, electromigration, inductive effectsAlways use multiple contacts on straps
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Power and Ground DistributionPower and Ground Distribution
GND
VDD
Logic
GND
VDD
Logic
GND
VDD
(a) Finger-shaped network (b) Network with multiple supply pins
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3 Metal Layer Approach (EV4)3 Metal Layer Approach (EV4)3rd “coarse and thick” metal layer added to the
technology for EV4 designPower supplied from two sides of the die via 3rd metal layer
2nd metal layer used to form power grid90% of 3rd metal layer used for power/clock routing
Metal 3
Metal 2Metal 1
Courtesy Compaq
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4 Metal Layers Approach (EV5)4 Metal Layers Approach (EV5)4th “coarse and thick” metal layer added to the
technology for EV5 designPower supplied from four sides of the dieGrid strapping done all in coarse metal
90% of 3rd and 4th metals used for power/clock routing
Metal 3
Metal 2Metal 1
Metal 4
Courtesy Compaq
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2 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/Vss
Significantly lowers resistance of gridLowers on-chip inductance
6 Metal Layer Approach 6 Metal Layer Approach –– EV6EV6
Metal 4
Metal 2Metal 1
RP2/Vdd
RP1/Vss
Metal 3
Courtesy Compaq
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ElectromigrationElectromigration (1)(1)
Limits dc-current to 1 mA/µm
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ElectromigrationElectromigration (2)(2)
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The Impact of The Impact of ResistivityResistivity
CN-1 CNC2
R1 R2
C1
Tr
Vin
RN-1 RN
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge (
V)
x= L/10
x = L/4
x = L/2
x= L
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge (
V)
x= L/10
x = L/4
x = L/2
x= L
Diffused signal Diffused signal propagationpropagation
Delay ~ LDelay ~ L22
The distributed The distributed rcrc--lineline
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The Global Wire ProblemThe Global Wire Problem
ChallengesNo further improvements to be expected after the introduction of Copper (superconducting, optical?)Design solutions
Use of fat wiresInsert repeaters — but might become prohibitive (power, area)Efficient chip floorplanning
Towards “communication-based” design How to deal with latency?Is synchronicity an absolute necessity?
( )outwwdoutdwwd CRCRCR693.0CR377.0T +++=
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Interconnect:Interconnect:# of Wiring Layers# of Wiring Layers
# of metal layers is steadily increasing due to:• Increasing die size and device count: we need more wires and longer wires to connect everything
• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC
substrate
poly
M1
M2
M3
M4
M5
M6
Tins
H
WS
ρ = 2.2 µΩ-cm
0.25 µm wiring stack
Minimum Widths (Relative)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.0µ 0.8µ 0.6µ 0.35µ 0.25µ
M5M4M3M2M1Poly
Minimum Spacing (Relative)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1.0µ 0.8µ 0.6µ 0.35µ 0.25µ
M5M4M3M2M1Poly
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Interconnect Projections: CopperInterconnect Projections: CopperCopper is planned in full sub-0.25 µm process flows and large-scale designs (IBM, Motorola, IEDM97)With cladding and other effects, Cu ~ 2.2 µΩ-cm vs. 3.5 for Al(Cu) ⇒40% reduction in resistanceElectromigration improvement; 100X longer lifetime (IBM, IEDM97)
Electromigration is a limiting factor beyond 0.18 µm if Al is used (HP, IEDM95)
Vias
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Diagonal WiringDiagonal Wiring
y
x
destination
Manhattan
source
diagonal
• 20+% Interconnect length reduction• Clock speed
Signal integrityPower integrity
• 15+% Smaller chips plus 30+% via reduction
Courtesy Cadence X-initiative
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Reducing RCReducing RC--delaydelay
Repeater
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Repeater Insertion (Revisited)Repeater Insertion (Revisited)Taking the repeater loading into account
For a given technology and a given interconnect layer, there exiFor a given technology and a given interconnect layer, there exists sts an optimal length of the wire segments between repeaters. The an optimal length of the wire segments between repeaters. The delay of these wire segments is delay of these wire segments is independent of the routing layer!independent of the routing layer!
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INTERCONNECTINTERCONNECT
Dealing with InductanceDealing with Inductance
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L L didi//dtdt
Impact of inductance on supply voltages:• Change in current induces the change in voltage• Longer supply lines have larger L
CL
V’DD
VDD
L i(t)
VoutV in
GND ’
L
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L L didi//dtdt: Simulation: Simulation
t
t
t
vout
iL
vL
20mA
40mA
5V
0.2V
0.01.02.03.04.05.0
V out
(V)
0
10
20
I L (m
A)
2 4 6 8 10t (nsec)-0.3
-0.1
0.1
0.3
0.5
V L(V
)
tfall = 0.5 nsec
tfall = 4 nsec
Signals Waveforms for Output Driver connected To Bonding Pads(a) vout; (b) iL and (c) vL.
The Results of an Actual Simulation are Shown on the Right Side.
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Choosing the Right PinChoosing the Right Pin
ChipL
L ´
Bonding wire
Mountingcavity
Leadframe
Pin
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Decoupling CapacitorsDecoupling Capacitors
Decoupling capacitors are added: • on the board (right under the supply pins)• on the chip (under the supply straps, near large buffers)
SUPPLY
Boardwiring
Bondingwire
Decouplingcapacitor
CHIPCd
1
2
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DeDe--coupling Capacitor Ratioscoupling Capacitor RatiosEV4
total effective switching capacitance = 12.5nF128nF of de-coupling capacitancede-coupling/switching capacitance ~ 10x
EV513.9nF of switching capacitance 160nF of de-coupling capacitance
EV634nF of effective switching capacitance320nF of de-coupling capacitance -- not enough!
Source: B. Herrick (Compaq)
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EV6 DeEV6 De--coupling Capacitancecoupling CapacitanceDesign for ∆Idd= 25 A @ Vdd = 2.2 V, f = 600
MHz0.32-µF of on-chip de-coupling capacitance was added
– Under major busses and around major gridded clock drivers– Occupies 15-20% of die area
1-µF 2-cm2 Wirebond Attached Chip Capacitor (WACC) significantly increases “Near-Chip” de-coupling
– 160 Vdd/Vss bondwire pairs on the WACC minimize inductance
Source: B. Herrick (Compaq)
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EV6 WACCEV6 WACC
587 IPGA
MicroprocessorWACC
Heat Slug
389 Signal - 198 VDD/VSS Pins389 Signal Bondwires
395 VDD/VSS Bondwires320 VDD/VSS Bondwires
Source: B. Herrick (Compaq)
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Design Techniques to address L Design Techniques to address L didi//dtdt
Separate power pins for I/O pads and chip coreMultiple power and ground pinsPosition of power and ground pins on packageIncrease tr and tfAdvanced packaging technologiesDecoupling capacitances on chip and on board
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MemoryMemory
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Issues in MemoryIssues in Memory
Memory ClassificationMemory ArchitecturesThe Memory CorePeripheryReliabilityCase Studies
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Semiconductor Memory ClassificationSemiconductor Memory Classification
Read-Write MemoryNon-VolatileRead-Write
MemoryRead-Only Memory
EPROM
E2PROM
FLASH
RandomAccess
Non-RandomAccess
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO
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Memory Timing: DefinitionsMemory Timing: Definitions
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Memory Architecture: DecodersMemory Architecture: Decoders
Word 0
Word 1
Word 2
Word N2 2
Word N2 1
Storagecell
M bits M bits
N
w o r d s
S0
S1
S2
SN2 2
A 0
A 1
AK2 1
K 5 log2N
SN2 1
Word 0
Word 1
Word 2
Word N2 2
Word N2 1
Storagecell
S0
Input-Output(M bits)
Intuitive architecture for N x M memoryToo many select signals:
N words == N select signals K = log2NDecoder reduces the number of select signals
Input-Output(M bits)
D e c o d e r
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ArrayArray--Structured Memory ArchitectureStructured Memory Architecture
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Hierarchical Memory ArchitectureHierarchical Memory Architecture
Advantages:Advantages:1. Shorter wires within blocks1. Shorter wires within blocks2. Block address activates only 1 block => power savings2. Block address activates only 1 block => power savings
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Block Diagram of 4 Block Diagram of 4 MbitMbit SRAMSRAM
Subglobalrow decoder
Global row decoder
Subglobalrow decoder
Block 30
Block 31
128 K Array Block 0
Block 1
Clockgenerator
CS, WEbuffer
I/Obuffer
Y-addressbuffer
X-addressbuffer
x1/x4controller
Z-addressbuffer
X-addressbuffer
Predecoder and block selectorBit line load
Transfer gateColumn decoder
Sense amplifier and write driverLocal row decoder
[Hirose90]
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ReadRead--Only Memory CellsOnly Memory Cells
WL
BL
WL
BL
1WL
BL
WL
BL
WL
BL
0
VDD
WL
BL
GND
Diode ROM MOS ROM 1 MOS ROM 2
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MOS OR ROMMOS OR ROM
WL[0]
VDD
BL[0]
WL[1]
WL[2]
WL[3]
Vbias
BL[1]
Pull-down loads
BL[2] BL[3]
VDD
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MOS NOR ROMMOS NOR ROM
WL[0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Pull-up devices
BL [2] BL [3]
GND
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MOS NOR ROM LayoutMOS NOR ROM Layout
Programmming using theActive Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (9.5λ x 7λ)
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MOS NOR ROM LayoutMOS NOR ROM Layout
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (11λ x 7λ)
Programmming usingthe Contact Layer Only
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MOS NAND ROMMOS NAND ROM
All word lines high by default with exception of selected row
WL [0]
WL [1]
WL [2]
WL [3]
VDDPull-up devices
BL [3]BL [2]BL [1]BL [0]
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MOS NAND ROM LayoutMOS NAND ROM Layout
No contact to VDD or GND necessary;
Loss in performance compared to NOR ROMdrastically reduced cell size
Polysilicon
Diffusion
Metal1 on Diffusion
Cell (8λ x 7λ)
Programmming usingthe Metal-1 Layer Only
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NAND ROM LayoutNAND ROM LayoutCell (5λ x 6λ)
Polysilicon
Threshold-alteringimplant
Metal1 on Diffusion
Programmming usingImplants Only
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Equivalent Transient Model for MOS NOR ROMEquivalent Transient Model for MOS NOR ROM
Word line parasiticsWire capacitance and gate capacitanceWire resistance (polysilicon)
Bit line parasiticsResistance not dominant (metal)Drain and Gate-Drain capacitance
Model for NOR ROM VDD
Cbit
rword
cword
WL
BL
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Equivalent Transient Model for MOS NAND ROMEquivalent Transient Model for MOS NAND ROM
Word line parasiticsSimilar to NOR ROM
Bit line parasiticsResistance of cascaded transistors dominatesDrain/Source and complete gate capacitance
Model for NAND ROMVDD
CL
rword
cword
cbit
rbit
WL
BL
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PrechargedPrecharged MOS NOR ROMMOS NOR ROM
PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.
WL [0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Precharge devices
BL [2] BL [3]
GND
pref