Digital Integrated Circuits -...

Digital IC Introduction

Digital Integrated

Circuits YuZhuo Fu

contact:[email protected]

Office location：417 room

WeiDianZi building,No 800 DongChuan

road,MinHang Campus


3.CMOS Inverter

Digital IC 3

outline

• CMOS at a glance

• CMOS static behavior

• CMOS dynamic behavior

• Power, Energy, and Energy Delay

• Perspective tech.

Digital IC 4

CMOS dynamic characteristic

• CMOS capacitances mosaic

• CMOS propagation delay

• Optimizing inverter sizing

Digital IC 5

Circuit Under Design

VDD VDD

VinVout

M1

M2

M3

M4

Vout2

This two-inverter circuit will be manufactured in a twin-well process.

Digital IC

CMOS Inverter: Transient Response

6

VDD

Vout

Vin = VDD

Ron

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36

Digital IC 7

CMOS capacitance mosaic

• Wire capacitance

• Junction(diffusion)

capacitance

• Gate capacitance

Most of them are nonlinear functions!

Digital IC 8

Computing the Capacitances

VDDVDD

VinVout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CL

SimplifiedModel

Polysilicon

In Out

Metal1

V DD

GND

PMOS

NMOS

1.2 m m =2l

Digital IC 9

Capacitance model

DS

G

B

CGDCGS

CSB CDBCGBDdiffDB

SdiffSB

GCBGB

GCDGDOGD

GCSGSOGS

CC

CC

CC

CCC

CCC

Digital IC 10

The Miller Effect

V in

M 1

C gd 1

V out

D V

D V

V in

M 1

V out D V

D V

2 C gd 1

“A capacitor experiencing identical but opposite

voltage swings at both its terminals can be

replaced by a capacitor to ground, whose value is

two times the original value.”

Digital IC

Diffusion capacitances

Slide 11

0jeqeq CK=C

])V-Φ(-)V-Φ[(m)-)(1V-(V

Φ-=K m-1

low0

m-1

high0

lowhigh

m

0

eq

Digital IC

Miller effect

12

Digital IC 13


Cox

(fF/um2)

Co

(fF/um)

Cj

(fF/um2)

mj Φb

(V)

Cjsw

(fF/um)

Mjsw

Φbsw

(V)

NMOS 6 0.31 2 0.5 0.9 0.28 0.44 0.9

PMOS 6 0.27 1.9 0.48 0.9 0.22 0.32 0.9

CDG0

CJ CJSW

W/L AD(um2) PD(um) AS(um2) PS(um)

NMOS 3/2 19 15 19 15

PMOS 9/2 45 19 45 19

Digital IC


Slide 14

Polysilicon

In Out

Metal1

V DD

GND

PMOS

NMOS

1.2 m m =2l

AD=4*4+3*1=16+3=19λ2

PD=1+4+4+4+1+1=15λ

Digital IC


• Vhigh=-2.5V,Vlow=-1.25V[NMOS,{2.5V->1.25V} HL]

• Bottom plate:Keqn(m=0.5,Φ0=0.9)=0.57

• Sidewall:Keqwn(m=0.44,Φ0=0.9)=0.61

• Vlow=0V,Vhigh=-1.25V [NMOS,{0V->1.25V}LH]

• Bottom plate:Keqn(m=0.5,Φ0=0.9)=0.79

• Sidewall:Keqwn(m=0.44,Φ0=0.9)=0.81

• Vhigh=-1.25V,Vlow=0V [PMOS,{2.5V->1.25V}HL]

• Bottom plate:Keqp(m=0.48,Φ0=0.9)=0.79

• Sidewall:Keqwp(m=0.32,Φ0=0.9)=0.86

• Vhigh=-2.5V,Vlow=-1.25V [PMOS,{0V->1.25V}LH]

• Bottom plate:Keqp(m=0.48,Φ0=0.9)=0.59

• Sidewall:Keqwp(m=0.32,Φ0=0.9)=0.7

15

Digital IC 16


capacitor expression Value(fF)

(H->L)

Value(fF)

(L->H)

Cgd1 2CGD0n*Wn 0.23 0.23

Cgd2 2CGD0p*Wp 0.61 0.61

Cdb1 KeqnADnCJ+KeqwnPDnCJSW 0.66 0.90

Cdb2 KeqnADnCJ+KeqwnPDnCJSW 1.5 1.15

Cg3 (CGD0n+CGSOn)Wn+CoxWnLn 0.76 0.76

Cg4 (CGD0p+CGSOp)Wp+CoxWpLp 2.28 2.28

Cw 0.12 0.12

CL 6.1 6.0


Computing it more

simple by estimation

Slide 17

Digital IC

Capacitance

• Any two conductors separated by an insulator have

capacitance

• Gate to channel capacitor is very important

• Creates channel charge necessary for operation

• Source and drain have capacitance to body

• Across reverse-biased diodes

• Called diffusion capacitance because it is associated

with source/drain diffusion

Slide 18

Digital IC Slide 19

Gate Capacitance

• Approximate channel as connected to source

• Cgs = eoxWL/tox = CoxWL = CpermicronW

• Cpermicron is typically about 2 fF/mm

n+ n+

p-type body

W

L

tox

SiO2 gate oxide

(good insulator, eox

= 3.9e0)

polysilicon

gate

Digital IC Slide 20

Diffusion Capacitance

• Csb, Cdb

• Undesirable, called parasitic capacitance

• Capacitance depends on area and perimeter

• Use small diffusion nodes

• Comparable to Cg

for contacted diff

• ½ Cg for uncontacted

• Varies with process

Digital IC Slide 21

Effective Resistance

• Shockley models have limited value

• Not accurate enough for modern transistors

• Too complicated for much hand analysis

• Simplification: treat transistor as resistor

• Replace Ids(Vds, Vgs) with effective resistance R

• Ids = Vds/R

• R averaged across switching of digital gate

• Too inaccurate to predict current at any given time

• But good enough to predict RC delay

Digital IC Slide 22

RC Delay Model

• Use equivalent circuits for MOS transistors

• Ideal switch + capacitance and ON resistance

• Unit nMOS has resistance R, capacitance C

• Unit pMOS has resistance 2R, capacitance C

• Capacitance proportional to width

• Resistance inversely proportional to width

kg

s

d

g

s

d

kCkC

kCR/k

kg

s

d

g

s

d

kC

kC

kC

2R/k

Digital IC

Reason of 2R

Slide 23

)2

V-VV(

L

Wk=I

2

DSAT

DSATGT

'

DSAT

Digital IC Slide 24

RC Values

• Capacitance

• C = Cg = Cs = Cd = 2 fF/mm of gate width

• Values similar across many processes

• Resistance

• R 6 KW*mm in 0.6um process

• Improves with shorter channel lengths

• Unit transistors

• May refer to minimum contacted device (4/2 l)

• Or maybe 1 mm wide device

• Doesn’t matter as long as you are consistent

Digital IC Slide 25

Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

2

1A

Y 2

1

Digital IC Slide 26



C

CR

2C

2C

R

2

1A

Y

C

2C

Y2

1

Digital IC Slide 27



C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1

Digital IC Slide 28



C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1

d = 6RC

Digital IC 29





Digital IC

Inverter Transient Response

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vin

t (sec) x 10-10

VDD=2.5V

0.25mm

W/Ln = 1.5

W/Lp = 4.5

Reqn= 13 kW ( 1.5)

Reqp= 31 kW ( 4.5)

tpHL = 36 psec

tpLH = 29 psec

so

tp = 32.5 psec

tf tr tpHL

tpLH

From simulation: tpHL = 39.9 psec and tpLH = 31.7 psec

Digital IC 32

Propagation delay: first order analysis

• Propagation delay model of RC

2→/ 21

OHOLOLOH

VVvVVv

)2

--()(

)9

7-1(

4

3≈

)1(I

dv1

'

2

1 sat12

n

nn

n

DSATTDDDSATnnsat

DD

DSAT

DD

v

v

eq

VVVVk

LWI

VI

V

VvvR

l

l

Assuming transistor as saturation

Digital IC 33

Propagation delay: first order analysis

• Propagation delay model of RC

L

DSATp

DDeqppHL C

I

VCRt )V-1(

4

3*69.0)2ln( DDl

L

DSATn

DDeqnpLH C

I

VCRt )V-1(

4

3*69.0)2ln( DDl

)

)/2-('**

1

)/2-('**

1(*52.0≈

*)11

(**2/75.0*69.0

2*69.0

2

ppppp

pnnnn DSATGTDSATDSATGTDSAT

n

nDDL

L

dsatpdsatn

DD

L

eqpeqnpLHpHL

p

VVVkL

WVVVk

LW

VC

CII

V

CRRtt

t

Digital IC

Inverter Propagation Delay,

Revisited

To see how a designer can optimize the delay of a

gate have to expand the Req in the delay equation

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

VDD (V)

tpHL = 0.69 Reqn CL

= 0.69 (3/4 (CL VDD)/IDSATn )

0.52 CL / (W/Ln k’n VDSATn )

Digital IC 35

Design techniques for minimized

propagation delay

• Reduce CL

• Keep the drain diffusion

areas as small as possible

• Increase the W/L ratio of

the transistor

• Increase Vdd

)1()(

*52.0≈

'

DDDSATnn

LpHL

VVkL

W

Ct

nl

Digital IC

Design for Performance

• Reduce CL

• internal diffusion capacitance of the gate itself

• keep the drain diffusion as small as possible

• interconnect capacitance

• fanout

• Increase W/L ratio of the transistor

• the most powerful and effective performance optimization tool in the

hands of the designer

• watch out for self-loading! – when the intrinsic capacitance dominates

the extrinsic load

• Increase VDD

• can trade-off energy for performance

• increasing VDD above a certain level yields only very minimal

improvements

Digital IC 37

Define NMOS-to-PMOS ratio

In order to create an inverter with

a symmetrical propagate delays

Also create symmetrical VTC β =2.4 which Rn=Rp!

nDSATnn

L

neqLpHLVk

LW

CRCt

')(2)2ln(

p

p

DSATpp

LeqLpLH

VkL

W

CRCt

')(2)2ln(

)2

(

)2

(

)(

)(

'

'

p

p

n

n

DSAT

TpMDDDSATp

DSAT

TnMDSATn

n

p

VVVVVk

VVVVk

LW

LW

1)(

)(

'

'

p

n

n

p

DSATpp

DSATnn

eq

eq

VkL

W

VkL

W

R

R

Digital IC 38

1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 10

-11

b

t p(s

ec)

tpLH tpHL

tp

b = Wp/Wn

Which point is optimal delay?

p

p

DSATpp

LeqLpLH

VkL

W

CRCt

')(2)2ln(

nDSATnn

L

neqLpHLVk

LW

CRCt

')(2)2ln(

Digital IC 39


V DD V DD

V in V out

M 1

M 2

M 3

M 4 C db 2

C db 1

C gd 12

C w

C g 4

C g 3

V out 2

Interconnect

n

p

wgdwggddL

LW

LW

CCCCCCCCCnnpnpn

)(

)(

))(1(212211

b

b

)1()))(1((345.0

))())(1((2

2ln

2

21

21

b

b

bb

nnn

p

nnn

eqwgd

eq

eqwgd

pHLpLH

p

RCCC

RRCCC

ttt

Digital IC 40


This r is different from before! It is the

resistor rate of the NMOS and PMOS

0

b

pt

0

)]1()))(1((345.0[21

b

b

b

nnn eqwgd RCCC

54.113

31≈)1(

25.05.2

21

um

VVdd

gndn

w

CC

Cb

Digital IC 41

Summary of ratio

Beta=1.6, we have minimum delay

Beta=2.4, we have equal delay tphl=tplh

Beta=3.5, we have VM=Vdd/2

Digital IC 42





Digital IC

iref

extpp

irefextirefref

intextinteqextinteqp

SC

Ctt

SCCSCSR

CCCRCCRt

00 69.069.0

)1)()((69.0

)1(69.0)(69.0

43

Increasing inverter performance by sizing the

NMOS and PMOS

Intrinsic delay is independent

of the sizing of the gate

S>>0 will eliminate the

impact of any external load If no load

If load

Digital IC 44

2 4 6 8 10 12 142

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 10

-11

S

t p(s

ec)

Device Sizing

(for fixed load)

Self-loading effect:

Intrinsic capacitances

dominate

Example 5.5

Digital IC 45

Inverter Chain

CL

If CL is given: - How many stages are needed to minimize the delay?

- How to size the inverters?

In Out

Digital IC 46

Inverter Delay

Minimum length devices, L=0.25mm, Assume

that for WP = 2WN =2W same pull-up and pull-down currents

approx. equal resistances RN = RP

approx. equal rise tpLH and fall tpHL delays

Analyze as an RC network

WNunit

Nunit

unit

PunitP RR

W

WR

W

WRR

11

tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL Delay (D):

2W

W

unit

unit

gin CW

WC 3Load for the next stage:

Digital IC 47

Inverter with Load

Load (CL)

Delay

Assumptions: no load -> zero delay

CL

tp = k RWCL

RW

RW

Wunit = 1

k is a constant, equal to 0.69

Digital IC 48

Inverter with Load

Load

Delay

Cint CL

Delay = kRW(Cint + CL) = kRWCint + kRWCL = Delay

(Internal) + Delay (Load)= kRW Cint(1+ CL /Cint)

CN = Cunit

CP = 2Cunit

2W

W

Digital IC 49

Delay Formula

/1/1

~

0int ftCCCkRt

CCRDelay

pintLWp

LintW

Cint = Cgin with 1

f = CL/Cgin - effective fanout

R = Runit/W ; Cint =WCunit

tp0 = 0.69RunitCunit

Digital IC 50

Apply to Inverter Chain

CL

In Out

1 2 N

tp = tp1 + tp2 + …+ tpN

jgin

jgin

unitunitpjC

CCRt

,

1,1~

LNgin

N

i jgin

jgin

p

N

j

jpp CC C

Cttt

1,

1 ,

1,

0

1

, ,1

Digital IC

Optimal Tapering for Given N

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives Result:

Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two

neighbors

each stage has the same effective fanout (Cout/Cin)

each stage has the same delay

51

1,1,, jginjginjgin CCC

Digital IC 52

Optimum size for fixed Number

of Stages

When each stage is sized by f and has same eff. fanout f:

Minimum path delay

Effective fanout of each stage:

1,/ ginL

N CCFf

N Ff

/10N

pp FNtt

Digital IC 53

Example

CL= 8 C1

In Out

C1 1 f f2

283 f

CL/C1 has to be evenly distributed across N = 3 stages:

CL/C1 has to be evenly distributed across N = 4 stages:

?84 f

Digital IC 54

Optimum Number of Stages

For a given load, CL and given input

capacitance Cin Find optimal sizing f

ftf

FFNtt p

N

pp 0

/1

0ln

ln1/

0ln

1lnln2

0

f

ffFt

f

t pp

For = 0, f = e, N = lnF

f

FNCfCFC in

N

inLln

ln with

fef 1

Digital IC 55

Optimum Effective Fanout f

Optimum f for given process defined by

fef 1

fopt = 3.6[4] for =1

Digital IC 56

Impact of Self-Loading on tp

1.0 3.0 5.0 7.0u

0.0

20.0

40.0

60.0

u/l

n(u

)

x=10

x=100

x=1000

x=10,000

No Self-Loading, =0 With Self-Loading =1

0

1

2

3

4

5

6

7

1 1.5 2 2.5 3 3.5 4 4.5 5

Digital IC 57

Normalized delay function of F

( ) Fln6.3=)6.3+1(Fln78.0=γ/F+1Nt=t N0pp

F unbuffered Two stages Inverter chain

10 11 8.3 8.3

100 101 22 16.6

1000 1001 65 24.9

10000 10001 202 33

Fln78.0=6.3ln

Fln=

fln

Fln=N,F=f N

Digital IC 58

Buffer Design

1

1

1

1

8

64

64

64

64

4

2.8 8

16

22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3

Digital IC

More general example

Slide 59

1 2 3 CLoutin

( )γ/f+1Nt=t 0pp

3

3

3

L

2

3

1

2

3

L

2

3

1

2

1

L

3

L

2

3

1

2

164=f

f16

1=

C

C

C

C4

C

C4

16

1=

C

C

C

C

C

C=

C

C=F

f=C

C=

C

C4=

C

C4

13

13

33

2

13

13

L

3

C16=C164

44*4=

f

C4=C

C44=C164

64=

f

C=C

Digital IC

Design Challenge

• A gate is never designed in isolation: its performance

is affected by both the fan-out and the driving strength

of the gate(s) feeding its inputs.

( 0.25)

• Keep signal rise times smaller than or equal to the gate

propagation delays

• good for performance

• good for power consumption

• Keeping rise and fall times of the signals small and of

approx. equal values is one of the major challenges in

high-performance designs(slope engineering.)

1-iii

stepstepptη+t=t

Digital IC

Input Signal Rise/Fall Time

• In reality, the input signal

changes gradually (and both

PMOS and NMOS conduct

for a brief time). This affects

the current available for

charging/discharging CL and

impacts propagation delay.

3.6

3.8

4

4.2

4.4

4.6

4.8

5

5.2

5.4

0 2 4 6 8ts(sec)

x 10-11

x 10-11

for a minimum-size inverter with a fan-

out of a single gate

tp increases linearly with increasing input slope, ts, once ts > tp

ts is due to the limited driving capability of the preceding gate

Digital IC

Rising-fall time of the input signal

Slide 62

1-iii

stepstepptη+t=t

Note: tp increases linearly with increasing input

slope,once ts>tp(ts=0)

1 2 3 CLoutin

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