Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic...
Transcript of Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic...
![Page 1: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/1.jpg)
Sequential Logic
References:
Adapted from: Digital Integrated Circuits: A Design
Perspective, J. Rabaey, Prentice Hall © UCB
Principles of CMOS VLSI Design: A Systems Perspective,
N. H. E. Weste, K. Eshraghian, Addison Wesley
![Page 2: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/2.jpg)
Clocked Systems: Finite State Machines
Combinational
Logic
Inputs Outputs
DQ
Clock or clocks
Current state bits Next state bits
Registers
Out = f(In, State)
Registers serve as storage element to store past history
![Page 3: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/3.jpg)
Clocked Systems: Pipelined Systems
Logic
Inputs OutputsQD
Clock
QD QDLogic
Registers
Registers serve as storage element to capture the output
of each processing stage
![Page 4: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/4.jpg)
Storage Mechanisms
• Positive feedback
– Connect one or more output signals back to the input
– Regenerative, signal can be held indefinitely, static
• Charge-based
– Use charge storage to store signal value
– Need refreshing to overcome charge leakage, dynamic
![Page 5: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/5.jpg)
Positive Feedback: Two Cascaded Inverters
Vi1 Vo1= Vi2 Vo2
Vi2= Vo1
![Page 6: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/6.jpg)
Bi-Stability and Meta-Stability
Vi1=Vo2
Vi2=
Vo
1
A
B
C
Vi1=Vo2
Vi2=
Vo
1
A
B
C
Gain larger than 1 amplifies
the deviation from C
Gain less than 1 reduces
the deviation from A
![Page 7: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/7.jpg)
SR-Flip Flop
• NOR-based SR flip-flop, positive logic
• NAND-based SR flip-flop, negative logic
Schematic Logic Symbol Characteristic table
Schematic Logic Symbol Characteristic table
Forbidden state
![Page 8: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/8.jpg)
JK- Flip Flop
Schematic Logic Symbol Characteristic table
• Clock input to synchronize changes in the output
logic states of flip-flops
• Forbidden state is eliminated,
• But repeated toggling when J = K = 1, need to keep
clock pulse small < propagation delay of FF
![Page 9: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/9.jpg)
Other Flip-Flops
Toggle or T flip-flop Delay or D flip-flop
![Page 10: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/10.jpg)
Race Problem
• A flip-flop is a latch if the gate is transparent while the
clock is high (low)
• Signal can raise around when is high
• Solutions:
– Reduce the pulse width of
– Master-slave and edge-triggered FFs
![Page 11: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/11.jpg)
Master-Slave Flip-Flop
• Either master or slave FF is in the hold mode
• Pulse lengths of clock must be longer than
propagation delay of latches
• Asynchronous or synchronous inputs to initialize the
flip-flop states
![Page 12: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/12.jpg)
One-Catching or Level-Sensitive
QM
QS
![Page 13: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/13.jpg)
Propagation Delay Based Edge-Triggered
• Depend only on the value of
In just before the clock
transition
![Page 14: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/14.jpg)
Edge Triggered Flip-Flop
![Page 15: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/15.jpg)
Flip-Flop: Timing Definitions
![Page 16: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/16.jpg)
Maximum Clock Frequency
Tttt setupcombppFF ,
![Page 17: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/17.jpg)
Timing Metrics in Sequential Circuits
Register
D Q
CLK
Register
D Qcomb.
logic
Setup Time (tsu) is the time that the data inputs must be valid before the
clock transition
Hold Time (thold) is the time that the data inputs must be valid after the
clock transition
Propagation delays (treg,max, treg,min) – D input is copied to Q
tlogic,max, tlogic,min
tsu , thold,
treg,max, treg,min
![Page 18: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/18.jpg)
Setup Time, Hold Time, and Propagation Delay
Data
Stable
T
tsutreg,maxtreg,max tlogic,max
thold
Data
StableData
Stable
,max log ,maxreg ic setupt t t T
log ,min ,minic reg holdt t t
t
t
t
D
CLK
Q
Register
D Q
CLK
![Page 19: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/19.jpg)
Multiplexer Based Latches
A latch is a level-sensitive device
D
Q
CLK
0
1
D
Q
CLK
CLK
___
CLK
![Page 20: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/20.jpg)
NMOS-only MUX based Latch
CLK
___
CLK
D QM
__
QM
Load of only 2 transistors to clock signals
Passes a degraded high voltage of VDD – VTn
![Page 21: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/21.jpg)
Master Slave Edge-Triggered Register
D
QM
CLK
1
0
Q
CLK
0
1
Master
Slave
A register is an edge-triggered storage element
A Flip-Flop is any bistable component formed by the cross-coupling
of gates
![Page 22: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/22.jpg)
Master Slave Edge-Triggered Register
D
QM
CLK
___
CLK
Q
CLK
CLK
___
CLK
___
CLK
T2
T1
T4
T3
I2
I1
I3
I4
I5I6
Setup Time: 3*tinv + ttx (I1T1 I3I2)
Propagation Delay: ttx + tinv (T3 I6)
Hold Time: 0
![Page 23: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/23.jpg)
CMOS Clocked SR Flip-Flop
M1
M2
M3
M4
M5
M6
M7
M8
S R
VDD
S
R
Q
Q
![Page 24: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/24.jpg)
Transistor Sizing of SR Flip-Flop
• Assume transistors of inverters are sized so that VM
is VDD/2, mobility ratio n/ p = 3
– (W/L)M1 = (W/L)M3 = 1.8/1.2
– (W/L)M2 = (W/L)M4 = 5.4/1.2
• To bring Q from 1 to 0, need to properly ratio the
sizes of pseudo-NMOS inverter (M7-M8)-M4
– VOL must be lower than VDD/2
82||
82
2
4,
2
78,DDDD
tpDDMpDDDD
tnDDMn
VVVVk
VVVVk
3478 )/()/()/( MM
n
p
M LWLWLW
)2.1/6.3()/(2)/(2)/( 3787 MMM LWLWLW
![Page 25: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/25.jpg)
Flip-Flop: Transistor Sizing
![Page 26: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/26.jpg)
Propagation Delay
Pseudo-
NMOS
inverter
(M5-M6)-M2
Inverter
M3-M4
![Page 27: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/27.jpg)
Complementary CMOS SR Flip-Flop
M1
M2
M3
M4
M5
M6
M7
M8
S R
VDD
S R
M9
M10
M11
M12
Eliminates pseudo-NMOS inverters
Faster switching and smaller transient current
![Page 28: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/28.jpg)
6-Transistor SR Flip-Flop
M1
M2
M3
M4
R
VDD
S
![Page 29: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/29.jpg)
CMOS D Flip-Flop
DQ
Q
D
VDD
D
![Page 30: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/30.jpg)
Master-Slave D Flip-Flop
D
VDD
D
![Page 31: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/31.jpg)
Negative-Level Sensitive D Flip-Flop
DQ
Q
D
VDD
D
![Page 32: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/32.jpg)
Master-Slave D Flip-Flop
D
VDD
D
![Page 33: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/33.jpg)
CVSL-Style Master-Slave D-FF
Q Q
VDD
D
VDD
![Page 34: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/34.jpg)
Charge-Based Storage
Pseudo-static Latch
In D
D
![Page 35: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/35.jpg)
Layout of a D Flip-Flop
In
Q
In Q
Q
Q
![Page 36: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/36.jpg)
Master-Slave Flip-Flop
InA
B
• Overlapping clocks can cause
– race conditions
– undefined signals
D
![Page 37: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/37.jpg)
2 Phase Non-Overlapping Clocks
1
2
In
1
2
A
D
1
2
12pt
![Page 38: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/38.jpg)
Asynchronous Setting
1
2
In
1
2
A
D
-Set
![Page 39: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/39.jpg)
Dynamic Edge-Triggered Register
DN1
Q
(0, 0) overlap
(1,1) overlap
___
CLK
___
CLK
CLK
CLK
N2
C2C1
T1 T2I1 I2
___
CLK
CLK
(0,0) 1 1 2overlap T I Tt t t t
(1,1)hold overlapt t
![Page 40: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/40.jpg)
2-phase Dynamic Flip-Flop
1
2
InA
2
D
1
Input
sampled
Output
Enabled
![Page 41: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/41.jpg)
Flip-flop Insensitive to Clock Overlap
VDD VDD
In
CL1CL2
-section -section
C2MOS Latch or Clocked CMOS Latch
M1
M2
M3
M4
M5
M6
M7
M8X D
![Page 42: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/42.jpg)
C2MOS Latch Avoids Race Conditions
VDD VDD
In
CL1CL2
M1
M2
M3
M5
M6
M7
X D
• Cascaded inverters: needs one pull-up followed by
one pull-down, or vice versa to propagate signal
• (1-1) overlap: Only the pull-down networks are active,
input signal cannot propagate to the output
• (0-0) overlap: only the pull-up networks are active
1 1
![Page 43: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/43.jpg)
C2MOS Latch Avoids Race Conditions
• C2MOS latch is insensitive to overlap, as long a the
rise and fall times of clock edges are sufficiently small
![Page 44: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/44.jpg)
Clocked CMOS Logic
• Replace the inverter in a C2MOS latch with a
complementary CMOS logic
VDD
CL1
PDN
PUN
M3
M4X
VDD
CL2
PDN
PUN
M7
M8
In1-3
In1-3
• Divide the computation into stages: Pipelining
![Page 45: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/45.jpg)
Pipelining
RE
GR
EG
a
b
log
RE
G
RE
GR
EG
a
b
log
RE
G
regsetuplogicpregp tttT ,,,min
RE
G
RE
G
regsetuppabspadderpregppipe tttttT ,log,,,,min, ),,max(
Non-pipelined Pipelined
![Page 46: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/46.jpg)
Pipelined Logic using C2MOS
In F G
NORA CMOS (NO-RAce logic)
Race free as long as all the logic functions F and G
between the latches are non-inverting
C1 C2 C3
out
VDDVDDVDD
![Page 47: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/47.jpg)
Example
VDD VDD
In
VDD
Number of static inversion should be even
![Page 48: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/48.jpg)
NORA CMOS -module
Logic
Precharge
Evaluate
Latch
Hold
Evaluate
= 0
= 1
![Page 49: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/49.jpg)
NORA CMOS -module
Logic
Evaluate
Precharge
Latch
Evaluate
Hold
= 0
= 1
![Page 50: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/50.jpg)
NORA Logic
• NORA data path consists of a chain of alternating
and modules
• Dynamic-logic rule: single 0 1 (1 0) transition for
dynamic n-block ( p-block)
• C2MOS rule:
– If dynamic blocks are present, even number of static
inversions between a latch and a dynamic block
– Otherwise, even number of static inversions between latches
• Static logic may glitch, best to keep all of them after
dynamic blocks
![Page 51: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/51.jpg)
Doubled C2MOS Latches
Doubled n-C2MOS latch Doubled p-C2MOS latch
![Page 52: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/52.jpg)
TSPC - True Single Phase Clock Logic
Including logic into
the latch
Inserting logic between
the latches
![Page 53: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/53.jpg)
Simplified TSPC Latches
A and A’ do not have full logic swing
![Page 54: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/54.jpg)
Master-Slave Flip-flops
Positive-edge triggered D-FF Negative-edge triggered D-FF
![Page 55: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/55.jpg)
Master-Slave Simplified TSPC Flip-Flops
• Positive edge-triggered D flip-flops
• Reduces clock load
![Page 56: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/56.jpg)
Further Simplication
![Page 57: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/57.jpg)
Schmitt Trigger
• VTC with hysteresis
• Restores signal slopes
![Page 58: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/58.jpg)
Noise Suppression using
Schmitt Trigger
Sharp low-to-high transition
![Page 59: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/59.jpg)
CMOS Schmitt Trigger
Moves switching threshold
of first inverter
![Page 60: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/60.jpg)
Sizing of M3 and M4
• VM+ = 3.5V
– M1 and M2 are in saturation; M4 is in triode region
• VM- = 1.5V
– M1 and M2 are in saturation; M3 is in triode region
2||||
2
22
4
22
21
MDDMDDtpDDtpMDD
tnM
VVVVVVkVVV
k
VVk
![Page 61: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/61.jpg)
Schmitt Trigger: Simulated VTC
![Page 62: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/62.jpg)
CMOS Schmitt Trigger
• In = 0, at steady state, VOut = VDD, VX =
VDD - Vtn
• In makes a 0 1 transition
– Saturated load inverter M1-M5 discharges
X
– M2 inactive until VX = Vin - Vtn
– Use Vin to approximate VM-
– M1-M5 in saturation
2521
22MDDtnM VV
kVV
k
![Page 63: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/63.jpg)
Multivibrator Circuits
Bistable Multivibrator
Monostable Multivibrator
Astable Multivibrator
flip-flop, Schmitt Trigger
one-shot
oscillator
S
R
T
![Page 64: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/64.jpg)
Transition-Triggered Monostable
DELAY
td
In
Outtd
Detects changes in the input signal
produces a pulse to initialize subsequent circuitry
e.g., address transition detection in static memories
![Page 65: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/65.jpg)
Monostable Trigger (RC-based)
![Page 66: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/66.jpg)
Astable Multivibrators (Oscillators)
T = 2 tp N
![Page 67: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/67.jpg)
Voltage Controller Oscillator (VCO)
Schmitt trigger
restores signal slopes
Current starved inverter
Decrease Vcontr to reduce discharge current
increase propagation delay of inverter
decreases oscillating frequency
(quadratic dependency)
![Page 68: Digital Gates Fundamental Parameters - Purdue …vlsi/ECE559_Fall09/Notes...JK- Flip Flop Schematic Logic Symbol Characteristic table • Clock input to synchronize changes in the](https://reader034.fdocuments.us/reader034/viewer/2022042109/5e89763388cf6b515702ab80/html5/thumbnails/68.jpg)
Relaxation Oscillator
T = 2 (ln 3) RC