Latche Flop Seqpla

8/8/2019 Latche Flop Seqpla

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These slides incorporate figures from Digital Design

Principles and Practices, third edition, by John F.

Wakerly, Copyright 2000, and are used by permission.

NO permission is given to re-use or publish thesefigures, in either original or modified form, in printed,

electronic or any other format.


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Latches

Flip-flopsSequential PLAs


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Sequential Circuits

Output depends on current input andpasthistory of inputs.

State embodies all the information about the

past needed to predict current output based

on current input. State variables, one or more information bits.


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Describing Sequential Circuits

State table

For each current-state, specify next-states asfunction of inputs

For each current-state, specify outputs as functionof inputs

Like a separate combinational problem for eachstate

State diagram

Graphical version of state table

0q 1q

1/1

0/0

0/0

1/1


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Clock signals

Very important with most sequential circuits

State variables change state at clock edge.


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HIGH LOW

LOWHIGH

LOW HIGH

HIGH LOW

Bistable element


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Analog analysis

Assume pure CMOS thresholds, 5V rail

Theoretical threshold center is 2.5 V


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Analog analysis

Assume pure CMOS thresholds, 5V rail

Theoretical threshold center is 2.5 V

2.5 V 2.5 V

2.5 V 2.5 V

2.51 V 2.0 V

2.0 V 4.8 V

4.8 V 0.0 V

0.0 V 5.0 V

5.0 V


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Metastability

Metastability is inherent in any bistable circuit

Two stable points, one metastable point


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Another look at metastability


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Why all the harping on metastability?

All real systems are subject to it

Problems are caused by asynchronous inputs

that do not meet flip-flop setup and hold times.

Especially severe in high-speed systems

since clock periods are so short, metastabilityresolution time can be longer than one clock

period.

Many digital designers, products, and

companies have been burned by thisphenomenon.


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Back to the bistable element cross-coupled inverter maintains a zero or one,

but has no provision for forcing a change

enter the set-reset (S-R) latch cross-coupled NOR gates

(control = 0) ==> inverter(control = 1) ==> zero out


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S-R latch operation

Metastability is possibleif S and R are negated

simultaneously.


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S-R latch timing parameters

Propagation delay

Minimum pulse width


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S-R latch symbols


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S-R latch using NAND gates

Differs from NOR implementation:controls are active-lowset control drives Q gate

also called latchS R

(control = 1) ==> inverter(control = 0) ==> one output


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S-R latch with enable


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D latch


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D-latch operation

latch acts like a wire while its control is activeflip-flop (later) grabs data when control changes


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D-latch timing parameters

Propagation delay (from C or D)

Setup time (D before C edge)

Hold time (D after C edge)


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Construct edge-triggered D flip-flop two D latches in series

driven by opposite clock phases first stage is the master second stage is the slave master-slave D flip-flop

note edge-triggerclock symbol


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Edge-triggered D flip-flop behavior


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D flip-flop timing parameters

Propagation delay (from CLK) Setup time (D before CLK)

Hold time (D after CLK)


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Edge-triggered D flip-flop withasynchronous preset and clear

slavemaster

release during low clock ==> slave reverts to cross coupled inverters master tracks D


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assert preset forces one

1

11

010

circuit exhibits pattern above, regardless of data and clock,

assuming clear remains unasserted

tracks D' when clock is lowone when clock is high, but no further effect

tracks clock', but no further effect

release during low clock ==> slave reverts to cross-coupled inverters, master tracks D release during high clock ==> master reverts to cross-coupled inverters, slave tracks master (stable 1) release during low-to-high at slave ==> slave captures master, which is already cross-coupled inverters release during low-to-high at master ==> master captures D, but slave isolates with stable one


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TTL edge-triggered D circuit

Preset and

clear inputs like S-R latch

3 feedback

loops interesting

analysis


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0

0

1

1

stable

tracking D

tracking D

1

1

D

D

setsQ = D

tracks D (captured D = 1)

orreverts to 1 (captured D = 0)

in either casecaptured D is stable

reverts to 1 (captured D = 1)0 (captured D = 0)

so, captured D also stable


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Variant: edge-triggered D flip-flop

--- multiplexes input D or output Q to flip-flop


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CMOS edge-triggered D circuit

Two feedback loops (master and slave latches)

Uses transmission gates in feedback loops


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Other D flip-flop variations

Negative-edge triggered

Clock enable

Scan


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Scan flip-flops -- for testing

TE = 0 ==> normal operation

TE = 1 ==> test operation

All of the flip-flops are hooked together in a daisychain from external test input TI.

Load up (scan in) a test pattern, do one normal

operation, shift out (scan out) result on TO.


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J-K flip-flops


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SR master-slave

note pulse catchingS has positive glitch (of sufficient duration) during high clock ==>

master sets ==> slave sets on falling clock transition


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SR master-slave timing


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JK master-slave

note pulse catching still a problemif Q is zero, positive glitch on J during high clock sets masterslave follows after clock goes low

JK l i i


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JK master-slave timing

Edge triggered JK flip flop


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Edge-triggered JK flip-flopremoves pulse catching


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Commercial edge-triggered JK flip-flop

similar to edge-triggered D flip-flop

Analysis: as before


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Analysis: as before--- NAND requires all ones on inputs to achieve zero out

--- NOR requires all zeros on inputs to achieve one out

0

0

1

1

two input onesacts like inverter for remaining input

two input onesacts like inverter for remaining input

stable output

1

1

JQ

KQ

JK + JQ + KQ

tracking: 1 if set (J = 1, K = 0)0 if reset (J = 0, K = 1)Q if toggle (J = 1, K = 1)

Q if hold (J = 0, K = 0)

tracking: 0 if set (J = 1, K = 0)

1 if reset (J = 0, K = 1)Q if toggle (J = 1, K = 1)Q if hold J = 0, K = 0

transitions to zero for:set, toggle a zero, hold a one(i.e., set Q)

transitions to zero for:

reset, toggle a one, hold a zero(i.e., reset Q)


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0

0

0

1

stable output

1

1

JQ

KQ

JK + JQ + KQ

stable zero now forces stable onehere while clock is high, regardlessof inputs J, K

Suppose this signal transitions to zero

transitions to oneno longer trackingJ, K inputs

1

forces stable zerowhile clock is high,

independent of inputchanges to J, K


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T flip-flops

Important for counters

S i l


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Sequential

PALs

16R8


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One output of 16R8

8 product terms to D input of flip-flop

positive edge triggered, common clock for all

Q output is fed back into AND array

needed for state machines and other applications Common 3-state enable for all output pins


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PAL16R6

Six registered

outputs

Twocombinational

outputs (likethe 16L8s)


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GAL16V8

Finally got it right

Each output isprogrammable ascombinational orregistered

(diagram showsonlyregistered outputs)

Also has

programmableoutput polarity


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GAL16V8 output logic macrocell


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GAL22V10

More inputs

More product terms

More flexibility


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GAL22V10 output logic macrocell


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Sequential PLD timing parameters

First PLD feeding a secondwith same clockoutput from first must arrive atsecond at least setup time before clock edge==> stable output time plus setup time must

not exceed a clock period

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