Digital Fudamental
Transcript of Digital Fudamental
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© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed
Digital Fundamentals
with PLD Programming
Floyd
Chapter 9
© 2009 Pearson Education
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed
A latch is a temporary storage device that has two stable
states (bistable). It is a basic form of memory.
SummarySummarySummary
Latches (biestables)
The S-R (Set-Reset) latch is the most basic type. It can be constructedfrom NOR gates or NAND gates. With NOR gates, the latch
responds to active-HIGH inputs; with NAND gates, it responds to
active-LOW inputs.
S
R
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The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
SummarySummarySummary
Funcionamiento S-R
R
S
Q
Q
Assume the latch is initially RESET
(Q = 0) and the inputs are at their
inactive level (0). To SET the latch
(Q = 1), a momentary HIGH signal
is applied to the S input while the R
remains LOW.
0 1
0
R
S
Q
Q
1
0
0
To RESET the latch (Q = 0), a
momentary HIGH signal isapplied to the R input while the S
remains LOW.
0
0
1
01
0
Latch
initially
RESET
Latchinitially
SET
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed
S
R
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
SummarySummarySummary
Funcionamiento S’-R’
Q
Q
11
01
0
1
Latch
initially
RESET
Q
Q
1
1
01
0
1
Latch
initially
SET
S
R
Assume the latch is initially RESET(Q = 0) and the inputs are at their
inactive level (1). To SET the latch
(Q = 1), a momentary LOW signal
is applied to the S input while the R
remains HIGH.
To RESET the latch a
momentary LOW is applied to the
R input while S is HIGH.
Never apply an active set and
reset at the same time (invalid).
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Símbolos lógicos
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Funcionamiento de un S’-R’
Tabla de verdad del S’-R’
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Otra forma de expresar la tabla de verdad del S’-R’
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Tabla de verdad del S-R
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Latch S-R con puerta (entrada de habilitación)
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Tabla de verdad
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Latch D
Memoriza el bit en la entrada D: Q será igual a D cuando
la entrada EN está activa.
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Otra forma de expresar la tabla de verdad
Funcionamiento en el tiempo
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SummarySummarySummary
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked (sincronizado) device,
in which only the clock edge determines when a new
bit is entered.
The active edge can be positive or negative.
D Q
C
Q
(a) Positive edge-triggered
D Q
C
Q
(b) Negative edge-triggered
Dynamicinput
indicator
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Flip flops sincronizados por
flanco de subida y de bajada
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Funcionamiento de un flip-flop S-R sincronizado por
flanco de subida
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Un flip-flop D sincronizado por flanco de subida
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed
SummarySummarySummary
Flip-flops
The J-K flip-flop is more versatile than the D flip flop. In
addition to the clock input, it has two inputs, labeled J and
K . When both J and K = 1, the output changes states(toggles) on the active clock edge (in this case, the rising
edge).Inputs
Comments
1
1 1
1
CLKKJ
Outputs
1
QQ
Q0
Q0
Q0
Q0
0 SET
Toggle
0
0
0
0 0 1 RESET
No change
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Funcionamiento
CLK
Q
K
J
CLK
K
J
Q
Q
Notice that the outputs change on the leading edge of the clock.
Set Toggle Set Latch
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Funcionamiento del flip-flop J-K sincronizado por
flanco de bajada
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SummarySummarySummary
Entradas asíncronas
Synchronous inputs are transferred in the triggering edge
of the clock (for example the D or J-K inputs). Most flip-flops have other inputs that are asynchronous, meaning
they affect the output independent of the clock.
Two such inputs are normally labeled
preset (PRE ) and clear (CLR). These
inputs are usually active LOW. A J-K
flip flop with active LOW preset and
CLR is shown.
CLK
K
J
Q
Q
PRE
CLR
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed
Funcionamiento
CLK
K
J
Q
Q
PRE
CLR
Set Toggle Reset Toggle
Set
Set
Reset
Latch
CLK
K
J
Q
PRE
CLR
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Resumen de los f lips-flops
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The propagation delay time is the time required for an
input to cause a change in the output. It is measured from the50% levels.
SummarySummarySummary
Flip-flop Characteristics
Figure 8--35 Propagation delays, clock to output.
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Figure 8--36 Propagation delays, preset input to output and clear input to output.
Retrasos de propagación de las entradas asíncronas
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Set-up time and hold time are times required before and
after the clock transition that data must be present to bereliably clocked into the flip-flop.
SummarySummarySummary
Flip-flop Characteristics
Setup time is the minimum
time for the data to be present
before the clock.
Hold time is the minimum timefor the data to remain after the
clock.
CLK
D
CLK
D
Set-up time, t s
Hold time, t H
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Figure 8--37 Set-up time (t s). The logic level must be present on the D input for a time
equal to or greater than t s before the triggering edge of the clock pulse for reliable data entry.
Set-up time
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Figure 8--38 Hold time (t h). The logic level must remain on the D input for a time equal toor greater than t h after the triggering edge of the clock pulse for reliable data entry.
Hold time
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© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed
SummarySummarySummary
Flip-flop Applications
Principal flip-flop applications are for
temporary data storage, as frequencydividers, and in counters (which are
covered in detail in Chapter 10).
Typically, for data storage applications,
a group of flip-flops are connected to
parallel data lines and clocked together.
Data is stored until the next clock pulse.
D
C
R
D
C
R
D
C
R
D
C
R
Parallel data
input lines
Clock
Clear
Output
lines
Q0
Q1
Q2
Q3
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Figure 8--39 Example of flip-flops
used in a basic register for parallel
data storage.
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SummarySummarySummary
Flip-flop Applications
For frequency division, it is simple to use a flip-flop in
the toggle mode or to chain a series of toggle flip flops to
continue to divide by two.
One flip-flop will divide f in by 2, two flip-flops will
divide f in by 4 (and so on). A side benefit of frequency
division is that the output has an exact 50% duty cycle.
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Figure 8--40 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of
CLK.
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Figure 8--41 Example of two J-K flip-flops used to divide the clock frequency by 4. QA is
one-half and QB is one-fourth the frequency of CLK.
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Aplicación: generar una cuenta
Figure 8--44 Flip-flops used to generate a binary count sequence. Two repetitions (00, 01,
10, 11) are shown.
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Ejemplo: determinar la cuenta generada
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Selected Key TermsSelected Key TermsSelected Key Terms
Latch
Bistable
Clock
D flip-flop
J-K flip-flop
A bistable digital circuit used for storing a bit.
Having two stable states. Latches and flip-flops are bistable multivibrators.
A triggering input of a flip-flop.
A type of bistable multivibrator in which the output
assumes the state of the D input on the triggering
edge of a clock pulse.
A type of flip-flop that can operate in the SET,
RESET, no-change, and toggle modes.
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Selected Key TermsSelected Key TermsSelected Key Terms
Propagation
delay time
Set-up time
Hold time
Timer
Registered
The interval of time required after an input signal
has been applied for the resulting output signal to
change.
The time interval required for the input levels to be
on a digital circuit.
The time interval required for the input levels to
remain steady to a flip-flop after the triggering
edge in order to reliably activate the device.
A circuit that can be used as a one-shot or as an
oscillator.A CPLD macrocell output configuration where the
output comes from a flip-flop.
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1. The output of a D latch will not change ifa. the output is LOW
b. Enable is not active
c. D is LOW
d. all of the above
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2. The D flip-flop shown will
a. set on the next clock pulse
b. reset on the next clock pulse
c. latch on the next clock pulse
d. toggle on the next clock pulse
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CLK
D
CLK
Q
Q
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3. For the J-K flip-flop shown, the number of inputs thatare asynchronous is
a. 1
b. 2
c. 3
d. 4
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CLK
K
J
Q
Q
PRE
CLR
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4. Assume the output is initially HIGH on a leading edge
triggered J-K flip flop. For the inputs shown, the output
will go from HIGH to LOW on which clock pulse?
a. 1
b. 2
c. 3
d. 4
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CLK
K
J
1 2 3 4
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5. The time interval illustrated is called
a. t PHL
b. t PLH
c. set-up time
d. hold time
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50% point on triggering edge
50% point on LOW-to-
HIGH transition of Q
CLK
Q
?
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CLK
D
?
6. The time interval illustrated is called
a. t PHL
b. t PLH
c. set-up time
d. hold time
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7. The application illustrated is a
a. astable multivibrator
b. data storage device
c. frequency multiplier
d. frequency divider
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HIGH HIGH
CLK
K
J QA
CLK
K
J
f in
QB f out
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8. The application illustrated is a
a. astable multivibrator
b. data storage device
c. frequency multiplier
d. frequency divider
D
C
R
D
C
R
D
C
R
D
C
R
Parallel data
input lines
Clock
Clear
Output
lines
Q0
Q1
Q2
Q3
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9. A retriggerable one-shot with an active HIGH output has
a pulse width of 20 ms and is triggered from a 60 Hz line.The output will be a
a. series of 16.7 ms pulses
b. series of 20 ms pulses
c. constant LOW
d. constant HIGH
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Answers:
1. b
2. d
3. b
4. c
5. b
6. d
7. d
8. b
9. d
10. a