Digital Design: Sequential Circuits for Registers and Counters Part - II
-
Upload
atush-jain -
Category
Education
-
view
58 -
download
1
Transcript of Digital Design: Sequential Circuits for Registers and Counters Part - II
![Page 1: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/1.jpg)
Chapter 16
Sequential Circuits for Registers and Counters
![Page 2: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/2.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2
Lesson 2
Shift Registers
![Page 3: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/3.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 3
Outline• Shift Register• Serial-In Serial-Out Register• Serial-In Parallel-Out Register • Parallel In Serial Out Shift Register• Parallel In Parallel Out Shift
Register
![Page 4: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/4.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 4
4-bit Shift Register • A shift register is a clocked sequential
circuit in which stored the binary word bits shift either towards left or towards right (towards higher place value or lower place value) on each successive clock transition.
![Page 5: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/5.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 5
4-bit Right Shift Register (n +1)th
clock transition after nth clock defined the present state
• Serial input → QA; • QA → QB; • QB → QC ;• QC → QD ;• QD = Serial out;• when output bits from left to right are
QA, QB, QC and QD.
![Page 6: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/6.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 6
4-bit Left Shift Register (n +1)th clock transition after nth clock defined the
present state• QD ← Serial input; • QC ← QD; • QB ← QC ;• QA ← QB ;• QA = Serial out• when output bits from right to left are
QD, QC, QB and QA.
![Page 7: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/7.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 7
Average Propagation Delay in Shifting at outputs
• Average propagation delay, tp of a Register is average interval tp from the +ve or -ve edge of CLK (Shift-clock) after which QA.. QD get the new values Q’A.. Q’D
![Page 8: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/8.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 8
Clock Edges • Shift register “looks upon” the data bits
at DD DC DB DA inputs (= Qs of previous state only) at the instant of a falling edge (-ve edge) in case of -ve edge D-FFs are used and at rising edge in case +ve edge D-FFs are used.
![Page 9: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/9.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 9
Outline• Shift Register• Serial-In Serial-Out Register• Serial-In Parallel-Out Register • Parallel In Serial Out Shift Register• Parallel In Parallel Out Shift
Register
![Page 10: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/10.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 10
4- bit Right Shift Register SISO using D-FFs
DQD
D-FFDQC
D-FFDQB
D-FFDQA
D-FF
CLK (shift)
Serial-in
4-bit Q Internal FF-Outputs
Serial-Out
![Page 11: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/11.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 11
4- bit Left Shift Register SISO using D-FFs
DQDD-FF
DQCD-FF
DQBD-FF
DQAD-FF
CLK (shift)
Serial-Out
4-bit Q Internal FF Inputs
Serial-In
![Page 12: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/12.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 12
Timing Diagram when +ve edge Clk D-FFs Right shift SISO
CLK(shift)
QA
QB
t
QC
1 or 0Serial in
QDSerial out
![Page 13: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/13.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 13
Timing Diagram when +ve edge Clk D-FFs Left shift SISO
CLK(shift)
QA
QB
t
QC
1 or 0Serial-in
QD
Serial out
![Page 14: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/14.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 14
Shift Register• A shift register shifts the transfers the
input D bits to next Qs such that Q’i (n+1) = Di after an interval from nth
clock edge instance plus propagation delay
![Page 15: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/15.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 15
Average Propagation Delay from input at one end to FF to last end FF
Q output• Average propagation delay, tp of a
Register is 4-times the average interval tp from the +ve or -ve edge of CLK (Shift-clock) after which QA.. QD get the new values Q’A.. Q’D
![Page 16: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/16.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 16
Outline• Shift Register• Serial-In Serial-Out Register• Serial-In Parallel-Out Register Parallel In Serial Out Shift Register
Parallel In Parallel Out Shift Register
![Page 17: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/17.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 17
4- bit Right Shift Register SIPO using D-FFs
DQD
D-FFDQC
D-FFDQB
D-FFDQA
D-FF
CLK (shift)
Serial-in
4-bit Q External FF-Outputs
Serial-Out
QDQCQBQA
![Page 18: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/18.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 18
4- bit Left Shift Register SIPO using D-FFs
DQDD-FF
DQCD-FF
DQBD-FF
DQAD-FF
CLK (shift)
Serial-Out
4-bit Q Internal Inputs
Serial-In
QDQCQB
QA
![Page 19: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/19.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 19
State Table for SIPO
• Refer Text
![Page 20: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/20.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 20
Outline• Shift Register• Serial-In Serial-Out Register• Serial-In Parallel-Out Register • Parallel In Serial Out Shift Register• Parallel In Parallel Out Shift Register
![Page 21: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/21.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 21
4- bit Right Shift Register PISO using D-FFs; L/S means load when 1 and shift when 0.
DQD
D-FFDQC
D-FFDQB
D-FFDQA
D-FF
CLK (shift)
Serial-Out
QD
XDXCXBXA
L/S
PR PR PR PR
CLRR R R R
S S S S
![Page 22: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/22.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 22
4- bit left Shift Register PISO using D-FFs; L/S means load when 1 and shift when 0.
D D-FFD D-FFD D-FF
QA
D-FF
CLK (shift) Serial- Out at QA
XDXCXBXA
L/S
PR PR PR PR
CLRR R R R
S S S S
QB QC QDD
![Page 23: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/23.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 23
State Table and State Diagram for PIPO
• Refer Text
![Page 24: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/24.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 24
D-FF from RS FFs
• RS FFs are used for PISO• R connects CLR input. When CLR = 0, then
all Qs become 0• Each R connects to S through a NOT gate• Each D input is at S input• Each X input is at AND. Other input of
AND connects Load/Shift (L/S) line.
![Page 25: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/25.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 25
Outline• Shift Register• Serial-In Serial-Out Register• Serial-In Parallel-Out Register • Parallel In Serial Out Shift Register• Parallel In Parallel Out Shift
Register
![Page 26: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/26.jpg)
26
PIPO Right Shift
DQD
D-FFDQC
D-FFDQB
D-FFDQA
D-FF
CLK (shift)
Serial-Out
QD
XDXCXBXA
L/S
PR PR PR PR
CLRR R R R
S S S S
QDQBQA
OE
QC
YDYBYA YC
![Page 27: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/27.jpg)
27
D D-FFD D-FFD D-FF
QA
D-FF
CLK (shift) Serial- Out at QA
XDXCXBXA
L/S
PR PR PR PR
CLRR R R R
S S S S
QB QC QDD
Left Shift PIPO
QA
OEYDYA YCYB
QBQDQC
![Page 28: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/28.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 28
A parallel in parallel out (PIPO) Shift Register
• Transfers the input bits X to next Qs such that Q’i (n+1) = X i after nth clock input.
• Loads the external inputs as the excitation inputs through ANDs
• Shifts on transition to the next state on a clock transition.
![Page 29: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/29.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 29
A parallel in parallel out (PIPO)
• Gives parallel outputs Ys through ANDs, which are the same as the next state. [Parallel Outputs mean Yi = Q’i and Parallel inputs mean Xi = Di at same time where i = 0, 1, 2 or 3 for a 4-bit PIPO. Note: i = 0, 1, 2... n-1 in an n-bit PIPO register]
![Page 30: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/30.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 30
A parallel in parallel out (PIPO) Shift Register
• Applied all n-inputs Xs on n-parallel input lines, called parallel load lines. Inputs load when L/S = 1
• All n-outputs Qs are on parallel lines.• Qs Shift on L/S = 0• Ys outputs on OE = 1
![Page 31: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/31.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 31
Summary
![Page 32: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/32.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 32
• Four type of Shift registers• SISO• SIPO• PISO• PISO
![Page 33: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/33.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 33
• Register shifts the inputs on clock edge because Q-input of one stage FF connects to D-input of next stage FF
• Left most D-FF input is serial input for right shift register
• Right most D-FF input is serial input for left shift register
• Left most D-FF output is serial output for left shift register
• Right most D-FF output is serial output for right shift register
![Page 34: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/34.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 34
End of Lesson 2 on
Shift Registers
![Page 35: Digital Design: Sequential Circuits for Registers and Counters Part - II](https://reader030.fdocuments.us/reader030/viewer/2022032619/55c41679bb61eb26058b465c/html5/thumbnails/35.jpg)
Ch16L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 35
Thank You