Devices, Lithography, Interconnect & Materials...Few Observations from IEDM (DEC 2014) •Moore’s...
Transcript of Devices, Lithography, Interconnect & Materials...Few Observations from IEDM (DEC 2014) •Moore’s...
© 2015 Synopsys, Inc. All rights reserved. 1
Devices, Lithography, Interconnect &
Materials
A GSA Update
Jamil Kawa
2/18/15
© 2015 Synopsys, Inc. All rights reserved. 2
Agenda
• Devices, Lithography, and Interconnect: The Trend
• What the “Big Players” are Saying- IEDM 2014
• More Technology Advances
• Summary
Confidential
© 2015 Synopsys, Inc. All rights reserved. 3
Moving Forward- The Trend
• The Driver: 100% Connectivity @ Zero
Power and…@ Zero Cost (example:
IoT)
• The Path: Drive Moore’s Law + More-
than-Moore + Koomey’s + Innovation
• The Bottlenecks: Physics + Economics
– Lithography: 193i
– Interconnect (R &C)
– Materials
– Variability
– Reliability (NBTI, HCI, tddb)
– $$$, or perhaps…
Confidential
Energy efficiency scaling: Instructions per μJ. (Source:
LaMarca (Intel), Intel Developer Forum 2012). It reflects
trends shown in publications by J Koomey (LBNL)
Improvement per
generation
Moore/
Dennard FinFET -First
generation
Density 2x <2x
Performance 2x Flattening
Clock scaling 50% 4%
Power/transistor -50% -21%
Power density 0% 58%
POWER
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Moving Forward- The Trend cont’d
• The Answer: Innovation
– Litho: Complimentary Pattering: DP, TP, QP + Spacer
Technology + EUV + DSA (directed self assembly) + atomistic
ion-implanters.. Etc
– Interconnect: low-k, air-gap,
– Materials: III-V materials, 2D materials, Graphene, Rare-Earth
– Devices: FinFETs, nano-wires, vertical nano-wires
– Structures : ReRAMs, Advanced Capacitors (energy storage)
– Litho + Material + Creative-ideas = Variability and Reliability
control
Lower variability -> lower VDD -> lower power
NBTI -> dramatic improvement
Confidential
© 2015 Synopsys, Inc. All rights reserved. 5
Moving Forward- The Trend cont’d
Few Observations from IEDM (DEC 2014)
• Moore’s law not slowing, but rather accelerating
– More innovation at existing 14/16nm FinFET nodes
Interconnect, materials, and thus power (lower) and performance
Interconnect with Air-Gap is here!
Controlled implants on Fin-base, etc…
High-k gate stack enhancements for NBTI
• FinFET to 7nm, nano-wires, TFETs, other beyond that
– 5nm vertical nano-wires on good development path
• IoT Themes:
– Major push in On-chip energy storage (MIM like)
– Power efficient and autonomous sensors
– Energy harvesting
Confidential
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Moving Forward- The Trend cont’d
IP
• ReRAM: big potential but not ready yet for prime time
– Main bottleneck: wide variability
• SRAM: still chasing lower power, higher speed, and
smaller footprint
• Wireless Power and Signal Transmission re-visited in
direct competition / Complementary to 3D-C
– Attempt at solving IO Speed Bottleneck (not scaling fast enough)
– Wafer thinning to ~ 10 μm
• More IoT driven schemes of energy harvesting including
thermal, Piezoelectric, Triboelectric, and Pyroelectric
– Self-sustaining wearable gadgets and autonomous sensors
Confidential
© 2015 Synopsys, Inc. All rights reserved. 7
Agenda
• Devices, Lithography, and Interconnect: The Trend
• What the “Big Players” are Saying- IEDM 2014
• More Technology Advances
• Summary
Confidential
© 2015 Synopsys, Inc. All rights reserved. 8
From Scott Jones
TSMC:16FF+ vs 16FF
• 15% speed improvement @ same power or a 30% power
improvement @same speed
INTEL: 14nm vs Intel’s 22nm
• Densest 16nm/14nm process available
• IDsat is 15% better for NMOS and 41% better for PMOS. Active
power is 30% better than 22nm with 10x better tddb(time dependent
dielectric breakdown) and less Vt variation.
• Air gaps are used on two of the interconnect layers
IBM: 14nm, SOI +eDRAM capable
Confidential
IBM Intel TSMC
Gate (CPP) 80nm 70nm 90nm
Metal 64nm 52nm 64nm
Gate x Metal 5,120nm2 3,640nm2 5,760nm2
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Intel- 14 nm
Confidential
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Intel cont’d
Confidential
• Air gap dielectric for 2 layers
• Huge improvement in reliability aspects
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TEM Images of Metal w. Air-gap
Confidential
K. Prall, IEDM 2010
(Fujitsu)
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IBM’s FDSOI
IBM - 20nm SOI, Gate First
• Thin film
– Effective back-biasing
• 20% tensile stress for N, 35% compressive for P
– Competitive and balanced Idsat for P and N
• 5 nm spacers
Confidential
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IBM’s FDSOI Basics
• Ultra-thin Body makes back-biasing possible and efficient
• Allows planar FDSO to continue past 20nm
• Allows for pretty low Vdd-min for SRAM and Logic
Confidential
© 2015 Synopsys, Inc. All rights reserved. 14
IBM FDSOI cont’d
Confidential
© 2015 Synopsys, Inc. All rights reserved. 15
Agenda
• Devices, Lithography, and Interconnect: The Trend
• What the “Big Players” are Saying- IEDM 2014
• More Technology Advances
• Summary
Confidential
© 2015 Synopsys, Inc. All rights reserved. 16
IBM – 14nm FinFET using DSA
• 29nm-pitch fins patterned using a technique called tone
inverted grapho-epitaxy (TIGER).
Confidential
Figure 7: critical dimension (CD), line edge roughness (LER)
and line width roughness (LWR) measured from SEM images of
5-fin-groups produced using the TIGER process. The CD of the
fin is a relative value and should not be construed as the actual
physical dimension. The variation in CD of the edge fins
compared to the nested fins is contained within the LWR value.
While the LWR is higher than desired, a number of process
parameters can be tuned to reduce it including improved tone
inversion materials and RIE optimization
• Targeted for 193i Litho beyond 10nm
• No mention of “L” in the paper but diagram shows ~ 10nm
© 2015 Synopsys, Inc. All rights reserved. 17
• Electrochemical capacitors fabricated using porous Si
nanostructures with very high surface-to-volume ratios and an
electrolyte
• Why capacitors?
– capture energy at high rates and low voltages as well as provide higher power,
albeit at lower energy densities, and degrade minimally from charging and
discharging.- No chemical reaction
– Capacitors are far more superior superior to Li batteries in life-cycling
Confidential
Energy Storage Technologies (Intel)
Integrated on-chip Porous Si Electro-Chemical Capacitors
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• Uses Porous-Silicon Electro Chemical capacitors with
progressive pore size as a function of depth (pore depth
12 μm)
– Inverse relationship between pore diameter and surface-area
density
– High aspect ratio makes path highly resistive. Tapering helps
reduce that
– Pore structure parameters are: 1) pore size 2) surface area 3)
porosity 4) depth 5) morphology
– Surface properties: 1) chemical stability 2) conductivity
3)wettability
• Obviously Intel is taking IoT and especially wearables
very seriously
Confidential
Energy Storage Technologies cont’d
Integrated on-chip Porous Si Electro-Chemical Capacitors
© 2015 Synopsys, Inc. All rights reserved. 19
Agenda
• Devices, Lithography, and Interconnect: The Trend
• What the “Big Players” are Saying- IEDM 2014
• More Technology Advances
• Summary
Confidential
© 2015 Synopsys, Inc. All rights reserved. 20
Summary - Generic
• Moore’s law not slowing, but rather accelerating
– More innovation at existing 14/16nm FinFET nodes
• FinFET to 7nm, nano-wires, TFETs, other beyond that
– 5nm vertical nano-wires on good development path
• SRAM: still chasing lower power, higher speed, and
smaller footprint
• ReRAM: big potential for large Caches but not ready yet
for prime time
• More research conducted on IoT building blocks such as
On-chip energy storage (MIM like) and Energy harvesting schemes
Confidential
© 2015 Synopsys, Inc. All rights reserved. 21
Supporting Slides
Confidential
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Basic Air-Gap Concept Illustration
Confidential
From Ph.D. Thesis of Dr. Je Min Park
U.C. Berkeley, 2011
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Capacitance and RC Delay Comparisons
Confidential
From Ph.D. Thesis of Dr. Je Min Park
U.C. Berkeley, 2011
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IoT – Sensors, Wearables, etc…
Confidential
An IBM simulation of an autonomous sensor system using the
IBM TrueNorth processor (SyNAPSE chip) with 5.4 Billion
transistors and a power budget of 20mW
Source: Skinny player URL. Designers: Chih-
Wei Wang and Shou-His Fu
© 2015 Synopsys, Inc. All rights reserved. 25
Id
Vg
DVT Over-
drive
Vdd
go
od
weak
leaky
SS
VT
+/-3sVT
Confidential
Variability & Vddmin
Aging + + + = Vddmin Adopted From Victor Moroz
© 2015 Synopsys, Inc. All rights reserved. 26 Modeling random variability: Victor Moroz, invited talk at WMED 2013 26
Variability Evolution: Planar to FinFET
The data is for the Lmin Wmin transistor
• Encouraging trend
• Several “reset
buttons”
• There is nothing
that can be done
to eliminate RDF,
so it kept getting
worse for planar
• The FinFETs are
more sensitive to
geometry, which
can be better
controlled by the
equipment
0
10
20
30
40
50
60
70
Sig
ma V
t, m
V
RDF p
RDF n
n-poly
HKMG
L CD&LER
W CD&LER
fin height
sigma pVt
sigma nVt
NMOS
PMOS
Confidential
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Components of NBTI
Different mutually uncorrelated processes
Trap generation: Breaking of Si-H (Si/IL interface) and
Ov-H bonds (IL bulk, IL/HK interface and beyond…)
Trapping: Process
related pre-existing
IL traps
Trap generation:
Creation of E’
centers (high VG);
negligible for HKMG Si
SiO(N)
HfO2
TiN Si-H
Ov-H
Pre-existing
hole traps
TDDB like trap
generation
(high VG stress)
H passivated Ov
defects
27
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Impact of NBTI on Threshold & Delay
Source: NBTI Modeling in the framework of temp. variation, Hamdioui, DATE 2010
Confidential
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• Double exposure: a sequence of two separate exposures of
the same photo-resist layer using two different photo-masks
Double Patterning Technology
Photoresist coating
First exposure
Second exposure
at different locations
Development of both
exposures in the photoresist
Confidential
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- First pattern
- Deposition of mask material
- Etching to from sidewall spacers
- Removal of first pattern
- Etching using remaining spacers as mask
- Removal of spacer, leaving final pattern
Self-Aligned Spacer
• A spacer is a film layer formed on the sidewall of a pre-patterned feature
• Since there are two spacers for every line, the line density doubles
Confidential
© 2015 Synopsys, Inc. All rights reserved. 31
2n lines after n iterations of spacer lithography!
Photo-lithographically
defined sacrificial
structures 1st Spacers 2nd Spacers 3rd Spacers
Spacer Lithography Rinse and Repeat
Confidential
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Line Width Roughness (LWR)
Spacer LWR LELE LWR
LER LWR= delta MAX-MIN
Confidential
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Directed self assembly (DSA) materials
Guided
Unguided behavior
Density multiplication
JSR, IBM, nextbigthing.com
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Methods to define small (base pattern) features
(DSA pitch division)
Researchers from the University of Wisconsin-Madison and Hitachi Global
Storage Technologies have reported a way to improve the quality and
resolution of patterned templates such as those used to manufacture hard
drives and other data storage devices. When added to lithographically
patterned surfaces such as those shown in the upper left panel of this
composite image, specially designed materials called block copolymers self-
assemble into structures, shown in the upper right panel, with improved quality
and resolution over the original patterns. These structures can be used to make
templates with nanoscale elements like the silicon pillars shown in the bottom
panel, which may be useful for manufacturing higher capacity hard disk drives.
(Credit: Courtesy of Paul Nealey)
EEtimes - JSR Corp., along with its U.S. operations, JSR
Micro Inc., have rolled out a new directed self-assembly
(DSA) technology for the sub-20-nm half-pitch node.
Developed as part of an ongoing research agreement with
IBM Corp., the new technology eliminates dual exposure
steps and is compatible with conventional 193-nm
lithography equipment.
© 2015 Synopsys, Inc. All rights reserved. 35
Complementary patterning (contacts)
Exposure a Exposure b
Trim Exposure
Combining
process
Trim
process
Step 1: print a
regular array of
dots. Options
include:
• Use a two-
step process
involving
crossed
gratings.
• Directed self-
assembly.
Step 2: Expose a trim
pattern and apply a
cutting process.
Options
include:
• ArF (193i) with a
feature-shrinking
process.
• EUV.
• eBeam direct write
Confidential
© 2015 Synopsys, Inc. All rights reserved. 36 Wider fins keep more doping to block the leakage 36
Creative Fin Doping Techniques
• Tilted implants at higher energy
• Segregation into thermal oxide
• Dopant trapping at the interface
Confidential
© 2015 Synopsys, Inc. All rights reserved. 37
IEDM Observations – ReRAM (or RRAM)
Confidential
Main themes
• Non-volatility makes it ideal for IoT applications requiring
zero-power in sleep mode
– Size is very small (1/8 flash for 1T-1R) and still dense for 2T-2R
– Speed acceptable for most applications currently using FPGAs
– Obviously more so for IoT sensors and wearables
• Low Power
• Easier to integrate with plain CMOS than FLASH
Memories
© 2015 Synopsys, Inc. All rights reserved. 38
RRAM (ReRAM)
• Biggest problem: high variability
– One paper (Rambus and Tsinghua University, and Technische
Universitat Munchen) reported a reduction in worst case write
current by 33% and fail bit count by 23x using a TiN,
Conductive TaO2/HfO2/TiN
• Control of capacitive surge currents during switching.
– If capacitive surge currents are high during FORM and SET
operations filaments are known to become stronger and
require higher RESET current to break.
– Reproducibility of switching, which is crucial for building
commercial products, is also sensitive to capacitive surge
currents.
Confidential
© 2015 Synopsys, Inc. All rights reserved. 39
Piezoelectric
• Piezoelectric Effect is the ability of certain materials to generate an electric
charge in response to applied mechanical stress.
• Inverse piezoelectric effect causes a change in length in this type of
materials when an electrical voltage is applied
• Effect is only observed in some crystals
Confidential
© 2015 Synopsys, Inc. All rights reserved. 40
Triboelectric
• A Tribo-electric Energy Harvester (TEH)
intentionally generates triboelectricity through
contacting two different materials. It uses
triboelectric charge to drive an iterative current via
electrostatic conduction
Confidential
© 2015 Synopsys, Inc. All rights reserved. 41
Donavan’s Pyro-electric Generation -
Waste energy conversion
MEMS pyroelectric generator: from Oak Ridge National Laboratories).
Confidential
• Pyroelectricity is the ability of certain materials to generate a temporary
voltage when they are heated or cooled.
• The change in temperature modifies the positions of the atoms slightly within
the crystal structure, such that the polarization of the material changes.
© 2015 Synopsys, Inc. All rights reserved. 42
• Carrier transport is increasingly ballistic, ~80%
• Variability is improving by addressing critical points
• Ge and III-V are too leaky for LP, give ~2x boost for
HP
• One nano-wire strength is comparable to one fin
• MOL parasitics dominates 7nm/5nm performance
• NW’s provide 3.6x speed boost at 5x lower power
42
Summary – Device Centric
Confidential
© 2015 Synopsys, Inc. All rights reserved. 43
BACK-UP SLIDES
Confidential
© 2015 Synopsys, Inc. All rights reserved. 44
Impact of NBTI on threshold and delay
Source: NBTI Modeling in the framework of temp.
variation, Hamdioui, DATE 2010 Confidential
© 2015 Synopsys, Inc. All rights reserved. 45
• 2-input NAND library cell
• Ge SOI FinFET is similar
• Hypothetic double strength
FinFET is 2.6x faster with 24%
switching energy reduction
• Si FinFET with oxide spacer is
even better, especially in
energy
• Low-k spacer is not necessary
• GAA lateral NW has equivalent
performance to FinFET with
oxide spacer
• 5nm vertical NW is really fast
(3.6x over Si) and really low
power (5x less energy)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 10 20 30 40 50 60 70 80 90
En
erg
y, f
J
Delay, ps
Engineering 7nm and 5nm Logic Cells
45
14nm
Confidential
Synopsys paper @ IEDM 2014