SN 16nm DAC IP Macro Test Chip 02 - Socionext Europe
2
16nm DAC IP Macro / Test Chip 70 - 120GSa/s 8-bit DAC H-Family Socionext has over 40 years’ experience and is a leader in state-of-the art system-on-chip technology and provides high-performance SoC designs, serial transceiver tech- nologies and advanced packaging solutions. Socionext’s proprietary CHAIS 1 high-speed converter technology, which allows implementation of extremely fast, high-resolution DAC with low power consumption that can be integrated with millions of gates in standard CMOS process, is the latest in a series of IP offerings. Developed in TSMC 16FF+ process technology, the high- speed DAC has been designed to cover a broad sampling rate range from 70GSa/s to 120GSa/s (DAC H-family). The high- effective resolution and wide-bandwidth characteristics of previous generations of CHAIS are now supported in a smaller process node, enabling lower power SoC solutions for coherent optical transceivers and high-speed test equipment but is also capable of supporting a whole range of other application areas. DAC IP Macro Basic Features Foundry TSMC Technology: 16nm FF+ Sampling rate (Fs): 70-120GSa/s Bandwidth (-3dB): 0.31*Fs Typical differential analogue output: 800mVPPDIFF Fully programmable and high-performance fractional DPLL Available in single channel, IQ pair, 2x IQ pair and 4x IQ pair Output clock @Fs/128 to digital core per channel Fully specified for -5°C to 100°C operation APB control interface Silicon proven and used in production, immediately available Deliverables Documentation: datasheet, user guides, test report Hard macro & integration support Abstract LEF and timing LIB files with constraints Behavioral verilog model Example test bench Layout/package guide Applications High-Speed Communication Systems Wireline/Optical Networking Wireless/Satellite Communication Antenna/Phased-Array/MIMO Systems Test & Measurement Equipment Industrial and Customer Applications 1 CHAIS – CHArge-mode Interleaved Sampler technology Overview
Transcript of SN 16nm DAC IP Macro Test Chip 02 - Socionext Europe
16nm DAC IP Macro / Test Chip70 - 120GSa/s 8-bit DAC H-Family
Socionext has over 40 years’ experience and is a leader in state-of-the art system-on-chip technology and provides high-performance SoC designs, serial transceiver tech-nologies and advanced packaging solutions.Socionext’s proprietary CHAIS1 high-speed converter technology, which allows implementation of extremely fast, high-resolution DAC with low power consumption that can be integrated with millions of gates in standard CMOS process, is the latest in a series of IP offerings.
Developed in TSMC 16FF+ process technology, the high- speed DAC has been designed to cover a broad sampling rate range from 70GSa/s to 120GSa/s (DAC H-family). The high-effective resolution and wide-bandwidth characteristics of previous generations of CHAIS are now supported in a smaller process node, enabling lower power SoC solutions for coherent optical transceivers and high-speed test equipment but is also capable of supporting a whole range of other application areas.
DAC IP Macro Basic Features Foundry TSMC Technology: 16nm FF+ Sampling rate (Fs): 70-120GSa/s Bandwidth (-3dB): 0.31*Fs Typical differential analogue output: 800mVPPDIFF Fully programmable and high-performance fractional
DPLL Available in single channel, IQ pair, 2x IQ pair and
4x IQ pair Output clock @Fs/128 to digital core per channel Fully specified for -5°C to 100°C operation APB control interface Silicon proven and used in production, immediately
available
Deliverables Documentation: datasheet, user guides, test report Hard macro & integration support Abstract LEF and timing LIB files with constraints Behavioral verilog model Example test bench Layout/package guide
Applications High-Speed Communication Systems Wireline/Optical Networking Wireless/Satellite Communication Antenna/Phased-Array/MIMO Systems Test & Measurement Equipment Industrial and Customer Applications
1 CHAIS – CHArge-mode Interleaved Sampler technology
Overview
Test Chip (ES)Evaluation of Socionext’s 16nm CHAIS converters can be conducted via a customized hardware & software platform. Test chips for the 70-120GSa/s 8-bit DAC H-family have2 DAC channels (one IQ pair).Each of these channels has a capture RAM (waveform memory) to store 512k x 8-bit samples.The data transfer from / to the waveform memory is via an industry standard SPI databus running at 3MHz.
For more detailed information on the macro family and support, please contact your Socionext representative.
For more detailed information on the macro family and support, please contact your Socionext representative.
4-Channel DK
Block Diagram - Example for a 4-channel DAC IP macro
4-Channel Test Chip (ES)
The Products and product specifications described in this document are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. All company names, brand names and trademarks herein are property of their respective owners.
Copyright 2020 Socionext EuropeDocument code: February 2020Edited: Marketing/Network Solution
Pittlerstrasse 4763225 Langen, GermanyTel: +49-6103-3745-312Email: [email protected] https://eu.socionext.com
Branch: Socionext Europe GmbH 3 Concorde Park, Concorde Road, SL6 4FJ, Maidenhead, UK
Socionext Europe GmbH
DAC IP Macro (H-Family) Part Numbers SNEUDAC120H16 - full rate: 70 - 120GSa/s
Support Development Kit and DAC test chip for customer
hands-on experience Test program development support SI/PI design support
Development KitPart Number: SNEUADCDAC16H-DK
2x ES boards allowing for synchronous operation of 2x DAC & 2x ADC, or 4x ADC, or 4x DAC
High-performance PCB with optimised analogueinterfaces
On-board Raspberry Pi® including easy to use GUI Complete stand-alone system
Socionext’s proprietary CHAIS1 high-speed converter technology is the latest in a series of IP offerings driving advanced systems for fibre optic networks. Developed in TSMC 16FF+ process technology, the high-speed ADC and DAC family has been designed to cover a broad sampling rate range from 15 to 103GSa/s (ADC H-family) and 70 to 120GSa/s (DAC H-family).The high-effective resolution and wide-bandwidth characteristics of previous generations of CHAIS are supported in a smaller process node, enabling lower power SoC solutions for coherent optical transceivers. The high- effective resolution and wide-bandwidth characteristics of previous generations of CHAIS are now supported in a smaller process node, enabling lower power SoC solutions for coherent optical transceivers and high-speed test equipment but is also capable of supporting a whole range of other application areas.
Evaluation of Socionext’s 16nm CHAIS converters can be conducted via a new customized hardware and software platform. Test chips for the 34 - 120GSa/s 8-bit ADC family have 2 ADC channels (one IQ pair). Each of these channels has a capture RAM to store 512k X 8-bit samples. The RAM contents can be accessed directly via the device SPI interface to the USB/FPGA interface on the accompanying evaluation board. Test chips for the 34 - 120GSa/s 8-bit DAC family have 2 DAC channels (one IQ pair) and each of these channels has 512k x 8-bit waveform memory.
SNEUADCDAC16H Development Kit 15 - 103GSa/s 8-bit ADC H-Family | 70 - 120GSa/s 8-bit DAC H-Family
Overview Test Chip (ES)
ADC/DAC Test Chip Features (supported with DKs)■ Technology: 16nm FF+■ Resolution: 8-bit■ Sampling rate (Fs):
- 70 - 120GSa/s (DAC H-family)- 15 - 103GSa/s (ADC H-family)
■ Fractional DPLL per IQ pair■ ADC-specific features
- Programmable analogue input range:0.5 – 1.7VPPDIFF
■ DAC-specific features- Typical differential analogue output:
800mVPPDIFF
Applications■ High-Speed Communications■ 100G to Terabit Systems■ Test & Measurement Equipment■ Industrial and Customer Applications
I_ADCinout
Q_ADCinout
I_DACout in
out in
DPLL
ADCnAIP
REFCLKIP
DPLL
SPIJTAG
AVDDVDDVSS
ADCnAIN
ADCnAQP
ADCnAQN
DACnAIP
DACnAIN
DACnAQP
DACnAQN
REFCLKIN
WaveformMemory
WaveformMemory
ES Block Diagram
1 CHAIS – CHArge-mode Interleaved Sampler technology - which allows implementation of extremely fast, high resolution ADC with low power consumption that can be integrated with millions of gates in standard CMOS process
Q_DAC
