Development of the FE-I4 pixel readout IC for b-Layer Upgrade & Super-LHC Michael Karagounis on...

Development of the FE-I4 pixel readout IC

for b-Layer Upgrade & Super-LHC

Michael Karagounis on behalf of the ATLAS PIXEL Upgrade FE-I4 collaboration

16.09.2008 TWEPP 2008 - FE-I4 pixel readout IC - Michael KaragounisSlide 2

Upgrade of the Current ATLAS Pixel Detector

FE-Chip FE-Chip

sensorMCC

pixel detectorpixel detector

b-Layer (innermost)b-Layer (innermost)

hybrid pixel modulehybrid pixel module

FE-I3

machine upgrade & consequences for the pixel detectormachine upgrade & consequences for the pixel detector~2013: ~2013: b-Layer upgradeb-Layer upgrade expected sensor performance degradation caused by radiation expected sensor performance degradation caused by radiation possible x2-3 luminosity increase at ~2013 (new triplets & injection chain) possible x2-3 luminosity increase at ~2013 (new triplets & injection chain)b-layer insert at smaller radius 3.7cmb-layer insert at smaller radius 3.7cm~2017: ~2017: super-LHC upgradesuper-LHC upgrade ~ x10 luminosity increase ~ x10 luminosity increase

FE-I4 targets the b-Layer upgrade in ~2013 & the outer layers at SLHC FE-I4 targets the b-Layer upgrade in ~2013 & the outer layers at SLHC

ATLASATLAS

16.09.2008 TWEPP 2008 - FE-I4 pixel readout IC - Michael Karagounis

• smaller b-Layer radius & potential increased luminosity smaller b-Layer radius & potential increased luminosity higher hit higher hit raterate

FE-I3FE-I3 column-drain architecture column-drain architecture not able to copenot able to cope with x3 increased hit rate.with x3 increased hit rate.

Smaller pixel sizeSmaller pixel size 50x400um 50x400um 50x250um 50x250um (reduce pixel cross section)(reduce pixel cross section)

New digital architectureNew digital architecture for increased data volume for increased data volume• Material reduction & improve of active areaMaterial reduction & improve of active area bigger chip sizebigger chip size 7.6x8mm 7.6x8mm ~20.0x18.8mm ~20.0x18.8mm reduce size of peripheral chip areareduce size of peripheral chip area increase cost efficiencyincrease cost efficiency• Power consumptionPower consumption analog design for reduced currentsanalog design for reduced currents decrease of digital activity by decrease of digital activity by sharing digital circuitssharing digital circuits with several pixels with several pixels Reducing cable losses by Reducing cable losses by new powering schemenew powering scheme• New sensor technologiesNew sensor technologies Adapt to several sensor types (3D,diamond, planar) with different detector Adapt to several sensor types (3D,diamond, planar) with different detector

cap. & leak.cap. & leak.

• Higher integration density for digital circuitsHigher integration density for digital circuits• Increased radiation tolerance of 130nm tech. with respect to 250nm Increased radiation tolerance of 130nm tech. with respect to 250nm

tech.tech.Slide 3

Motivation for FE-I4 Development

Why a Why a redesignredesign ? ?

Why a new Why a new technology?technology?

FEI3 inefficiencies

Hit prob. / DC

LHC

3xLH

C

sLHC

pile-upbusy/waitinglate copytotal inefficiency

ineffi

cienc

y


Collaboration Effort

FE-I4-P1FE-I4-P1 institutes involved:institutes involved:Bonn, CPPM, Genova, LBNL, Nikhef Bonn, CPPM, Genova, LBNL, Nikhef

core blockscore blocks• analog readout electronicsanalog readout electronics• new concept of digital pixel logicnew concept of digital pixel logic• readout scheme of double columnreadout scheme of double column

peripheric blocksperipheric blocks• bandgap reference & DACs bandgap reference & DACs biasing & calibration biasing & calibration• voltage regulators voltage regulators power management power management• LVDS TX/RX LVDS TX/RX fast off-chip communication fast off-chip communication• slow controlslow controlcollaborative toolscollaborative tools• weekly phone meetingweekly phone meeting• VCS shared design database based on VCS shared design database based on ClioSoftClioSoft tool tool

LDORegulator

ChargePump

CurrentReference

DACs

Cont

rol

Bloc

kCa

pacit

ance

Mea

sure

men

t

3mm3mm

4mm4mm

submitted @ 24-Mar-08submitted @ 24-Mar-08

61 x 14Array


Analog Readout Chain

Preamp

Am

p2

FDAC

TDAC

Config Logic

discri

• two-stage architecture optimized for low power, low noise and fast rise time

• additional gain Cc/Cf2~ 6• more flexibility on choice of Cf1• charge collection less dependent on detector capacitor

• decoupled from preamplifier DC potential shift caused by leakage

• Local DACs for tuning feedback current and global threshold

• charge injection circuitry

145 m

50 m

Cc

Cf2Cf1

Preamp Amp2

feedbox feedbox

Inj0

Inj1

injectIn

Cinj1

Cinj2

+local

feedback tune

FDAC4 Bit

Vfb

+local

thresholdtune

TDAC5 Bit

Vfb2

+

-

HitOutNotKill

Vth


Preamplifier Feedback & Leakage Compensation

Vin

Vbp

Vbn

Vout

vfb

VbnLcc

Cf1=17fF

• Regulated cascode preamplifier Regulated cascode preamplifier High gain High gain Less biasing voltages Less biasing voltages Less crosstalk pathsLess crosstalk paths

• Triple Well NMOS input transistorTriple Well NMOS input transistor shielded from substrate noiseshielded from substrate noise

• NMOS feedback transistor for NMOS feedback transistor for constant current discharge of the constant current discharge of the feedback capacitorfeedback capacitor

• Leakage current compensation basedLeakage current compensation basedon differential amplifieron differential amplifier

constant current feedback

leakage compensation

2ke<Qin<22ke10mV DC shift

@ 100nA leakage

Vout[V]

t[s]

Vout[V]

t[s]

200m

250m

225m

0.1 0.5

0.1 0.5

200m

300m

380m


2-nd Stage Amplifier & Comparator

Vbp

Vbn

VinVbpbuf

Vout

Cf2=6.86fF

Vbpff • PMOS input folded regulated cascode• expecting negative going output• might be changed to straight cascode• classic 2-stage comparator design

20 ns timewalk for 2ke-< Qin< 52ke- & threshold @1.5ke-

ENC=160e- @ Cd=0.4p and Il=100nA

DisOut

Unbias

DisIn

VthIn

ENC[e-]

Cd[F]

Qin[C]

tLE[s]

2nd stage amplifier

comparator

100f 200f 300f

60

100

150

10k 20k 30k 40k

Il=0nA

20n

10n

0


Digital Readout Architecture

Digital Part

DA

TA

Control

Free

ze

Hit

EO

C B

uffe

r

TriggerLogic

Control

ClusteringLogic

Shared Digital Part

Local Buffer

DA

TA

TriggerLogic

FE-I3 FE-I4

• All pixel hAll pixel hits are sent to the EoC buffer its are sent to the EoC buffer outside the active area at the bottom of the outside the active area at the bottom of the chipchip• A hit A hit pixel is blocked until the double pixel is blocked until the double column buscolumn bus is free is free and the data has been sent out and the data has been sent out• Every Pixel has its own digital circuitryEvery Pixel has its own digital circuitry

bottleneck

• 99% of hits will not be triggered for off-99% of hits will not be triggered for off-chip chip transmission transmission no need to move hits to no need to move hits to EoC!EoC! Storage of hits in buffers at pixel levelStorage of hits in buffers at pixel level Local synchronization to trigger latencyLocal synchronization to trigger latency• Pixels are grouped together to logic units.Pixels are grouped together to logic units. Logic units are grouped to buffer regions Logic units are grouped to buffer regions

Both FE readout basedBoth FE readout basedon double columnon double column

structurestructure

EOC


Simulation of Digital Architecture

Two sources of inefficiencies are identified in the FE-I4 architecture

~0.5 % 5 cells

~0.1 % 6 cells

tota

l ine

ffici

ency

fr

acti

on

FE-I4 inefficiency as function of hit rate

x6

• Pile-Up Inefficiency: proportional to logic unit (pixel) area & mean ToT. Handle: reduce cross-section (back to single pixel or truncation); aggressive return to baseline (decrease ToT)• Local Buffer Overflow Inefficiency: Handle: increase size of Logic Unit / Local Buffer “averaging out effect” increase # of cells per Local Buffer.

Loca

l Buff

er O

verfl

ow in

eff.

[%]

FE-I4 Local Buffer overflow ineff. as function of number of buffer cells

(3xLHC)

At 2-3 times LHC luminosity and r~3.7cm, FE-I4 inefficiencies acceptable Implementation at RTL & gate level (+ integration of the 2 simul. framework) is actively going

on.


LVDS Driver

Vbn

Io

600u600u 1800u

M11 M14

M1

M2 M3VcmVofs

Vbp

Vbn

• Standard LVDS architecture for Standard LVDS architecture for 320MHz320MHz clockclock rate and adapted to low rate and adapted to low supply voltage supply voltage 1.5-1.2V1.5-1.2V• Current is routed to/from the output by Current is routed to/from the output by four four switches M3-M6 switches M3-M6• Common-mode voltage is measured by a Common-mode voltage is measured by a resistive divider and controlled by a resistive divider and controlled by a common-common- mode feedback circuit mode feedback circuit• Output currentOutput current is switchable between is switchable between 0.6 -0.6 -3mA3mA

Boni et al., IEEE JSSC VOL. 36 NO. 4, 2001

M3 M4

M5 M6

CMFBCMOSdriver

D

D

D

VofsVcm

Vbp

Vbn

5pF

5pF

100k 100k

TX

TX

Dn

DD


LVDS Driver with Tristate Option

• Might be beneficial for multiplexing the output Might be beneficial for multiplexing the output signal signal of of several FE chips through one transmission several FE chips through one transmission lineline at at the outer layers the outer layers• Switching Transistors M3 - M6 are steered by Switching Transistors M3 - M6 are steered by seperate seperate signals signals• All switches can be left open at the same time All switches can be left open at the same time giving giving a high impedance state at the LVDS driver a high impedance state at the LVDS driver outputoutput• Switching signals are set by additional tristate Switching signals are set by additional tristate logiclogic

M1

M2

M3 M4

M5 M6

Iout

IoutN

TristateLogic

Nn

Pn

EN

DI P

N

DI EN N Nn P Pn Out

0 0 0 0 1 1 hZ1 0 0 0 1 1 hZ0 1 0 1 0 1 01 1 1 0 1 0 1

Tristate Logic

Transmission Line

TX+

-

TX+

-

TX+

-TX

+

-


LVDS Receiver

M11M12 M13 M14

M8

M9 M10

M4 M5 M6M7

M1

M2 M3

IN1 IN2M14

M15M16

M18M17

OUT

M20M19

M21 M22

Tyhach et al., Tyhach et al., A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface,

IEEE JSSC, Sept. 2005

• parallel PMOS/NMOS comparator input parallel PMOS/NMOS comparator input stagesstages allow operation in a wide range of common- allow operation in a wide range of common-modemode voltages voltages• cross coupled positive feedback structure cross coupled positive feedback structure allowsallows introduction of hysteresis introduction of hysteresis• second stage sums singals from both input second stage sums singals from both input stage stage and converts them to a CMOS output signal and converts them to a CMOS output signal


LVDS Chip Layout & Measurements

• 21-Jul-2007:21-Jul-2007: first test chip submitted to UMC 130nm via Europractice mini-asic first test chip submitted to UMC 130nm via Europractice mini-asic runrun real hardware test of chosen architecture for use in FE-I4 real hardware test of chosen architecture for use in FE-I4• 24-Mar-2008:24-Mar-2008: 4 channel LVDS transceiver chip submitted to IBM 130nm (LM) 4 channel LVDS transceiver chip submitted to IBM 130nm (LM) via CERN via CERN for use in a SEU test setup for use in a SEU test setup characterization of new cables and flex types characterization of new cables and flex types• 15-Sep-2008:15-Sep-2008: LVDS driver with LVDS driver with tristate optiontristate option submitted to IBM130nm (DM) submitted to IBM130nm (DM) via MOSISvia MOSIS

UMC 130nmUMC 130nm

IBM 130nmIBM 130nm Preliminary Measurements on the IBM 130nm Transceiver Preliminary Measurements on the IBM 130nm Transceiver ChipChip

40MHz

160MHz

320MHz

Clock-Rate

Common Mode Voltage

1.05V

600mV

150mV

TX outputTX output Chained RxTx output @ 320 MHz ClockChained RxTx output @ 320 MHz Clockwith differential probe and 100 Ohm on board termination @ 1.2V supplywith differential probe and 100 Ohm on board termination @ 1.2V supply

0.8mm0.8mm

1.8mm1.8mm

1.5mm1.5mm

1.5mm1.5mm


Powering Options Under Consideration

• Reduction of cable material budget• Limitation of cable power lossesMinimization of current flowing through supply linesTwo powering options are investigated:

Shunt LDO

FE-I41.2V1.5V Shunt LDO

Shunt LDO

FE-I41.2V1.5V Shunt LDO

IinIout

2x DC/DC LDO

FE-I4 1.2V1.5V

3.3V

2x DC/DC LDO

FE-I4 1.2V1.5V

x2 DC/DC switched capacitor based conversion serial powered modules & „Shunt LDO“ regulation


Low Drop Out Regulator

• LDO regulator for Vin=1.6V,Vout=1.5-1.2V minimun drop out voltage 100mV• Iload=500mA• Line Regulation :

• Load Regulation:

+

-

Vin

Vref

Vout

R1

R2

Cout

M1

201

1005

mVmV

Arg

VV optmpt

in

out

m

mAmV

Ar

IVout opt

load

331505

1

M4M5

M1

M2 M3VinPVinN

Vbp

Vout

M6M7

M8 M9M10

M11M12

M13

M14

M15

• 2 stage error amplifier with fully-differential first stage and common-mode feedback biasing• Rail-to-rail Class-AB output • No need for transistors M4 & M5 to be gate-drain connected which would reduce the output impedance and the gain of the first stage

Error Amplifier

A

SpecificationLDO useful for both powering schemes


LDO Stabilization by Zero Cell

Vin

Iout

Vbn

Vbpc

Vbp

M2

M4

M5

Cz

VbncM1

M4 M5

M1

M2 M3

Vin

M16

M7 M9M10

M13 Iout

Vbn

Vbnc

Vbpc

M8

M11M12

M14

M15

M17

Vbn Vbn

Chava,Silva-Martinez, A Frequency Compensation Scheme for LDO Voltage Regulators, IEEE Transactions on Circuits and Systems, June 2004

New Zero Cell

+

-

Vin

Vref

Vout

R1

R2

Cout

M1

i=sCVout

f[Hz]1k 1M 1G

10

30

[dB] • Zero is introduced in the open loop transfer function by a frequency dependent voltage controlled current source• Less peaking of Vout in comparison with compensation by RESRof Cout• A frequency dependent current is flowing through the capacitor at the source of M13 which is mirrored to the output.• New Zero Cell based on transimpedance amplifier input stage • AC coupled input No need for source follower -> No current mirror• Only pole: Input impedance at the source of M1 High bandwidth

submitted to IBM 130nm (DM) 15-Sep-2008 via MOSISsubmitted to IBM 130nm (DM) 15-Sep-2008 via MOSIS


2x DC/DC switched capacitor based conversion

Rout includes 25mu long wire bond resistances singlein- & output and cap bonds due to small pads

Measurement with Cpump=0.22uF (0201 package)

Good radiation performance of 3.3V ELT NMOS transistor is crucial for succesful operationFirst irrradiation results are very encouraging (see spare slide)

On chip four transistor switching scheme using 3.3V thick gate oxide devices To avoid shorts between Vin & Vout or Vout & GND three nonoverlapping clocks are used

33 33

33 33

Vin

Vout

Cout

Cpump

ClkTop

ClkBot1 ClkBot2

GND


New Shunt Concept Basic Ideas

• Shunt regulator generates constant output voltage out of a current supply.• Parrallel placed shunt regulatros need an input resistor Rslope for safe operation• Resistor Rslope reduces the slope of the Iin=f(Vout) characteristic Mismatch has less influence on current distribution and device break down is avoided• Rslope has no regulation contribution but burns power Replacement of Rslope by a regulated „resistor“• Shunt regulator was meant to be used in combination with a LDO Change chain order and place LDO before the shunt• The LDO PMOS power transistor becomes the regulated „resistor“ Rslope•The shunt transistor becomes part of the LDO load

+

-Vref

Vout

R1

R2

M1

Iin

Iout

IsupplyRload

Rslope

+

-

Vin

Vref

Vout

R1

R2

M1

without resistorIin[mA] with resistor

Vout[V]

750

500

250

0

0 0.5 1 1.5 2


LDO Regulator with Shunt Transistor Simplified Schematic • Combination of LDO and shunt transistorCombination of LDO and shunt transistor

• M4 shunts the current not drawn by the loadM4 shunts the current not drawn by the load• Fraction of M1 current is mirrored & drained Fraction of M1 current is mirrored & drained into M5into M5• Amplifier A2 & M3 improve mirroring accuracyAmplifier A2 & M3 improve mirroring accuracy• Ref. current defined by resistor R3 & drained Ref. current defined by resistor R3 & drained into M6into M6• Comparison of M5 and ref. current leads to Comparison of M5 and ref. current leads to constant constant current flow in M1 current flow in M1• Ref. current depends on voltage drop VRef. current depends on voltage drop V IinIin - V - Voutout

which again depends on supply current Iin which again depends on supply current Iin• „Shunt-LDO“ regulators having completely Shunt-LDO“ regulators having completely different different output voltages output voltages can be placed in parallelcan be placed in parallel without without any any problem regarding mismatch & shunt current problem regarding mismatch & shunt current distributiondistribution• Resistor R3 mismatch will lead to some variation Resistor R3 mismatch will lead to some variation of of shunt current but shunt current but will not destroy the regulatorwill not destroy the regulator• „ „Shunt-LDO“ Shunt-LDO“ can cope with an increased supply can cope with an increased supply currentcurrent if one FE-I4 does not contribute to shunt current if one FE-I4 does not contribute to shunt current e.g.e.g. disconnected wirebond disconnected wirebond ref current goes up ref current goes up• Can be used as an Can be used as an ordinary LDO when shunt is ordinary LDO when shunt is disableddisabled

+ -

+

-

+

-

Iin

Iout

Vref

Vout

A1

A2

A3

M1M2

M3

M4

M5

R1

R2

Vin

Iload

R3

M6

Ishunt

submitted to IBM 130nm (DM) 15-Sep-2008 via MOSISsubmitted to IBM 130nm (DM) 15-Sep-2008 via MOSIS

slope R3/mirror ratio slope R3/mirror ratio 2kOhm/1000=2Ohm2kOhm/1000=2Ohm

Parallel placed regulatorsParallel placed regulatorswith different output voltagewith different output voltage

Same shunt currentSame shunt currentdrawn by both devicesdrawn by both devices

Vout=1.2Vout=1.5


Conclusion / Plans

• New Pixel Front-End IC targeting both b-layer upgrade and the outer layers of sLHC is being developed

• The prototype FE-I4-P1, LVDS Transceiver & SEU Test Chip returned from production

• Functional test and Pre & Post irradiation characterization is beeing performedFunctional test and Pre & Post irradiation characterization is beeing performed

• Digital architecture of FE-I4 is currently being defined. Implementation at RTL level has Digital architecture of FE-I4 is currently being defined. Implementation at RTL level has started.started.

• Additional blocks to study new concepts on real hardware have been developed & Additional blocks to study new concepts on real hardware have been developed & submitted submitted LDO with shunt ability LDO with shunt ability „SHULDO“„SHULDO“, LDO with , LDO with enhanced „Zero Cell“ compensationenhanced „Zero Cell“ compensation, LVDS , LVDS tristate drivertristate driver

Design of a full-scale layout is foreseen for the year 2009 Design of a full-scale layout is foreseen for the year 2009

Analog Pixel Array LDO RegulatorCurrent Reference LVDS TX/RX

DC/DC Charge Pump Control BlockCap. Measurement SEU Test Structure


SPARE SLIDE: FE-I4 Specification


SPARE SLIDE: Preliminary irradiation results

0 dose curves look funny due to some parasitic turning on. Transistor being measured is not isolated. Somehow the radiation has cured this parasitic.

First measurement of enclosed geometry 3.3V transistors in 0.13um process

3.3V NMOS ELT


Bottom of Chip is more critical:

A = circuit area (~independent of array size)D = defect density ~ 0.5 / sq. cm. (from MOSIS)for A=2mm x 20mm, Yield = 82%

Pixel array

Bottom of chip

Defects in the pixel array should lead by redundant design predominantly to the loss of a single pixel or region.

A few dead pixels or regions can be tolerated for physicsgrade chips

Even with some dead pixels its like having 100% yield

Assuming 15% of the pixel area contains very critical circuits meaning defects there would lead to the lossof more than one pixel or region (e.g. whole column)

We get Y= 78% for array A = 20mm x 17mm

Yield = [ (1-e-DA) / DA ]2,

Combined yield = 64% for 80x336 chip, 68% for 64x320 chip

SPARE SLIDE: Chip Yield


The ATLAS Pixel Upgrade FE-I4 collaboration

Bonn - David Arutinov, Marlon Barbero, Tomasz Hemperek, Michael Karagounis

CPPM - Denis Fougeron, Moshine Menouni

Genova - Roberto Beccherle, Giovanni Darbo

LBNL - Robert Ely, Maurice Garcia-Sciveres, Dario Gnani, Abderrezak Mekkaoui

Nikhef - Ruud Kluit, Jan David Schipper

Development of the FE-I4 pixel readout IC for b-Layer Upgrade & Super-LHC Michael Karagounis on...

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