PADFRAME Michael Karagounis. 03.11.2009 FE-I4 Review - Padframe - Michael Karagounis Questions &...

PADFRAME

Michael Karagounis

03.11.2009 FE-I4 Review - Padframe - Michael Karagounis

Questions & Answers LVDS 1

Answer: No, but they are compatible to commercial LVDS circuits

Question: Do your LVDS circuits meet the specs of the LVDS standard

03.11.2009 FE-I4 Review - Padframe - Michael KaragounisSlide 3

LVDS Driver Restrictions

M3 M4

M5 M6

CMFBCMOSdriver

D

D

D

VofsVcm

Vbp

Vbn

5pF

5pF

100k 100k

TX

TX

• Only Thin-Gates Transistors -> max. voltage 1.2-Only Thin-Gates Transistors -> max. voltage 1.2-1.5V1.5V

• Maximum output voltage before current source Maximum output voltage before current source leaves leaves saturation saturation VDD- 250mV VDD- 250mV

• LVDS standard defines a common mode range of 0 LVDS standard defines a common mode range of 0 – 2.4V – 2.4V for the LVDS receiver for the LVDS receiver

A commercial LVDS receiver (e.g. FPGA input) is A commercial LVDS receiver (e.g. FPGA input) is able to able to process the data signal process the data signal


LVDS Receiver Restrictions

M11M12 M13

M14

M8

M9 M10

M4 M5 M6M7

M1

M2 M3

IN1 IN2M14

M15M16

M18M17

OUT

M20M19

M21 M22

Tyhach et al., Tyhach et al., A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface,

IEEE JSSC, Sept. 2005

Rail-to-Rail Input stageRail-to-Rail Input stage max. input voltage limited by VDD max. input voltage limited by VDD

Option1:Option1:

To process standard LVDS signal 1.2V +/- To process standard LVDS signal 1.2V +/- 175mV175mV VDD >= 1.375 V VDD >= 1.375 V

Option2:Option2:

Override Driver Common Mode Voltage Override Driver Common Mode Voltage

Option 3:Option 3:

Use LVDS transceiver chip in test setupUse LVDS transceiver chip in test setup

TX RX

+

-

+

-

Iout


Questions & Answers LVDS 2

Answer: No, because we bias the receiver input (Yes it is Fail-Safe)

Does your receiver reach an intermediate state of high current consumption? ( Is your receiver Fail-Safe?)

Question:


Failsafe-Biasing

RX

+

-

60mV

Maxim Application Note 4007,Maxim Application Note 4007,Robust Fail-Safe Biasing for AC-Coupeled Multidrop LVDS Bus, 2007Robust Fail-Safe Biasing for AC-Coupeled Multidrop LVDS Bus, 2007

• bias voltage close to VDD/2 is defined by resistive bias voltage close to VDD/2 is defined by resistive divider divider

• bias is fed to RX inputs by high ohmic resistorsbias is fed to RX inputs by high ohmic resistors

• additional high ohmic resistor connected between additional high ohmic resistor connected between inverted inverted input & ground introduces voltage difference @ input & ground introduces voltage difference @ inputsinputs


AC Coupled Communication Scheme

TTXX

RRXX

CMOSCMOS

OUTOUT

TX RX

+

-

+

-

Iout

On-Chip

approach allows to study AC-coupled communications scheme approach allows to study AC-coupled communications scheme

DC – Balancing can be achieved by sending commands with wrong DC – Balancing can be achieved by sending commands with wrong chip id chip id & complementary data during command data transmission breaks & complementary data during command data transmission breaks


Self-Biasing of LVDS Receiver

consequence of power-on sequence:consequence of power-on sequence:

LVDS receiver has to be fully functional before the LVDS receiver has to be fully functional before the precise reference circuit is availableprecise reference circuit is available LVDS receiver has to be self biased LVDS receiver has to be self biased

LVDS receiver biasing has to be reliableLVDS receiver biasing has to be reliableR1 R2 R3

START-UP

Vbias

• modified version of low voltage beta-multiplier (M1, R2 & R3 have been added) (Baker, CMOS, 2nd edition, IEEE press p. 629)

• reference current is defined by R1 (R1=R2=R3)

• circuit has only one dominant pole easy to compensate

• addition of transistor M1 gives first order temperature compensation (Friori, A New Compact Temperature compensated CMOS current reference, IEEE Trans. Circ. & Sys., 2005)

• start-up circuit enforces current flow in the circuit and switches off during normal operation


Reference Current vs. Supply Voltage

reference current stays stable for VDD > 1.0


Reference Current vs. Temperature

variation of referene current < 300nA with temperature


Monte Carlo Simulation

Imean=23.7 uA, Isigma=1.3 uA, Imin=17.5uA,Imax=32.5uA


Monte Carlo: RiseTime & Duty Cycle

Slide 12

Rise Time Duty Cycle

Mean:217psSigma:20ps Mean:50.4%

Sigma:0.5%


STATUS: LVDS circuits

OLD

NEW

• Layouts have been adapted to the longer bondpad Layouts have been adapted to the longer bondpad pitch of pitch of production chip (with respect to the test chips) production chip (with respect to the test chips) LVDS driver has now more width & less height LVDS driver has now more width & less height

• Metalization has been changed from LM to DMMetalization has been changed from LM to DM

• Design has been ported fom Tripple-Well to T3 Design has been ported fom Tripple-Well to T3 substrate substrate isolation option isolation option

• LVDS biasing & failsafe circuits designed & layoutedLVDS biasing & failsafe circuits designed & layouted

LVDS driver

Extraction & simulations of parasitics has not been done Extraction & simulations of parasitics has not been done yetyet


0 1 2 3 4 5 6 7 8 9

0 10 20 30 40 50 60 70 80 90 100 110 1200 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9

PROBE

PROBE

PROBE

PROBE

PROBE

5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6

LDOD

VREF

OVERRIDE

DCDC

CAP BOTTOM

DCDC CLK OVERRIDE

PROBE

PROBE

PROBE

PROBE

PROBE

PROBE

DC DC

LDO

D

LDO

A

DCDC

CAP TOP

DCDC

IN

DCDC

OUT&LDOD

IN

LDOD

OUT

LDOA

VREF

OVERRIDE

LDOA

IN

LDOA

OUT

VDDA

VDDD

DCDC-OUT

LDO

GND

LDOA

GND

GND

OFF - CHIP

20mm

PROBE

PROBE

PROBE

PROBE

PROBE

PROBE

PROBE

PROBE

0 1 2 3 4 5 6 7 8 9

0 10 20 30 40 50 60 70 80 90 100 110 1200 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9

PROBE

PROBE

PROBE

PROBE

PROBE

5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6

LDOD

VREF

OVERRIDE

DCDC

CAP BOTTOM

DCDC CLK OVERRIDE

PROBE

PROBE

PROBE

PROBE

PROBE

PROBE

DC DC

LDO

D

LDO

A

DCDC

CAP TOP

DCDC

IN

DCDC

OUT&LDOD

IN

LDOD

OUT

LDOA

VREF

OVERRIDE

LDOA

IN

LDOA

OUT

VDDA

VDDD

DCDC-OUT

LDO

GND

LDOA

GND

GND

OFF - CHIP

20mm

PROBE

PROBE

PROBE

PROBE

PROBE

PROBE

PROBE

PROBE

VDDA1 VDDD1 VDDA2 VDDD2

Pad Frame

50 Power 22 Digital I/O 13 Analog I/O 21 Probe 128 Overall133 Maximum

External power routing Possibility to study different powering schemesPads grouped together to independent supply domains


Bond Pads

• 150um bond pitch

• Two different bond pad sizes 100um x 200um I/O pads 250um x 200um power pads (corresponds to two I/O pads)

• ESD devices, vertical M2 & horizontal M3,MQ,MG supply rail routing below the pad

• Only supply voltage & ground of according supply domain is routed below the pads

• VDDT3 rail is either connected to dedicated pad (digital domain) or shorted to VDD

VDDGND

VDDT3SUB

HBM diodes HBM diodes

CDM diodes

100um

150 um

M3/MQ/MG

INPUTPAD

CORE

OUTPUTPAD

CORE

250 um

POWER PAD

300 um

200 um

RC-Clamp

M3/MQ/MG M3/MQ/MG M3/MQ/MG


Bond Pad Layout

Analog InputPad

SpacerCell

CutCell

120um empty for TSV tests

ESD

• ESD devices are located in upper ESD devices are located in upper part of part of the pad the pad

• lower part has been kept empty for lower part has been kept empty for TSVTSV

• Spacer cells are placed between the Spacer cells are placed between the padspads

• cut cells seperare pads of different cut cells seperare pads of different supply domains & provide bus to bus supply domains & provide bus to bus ESD ESD protection protection


Question & Answer ESD

Answer: Yes, we follow the recommendation of the IBM ESD manual!

Do you follow a dedicated ESD strategy?Question:


VDDD

GNDD

SUB

VDDT3

VDDA

GNDA

ESD strategy

• I/O pads are connected via reverse-biased diodes to the supply rails

• Inputs have seconde diode pair & series resistor limit max. voltage @ gate of transistor

• Reverse biased diodes between VDD & GND rails discharge path from GND to VDD

• RC-Clamp shorts VDD & GND in case of positive going ESD event discharge path from VDD to GND

• Ground busses are protected by antiparallel diodes

RC-Clamp

Ground-to-Supply Discharge

Bus-to-Bus ProtectionInput Pad

Output Pad


Status Padframe

All needed pad types have been developed:

Supply:

Analog VDD

Digital VDD

VDD 3.3V

Wide VDD

GND

Wide GND

Substrate

VDDT3

Digital:

CMOS IN

CMOS OUT

LVDS IN

LVDS OUT

Analog:

Analog IN

Analog OUT

Wide Analog OUT

Construction of pad frame ongoingConstruction of pad frame ongoing


OLD & BACKUP SLIDES


LVDS Chip Submissions

• 21-Jul-2007:21-Jul-2007: first test chip submitted to UMC 130nm via Europractice mini-asic first test chip submitted to UMC 130nm via Europractice mini-asic runrun real hardware test of chosen architecture for use in FE-I4 real hardware test of chosen architecture for use in FE-I4

• 24-Mar-2008:24-Mar-2008: 4 channel LVDS transceiver chip submitted to IBM 130nm (LM) 4 channel LVDS transceiver chip submitted to IBM 130nm (LM) via CERN via CERN for use in a SEU test setup for use in a SEU test setup characterization of new cables and flex types characterization of new cables and flex types

• 15-Sep-2008:15-Sep-2008: LVDS driver with LVDS driver with tristate optiontristate option submitted to IBM130nm (DM) submitted to IBM130nm (DM) via MOSISvia MOSISUMC 130nmUMC 130nm IBM 130nm (LM)IBM 130nm (LM)

0.8mm0.8mm

1.8mm1.8mm

2mm2mm

1.5mm1.5mm

IbnLDO

SHUNTLDO

R

SHUNTLDO

L

TristateLVDS

LDO

10 BIT DAC

IbpD

AC

DO

gndS

ub

gndD

AC

vddD

AC

Iout

DA

C

Iout

DA

Cn

vddI

n

vddI

n

vddI

n

vddI

n

gndL

DO

gndL

DO

gndL

DO

gndL

DO

vref

LDO

vddOut

vddOut

vddOut

vddOut

gndSub

IbnShuldoR

VrefShuldoR

IinShuldo

IinShuldo

IinShuldo

IinShuldo

IoutShuldo

IoutShuldo

IoutShuldo

IoutShuldo

RrefShuldoR

IrefShuldoR

VoutS

huldoR

VoutS

huldoR

VoutS

huldoR

VoutS

huldoR

IrefShuldoL

VoutS

huldoL

VoutS

huldoL

VoutS

huldoL

VoutS

huldoL

IbnShuldoL

VrefShuldoL

IinShuldo

IinShuldo

IinShuldo

IinShuldo

IoutShuldo

IoutShuldo

IoutShuldo

IoutShuldo

RrefShuldoL

gndSub

VDDD

GNDD

CLK

DI

LD

gndSub

gndLvds

vddLvds

IrefLVD

S

VosLV

DS

IbnD

AC

2 mm

2 m

m

TxLV

DS

TxnLV

DS

100 um

162.5 um

IBM 130nm (DM)IBM 130nm (DM)2mm2mm

1.5mm1.5mm


LVDS Transceiver-Chip Test Setup

• 4 x LVDS receiver CMOS output & CMOS input LVDS driver

• Configurable Chain: LVDS receiver LVDS driver

• 2x Type 0 cable adapter: LVDS signal Type 0 cable termination resistor LVDS receiver

Biasing

Type 0 Cable Adapter

Type 0 Cable Adapter

developed by A. Eyring


Measurements LVDS Transceiver Chip

40MHz

160MHz

320MHz

Clock-Rate

Input Common Mode Voltage

1.05V

600mV

150mV

CMOS In CMOS In LVDS TX Out LVDS TX OutLVDS Rx In LVDS Rx In LVDS Tx Out LVDS Tx Out

@ 320 MHz Clock @ 320 MHz Clock

measured by L. Gonella

LVDS RX In LVDS RX In CMOS Out CMOS Out

40MHz

160MHz

320MHz

Clock-Rate

Measurement with active differential probe and 100 Ohm termination resistor on PCB @ 1.2V supplyMeasurement with active differential probe and 100 Ohm termination resistor on PCB @ 1.2V supply

Increased biased currents needed for LVDS RX to operateIncreased biased currents needed for LVDS RX to operate@ high frequences & low common mode voltages@ high frequences & low common mode voltages


LVDS Transceiver-Chip Eye Diagram

Test-Setup includes:• One – 4 meter twisted pair 36 AWG wire

(0.127 mm copper diameter)• 160 Mbps data rate• Eye pattern is 317mV, need > 200mV• No errors @ 150 Mbps or 350 MbpsError rate

better than 2*10-13 @ 350 Mbps

50 OHM

TEST CHIP LVDS DRIVERXILINX DEVELOPMENTBOARD - ML405

100 OHM4 METER TWISTED PAIR 36-AWG

COPPER80 OHM

50 CM PPA-0 FLEX100 OHM

HRS DF30CONNECTOR

IBL DATA TRANSMISSION TEST SETUP

LVDS RECEIVER

CMOSDRIVER

M. Kocian, D. Nelson, Su Dong SLAC

350Mbps without cable 160Mbps with cable


CMOS Input & Output Buffers

developed by D. Gnani

Schmitt-Trigger with 200mV hysteresis

• Cascoded structures have higher snapback voltage

• Have been used in LVDS-Transceiver chip

Vin

Vout

M8

M1

M2

M3

M4

M5

M6

M7Vin

M2

M1Vout

M4

M3

M6

M5

M7

M10

M8

M9

Input Buffer

Output Buffer

PADFRAME Michael Karagounis. 03.11.2009 FE-I4 Review - Padframe - Michael Karagounis Questions &...

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