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LICENTIATE T H E S I S

Department of Computer Science, Electrical and Space EngineeringDivision of EISLAB

Design of Time-to-Digital Converter Circuits for 3D

Time-of-Flight Measurements

Muhammad Tanveer

ISSN 1402-1757ISBN 978-91-7439-923-3 (print)ISBN 978-91-7439-924-0 (pdf)

Luleå University of Technology 2014

Muham

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ISSN: 1402-1757 ISBN 978-91-7439-XXX-X Se i listan och fyll i siffror där kryssen är

Design of Time-to-DigitalConverter Circuits for 3D

Time-of-Flight Measurements

Muhammad Tanveer

Department of Computer Science, Electrical and Space EngineeringLulea University of Technology

Lulea, Sweden

Supervisors:

Jonny Johansson, Johan Borg

Printed by Luleå University of Technology, Graphic Production 2014

ISSN 1402-1757 ISBN 978-91-7439-923-3 (print)ISBN 978-91-7439-924-0 (pdf)

Luleå 2014

www.ltu.se

To my family and friends

iii

Abstract

The three-dimensional view of the world is something that we often take for granted, aphenomenon that has proven challenging for machine vision applications in which de-scription of the environment requires the relative position and motion of different objectsin the scene. Currently, range imaging (RIM) measurements are based on digital imagingtechnology and are merged with the ability to measure the distance to the correspondingobject point in each pixel. The distance measurement is based on either the direct orindirect time-of-flight principle. The distance to the corresponding object point in eachpixel is directly correlated with time-resolved imaging concerning the measurement ofthe photon arrival time. This time-resolved image generates a distance image by usingthe direct time-of-flight technique. This distance image is much more useful than an or-dinary picture in regard to measuring and controlling anything, including in the processindustry, obstacle detection for automotive safety, navigation, and path planning.

The time resolved imaging system consists of two essential building blocks: 1) aphoton detector capable of sensing single photons and 2) a fast time resolver or time-to-digital converter that can measure the time of light to picosecond resolution. To addressemerging applications, a miniaturized time resolver with acceptable performance anda low cost must be designed that could be integrated with an array of single photondetectors. The goal of this thesis is therefore to investigate, design, and layout a time-to-digital converter to achieve an acceptable cm-level resolution for a range of 10-15 meters.

In this thesis, two ideas have been selected for investigation based on their appealingattributes, including their improved resolution, area, and power consumption: 1) anon-pixel time stretcher based on analog time expansion and 2) the combination of theon-pixel time stretcher with a global gated ring oscillator-based time-to-digital converter.Both ideas have been used in conjunction to demonstrate a new architecture for a time-to-digital converter for 3-D time-of-flight measurements. The time stretcher uses analoguetime expansion, where the time interval to be measured is stretched by a factor k. Thisis achieved by charging a capacitor with a constant current I, followed by dischargingthe capacitor by a current I

k. To achieve an acceptable linearity and constant current

generation, wide swing cascode current source/sinks have been used. An idea to buildprecisely matched current mirror as a time stretcher has also been addressed. The finaltime-to-digital conversion is performed by the gated ring oscillator-based time-to-digitalconverter. The multiphase gated ring oscillator, which is the heart of TDC, is capable ofmeasuring the stretched time interval by counting the full clock cycles and determiningthe timing positions within the clock cycle.

v

The work has been discussed in light of the previous research by designing circuits,performing layouts, simulating and conducting parasitic extractions in a 0.35 μm CMOSprocess. Based on simulations and results, a prototype of an integrated TDC can bebuilt to achieve a cm-level distance error.

vi

ContentsPart I 3

Chapter 1 – Thesis Introduction 5

1.1 Aim and scope of this work . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Contribution and contents of this work . . . . . . . . . . . . . . . . . . . 7

Chapter 2 – Optical TOF Range Measurement 9

2.1 Optical range measurement techniques . . . . . . . . . . . . . . . . . . . 10

2.2 Interferometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Triangulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Time-of-flight distance measurement . . . . . . . . . . . . . . . . . . . . 11

2.5 3D time-of-flight ranging . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 3 – High-Resolution TDC Architectures 17

3.1 Clocked delay lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Vernier delay lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3 Time-to-amplitude converters . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4 Time stretchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.5 Gated ring oscillator-based TDC . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 4 – Time-to-Digital Converter Performance Parameters 25

4.1 Time resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Maximum range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3 Non-linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4 Conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5 Power consumption and silicon area . . . . . . . . . . . . . . . . . . . . 27

Chapter 5 – Time stretcher-based TDC 29

5.1 TDC architecture selection . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 GRO-TDC and sub-circuits . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3 Timing signal interpolation . . . . . . . . . . . . . . . . . . . . . . . . . 33

Chapter 6 – Summary of Appended Papers 35

Chapter 7 – Conclusion and Future work 37

7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.2 Further work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

vii

References 39

Part II 45

Paper A 471 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Time stretcher based on a Miller-integrator . . . . . . . . . . . . . . . . . 523 Open-loop integration based time stretcher . . . . . . . . . . . . . . . . 534 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Paper B 591 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 The Architecture of Proposed Time-to-Digital Converter . . . . . . . . . 633 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Paper C 771 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 A current mirror-based time stretcher . . . . . . . . . . . . . . . . . . . . 803 Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 The high swing cascode current mirror . . . . . . . . . . . . . . . . . . . 855 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

viii

Acknowledgements

During the course of this research, I have had the pleasure of working with many skilled,professional people who have helped and supported me. I would like to express my grat-itude particularly towards my academic supervisors at Lulea University of Technology,Sweden and Oulu University of Technology in Finland, whose experience, knowledge, andsound advice were, and always will be, the underlying foundation of this work. Outsidethe electronic engineering environment, the solid support of my family and friends hasbeen vital and has given me the strength to see it through to a logical conclusion. In theirown unique way, and in no particular order, I will always be indebted to Johan Borg,Jonny Johansson, Juha Kostomowara, Kalevi Hyyppa, Ilka Nissinen, and Jan Nissinen.However, of particular importance to me has been the friendship, freely granted knowl-edge and skills of Tomas Linder, Sarfraz Iqbal, Johan Carlson, Andreas Nilson, BlerimEmuruli, Erica Svanstorm, and Rumen Kyusakov.

ix

Abreviations

2D 2-Dimensional3D 3-DimensionalADC Analog-to-Digital ConverterCMOS Complementary Metal Oxide SemiconductorD-TOF Direct Time-of-FlightDR Dynamic RangeDNL Differential Non-LinearityFF Fill FactorGRO Gated Ring OscillatorI-TOF Indirect Time-of-FlightINL Integral Non-LinearityLSB Least Significant BitMMV Monostable Multi VibratorRIM Range Imaging MeasurementSNR Signal-to-Noise RatioTAC Time-to-Amplitude ConverterTDC Time-to-Digital ConverterTOF Time-Of-FlightTIM Time Interval MeasurementTS Time Stretcher

1

Part I

3

Chapter 1

Thesis Introduction

The three-dimensional view of the world is something that we often take for granted,a phenomenon that has proven challenging for machine vision applications in whichtraditional image sensors often provide a flat, two-dimensional view of the world. In3D cameras, an image of a scene generates a distance image by using the time-of-flighttechnique [1]. The distance image is much more useful than an ordinary picture inregard to measuring and controlling anything, such as in the process industry. In recentyears, considerable research has been reported and is in progress in the area of chip-baseddistance measurement cameras to improve the performance in terms of range and distanceerror [1][2][3]. The continuous progress and emergence of new applications for acquiringdepth data have surpassed the capabilities of the existing products and technologies, bycommanding attributes such as higher accuracy, precision, reduced time of acquisition,smaller size, and lower cost. Laser scanners also use time-of-flight technology, but they arebased on the rotational mechanics of scanning scenes in one or two dimensions [4]. Chip-based 3D cameras offer basic signal processing in each pixel by offering the advantage ofa lack of moving part and by being more compact and less expensive than laser scanners[5].

The main emphasis of this work is on the analysis, architectures, and design of circuitsfor 3D TOF (time-of-flight) measurements, that can be implemented as an integrated cir-cuit, using low-power and low-cost CMOS technology. The 3D measurement technologycalled TOF has been around for a long time and is used for measurements over long andsmall distances, down to cm-level distance error. It, however, evolved drastically overthe last decade. The scanner-less 3D TOF imaging sensor is composed of an array ofphoto detectors (pixels) and is capable of measuring the TOF required by a light pulseto travel from the light source to the target and back to the sensor. The revolutionaryaspect is its ability to use an array of sensors/imaging sensors so that the 3D images canbe taken simultaneously and at a high speed. Previously, it was limited to measurementat one point, and the entire image was drawn by using expensive, heavy, and movingobjects, such as mirrors or prisms.

5

6 Thesis Introduction

Camera systems transfer information via photons and need a lightning source. Passivelight sources have problems with sunlight, darkness, glare, and poor signal-to-noise ratios[6]. With active illumination, such as a laser, one can synchronize this illumination withthe camera by using a narrow wavelength range, and further robustness could be achievedby using a custom optical filter. To achieve cm-level distance measurement error withinthe required measurement range, the light source must acquire ultra-fast rise time of apulse, in the order of 100 ps, and high optical power [6].

The solid state range sensor that constitutes the core of the measurement systemconsists of two parts: an array of photodetectors and a time interval measurement unit.The performance of both building blocks plays a significant role in the achievement ofminimum distance and depth error. Recent research in this area has proven that photoncounting techniques that use single photon avalanche diodes are favorable because oftheir achievable sensitivity, fast response, and ability to be integrated in standard CMOSprocesses [7][8][9].

1.1 Aim and scope of this work

A complete analysis of the precision and accuracy of these diverse 3D range measurementsystems remains an unsolved task. Precise understanding of integrated circuits for 3DTOF camera, and more specifically the TIM (time interval measurement) unit, is needed.This thesis can be understood as a compilation of new techniques for the design ofintegrated circuits for 3D time-of-flight cameras. The specific questions investigated inthe appended papers are as follows:

• Do circuit techniques exist that could minimize the impact of quantization andmismatch error in integrated circuit elements of state-of- the-art TDCs to improvethe resolution?

• Is it possible to design and elaborate an architecture for a high-resolution, compact,and low-power time-to-digital converter for a 3D TOF camera aimed at cm-leveldistance error with a dynamic input range of 10-15 m?

• Is it possible to design and characterize precisely matched circuits for better lin-earity based on analogue time expansion that can be used in conjunction with atime-to-digital converter to achieve better resolution?

To answer these questions, analogue circuits have been designed and used to cre-ate on-pixel analogue electrical storage. The phenomenon of time stretching has beeninvestigated by cascading it with a time-to-digital converter. In this context, specialinterest is given to the influencing parameters and performance metrics, such as linearityand system optimization. The goal is to design a time interval measurement unit as anintegrated circuit with on-pixel analogue electrical storage. The presented results and in-vestigation will help in better understanding and characterizing circuits for time intervalmeasurement for a 3D time-of-fight camera.

1.2. Contribution and contents of this work 7

1.2 Contribution and contents of this work

Given the aim of the thesis as set out above, its main contribution is the design and anal-ysis of techniques for on-pixel analogue electrical storage and analogue time expansionbased on time stretching and time-to-digital conversion. The other contribution of thisthesis work is the design and implementation of a multiphase gated ring oscillator-basedtime-to-digital converter architecture, the basic frequency of which is used to calculatethe full clock cycles elapsing between the timing signals. Additionally, the position of thetiming signals within the clock period is determined by storing the state of phases of thegated ring oscillator for each timing signal. Thus, the stretched time interval obtainedcan be measured with improved resolution.

This work is structured as follows. This introduction is followed by an overview ofthe basic principal and specific techniques used for optical range measurement and 3Drange imaging camera technologies in chapter 2. In chapter 3, a review of the commontypes of time interval measurement systems used is presented, along with their meritsand demerits. This review also includes proposals that aim at the same goals pursuedin this work. Chapter 3 also presents design and evaluation of the techniques based onthe time stretcher and sub-circuits that could be used in conjunction with time-to-digitalconversion. Chapter 4 present a general overview of the characterization metrics of thetime-to-digital converters. The proposed design, a time stretcher-based TDC, has beenpresented in chapter 5. This chapter also explain an architecture, that has been designedand implemented for time-to-digital conversion based on a gated ring oscillator. Chapter6 presents a summary of the appended papers. This work closes with conclusions, and abrief outlook is given with respect to the future development of this technology.

8 Thesis Introduction

Chapter 2

Optical TOF Range Measurement

The TOF measurement system already exists in nature’s navigation solutions, e.g.,dolphins and bats use such a sensor system for both navigation and object tracking(hunting). Moreover, humans have also used TOF technique for a long time, but mostof these methods are based on the propagation time of sound [10]. This chapter focuseson the basic principles of optical range measurement techniques. These techniques workwith light, i.e., electromagnetic radiation fields in the wavelength range of 400-1000 nano-meters (visible and near infra-red spectrum). A rough description of each principle, alongwith some advantages and disadvantages of each, is presented with some examples. Deepinsight and broader knowledge about these principles can be found in [11]. Figure 2.1shows the family tree of contactless 3D range measurement techniques.

Contactless 3D shape Measurements

Light Wavesλ= 0.5-1 μm

(300-600 THz)

Microwavesλ= 3-30 mm

(10-100 GHz)

Ultrasonic Wavesλ= 0.5-1 μm(0.3-3 MHz)

Triangulation

Depth detection by means of geometrical angle measurement

Interferometry

Depth detection by means of optical coherent time-of-flight measurement

Time-of-flight (TOF)

Depth detection by means of optical modulation time-of-flight measurement

Active Triangulation Passive Triangulation

Direct (Pulsed)

Indirect (pulsed or CW)

Figure 2.1: Family tree of contactless 3D range measurement.

9

10 Optical TOF Range Measurement

2.1 Optical range measurement techniques

TOF measurement, the basic principle of this work, is discussed in more detail. Adiscussion and comparison of different ranging techniques are presented. Due to theapplication-specific advantages of microwave and ultrasound techniques and diffractionlimitations, they are not included in this comparison. Interferometry which is applica-ble predominantly in highly accurate measurements ( λ

100to λ

1000) over small distances,

ranging from micrometers to several centimetres, lies outside the scope of this work. Therequirements of a particular application determine the suitability of each technique, in-cluding the range to be measured, minimum distance error, acquisition time, cost, andwhether absolute or relative measurements are required. The applications of interest forthis project are typically in the range of 10-15 m and require an absolute measurementmade with cm-level distance error. Low cost and low power are important factors thatcan allow the sensor to be used in a wide range of applications.

2.2 Interferometry

Interferometry measures the runtime difference between a reference and a measurementpath. In this technique, the superposition of two monochromatic waves with amplitudea1, a2 and phase φ1, φ2 result in another monochromatic wave of the same frequency, butwith different phase φ3 and different amplitude a3 [12]. The movement of a measurementobject towards or away from the interferometer generates intensity peaks each time theobject is moved by a multiple of λ

2. This movement can be recovered by counting the

number of minimum and maximum transitions with an accuracy of approximately λ. Theusage of light’s wavelength as a distance measurement is the major drawback because, theambiguity interval is limited to λ. Enhanced interferometers use multiple wavelengthsto solve this problem. The basic application for interferometry is the highly accuratemeasurement over small distances (micrometers to several centimeters) [12].

2.3 Triangulation

In this technique, a scene is viewed from multiple viewpoints in the form of stereo-vision,together with the depth of focus system. This method is very well known and consideredthe basis for human depth perception [13][14][15]. Triangulation is a geometric approachin which a triangle is formed between two known reference points and the unknown objectposition. The distance of the target can be determined by measuring the triangle’s angleor the triangulation base. As shown in Figure 2.2, if a point is observed from two differentsites, A and B, of known distance x, by measuring the viewing angle α and β with respectto AB, the observed point distance can be calculated using the following equation:

2.4. Time-of-flight distance measurement 11

z =x

1

tanα+

1

tanβ

. (2.1)

Because each point to be measured must be taken from both viewing positions un-ambiguously, passive triangulation techniques require a scene with high contrast. Stereovision is one famous 3D realization of passive triangulation that uses at least two camerasto observe the scene from different angles [16][15]. Hence typical object features are foundand compared in both images using 2D-correlation. From the position of each feature’scentroid in both separate images, the angles α and β can be deduced, and the distancecan be calculated using equation 2.1, assuming that the distance of the cameras withrespect to each other, as well as their orientation, is known. In triangulation techniques,computational effort and shadowing effects are some typical problems. Additionally, costand overall system size are also major drawbacks of triangulation systems.

�� tan1

tan1

x = z�

? = z

xA B

Object

� �

Figure 2.2: Basic principle of triangulation-based range finding.

2.4 Time-of-flight distance measurement

An absolute distance can be measured if we are able to measure the absolute time thata light pulse needs to travel from the target to the reference point, the detector [15].The distance measurement is possible because we know the speed of light very precisely:c = 3 × 108 ms−1. The basic principle of a TOF ranging system is illustrated in Figure2.3. A source emits a light pulse and starts a highly accurate stopwatch. The lightpulse travels to the target and back. The reception of the light pulse by the detectormechanism stops the stopwatch, which determines the time of flight of the light pulse.As the light pulse travels the distance twice (back and forth), a measured time of 6.67ns corresponds to a distance of one meter [17]. To achieve a distance error of 1 cm,time measurement accuracy of better than 70 ps is required [17]. The most essential


Figure 2.3: Basic principle of an (optical) TOF ranging system.

properties are that the active light source (emitter) and detector be synchronous, verycompact and are located very close to each other. This provides a significant advantageover triangular-based ranging systems, which suffer from shadowing effects.

The basic challenge of establishing a TOF ranging system is the realization of a highlyaccurate time mechanism system, i.e., the focus of this report, which is discussed in moredetail in chapter 3. The laser scanners used for 3D measurements are mostly bulky andsensitive to vibrations. The TOF ranging systems use pulsed modulation, or continuouswave modulation (CW), as a light source [15]. Both modulation principles have theirown advantages and disadvantages, which have been briefly discussed.

2.4.1 Pulsed modulation

The most obvious method of operating a TOF system is pulsed modulation because timeof flight is measured directly, as illustrated in Figure 2.4. The final time estimation isperformed by correlating a start and stop signal with a parallel running time intervalmeasurement unit that is usually known as a time-to-digital converter. Pulsed lightoperation offers the advantage and possibility of transmitting a high amount of energyin a very short time [6]. Thus, the influence of background illumination can be reduced,and a high short-term optical signal-to-noise ratio (and signal-to-background) ratio canbe attained while maintaining a low mean value of optical power. The basic problem isthe inexact measurement of light pulse return, due to light scattering [15]. Additionally,it is difficult to produce very short light pulses with fast rise and fall times, which canensure an accurate detection of the incoming light pulse [6]. The low repetition ratescan also drastically restrict the frame rate for TOF scanners. Nevertheless, due to theconsiderable advantages concerning the signal-to-background noise ratio, most of today’sTOF range finders are operated using pulsed modulation [6].

2.4. Time-of-flight distance measurement 13

Figure 2.4: Pulsed wave modulation-based concept.

2.4.2 Continuous wave modulation

To alleviate some of the requirements of pulsed modulation, continuous wave modulationhas been developed [15]. In this technique, the round-trip of light is not measureddirectly, but two modulated light signals are used. A continuous wave modulation-basedsensor generally has two accumulation regions in each pixel to demodulate the signal[18]. Generally, the phase difference between the sent and received signals is measured,rather than directly measuring a light pulse’s turn-around time. Because the modulationfrequency is known, the measured phase directly corresponds to the time of flight, whichis the quantity of interest. Compared with pulsed modulation, a variety of light sourcescan be used for this mode of operation because extremely fast rise and fall times are notrequired. Different shapes of signals are possible, including sinusoidal waves or squarewaves. The main disadvantage of this technique is noise; integration over time is requiredto reduce noise that limits the frame rate and cause motion blur [19].

Figure 2.5: Continuous wave modulation-based concept.


Sensor Control and Interface

3D Data Output

Emitter Trigger

Modulated/Pulsed LED / LASER Source

Optical diffuser

Collection lens

TOF SensorTime resolved pixel

z

(a)

(b)

(c)

(d)

(e)

Target

Figure 2.6: Components of 3D Time-of-flight based depth camera system.

2.5 3D time-of-flight ranging

A new emerging technology that has alleviated the scanning mechanism of a laser beam byserially acquiring data point-wise is 3D TOF ranging [20][3]. In a 3D TOF system, one canilluminate the entire scene with a light source to perform simultaneous depth capture and3D measurement of an entire scene, as shown in Figure 2.6. This, however, necessitatesthe use of [20] (a) a modulated light source in the infra-red part of the spectrum tomake the illumination unobtrusive; a pulsed laser with an ultra-fast rise time and highoptical power can usually be used; (b) an optical diffuser, to achieve a flood illuminationover the wide field of view; (c) the collection lens, to gather and focus the back-reflectedlight echo from the target on-to the sensor focal plane using an optical objective; (d) asolid-state image sensor, composed of a 2D array of photo-detectors, preferably SPADs(single photon avalanche diodes), due to their extremely high sensitivity, capability todetect down to a single photon, with intrinsic low noise performance, and are capableof measuring the TOF needed by the light source to the target and back to the sensor;and (e) finally, the sensor interface to provide the sensor power supply, required biasingvoltage/current signals, digital control phases, and data stream read out from the sensor[3]. The SPADs need to be coupled with proper time processing high-speed circuitry,which would also occupy space and thus lower the device’s crucial optical fill factor [20].In an optical measurement system, the light travels at a speed of 3 × 108m

s; hence, the

measurement of propagation delay over short ranges requires very high-speed circuitry,which is a formidable challenge and the aim of this thesis, as discussed in chapters 3, 4,and 5 in detail.

2.6 Discussion

Basic optical measurement principles have been introduced in previous sections to gain acomparative insight. Figure 2.7 shows a comparison of these implementations in terms ofthe distance range and uncertainty distance error. As in triangulation, the measurement

2.6. Discussion 15

Figure 2.7: Performance map of conventional optical 3D measurement systems [21].

range and distance errors are determined by the triangulation baseline. Miniaturizationof the complete system leads to a reduced triangulation baseline and, therefore, affectsmeasurement uncertainty. The measurement uncertainty in interferometry is given bythe wavelength of the employed coherent light source, which cannot be influenced sub-stantially.

The TOF techniques has shown amazing expansion in recent years, and the nextthree to five years will demonstrate the potential of this technology [20]. They have notonly become cheaper, smaller, and simpler to realize, but their distance error uncertaintyalso improve steadily. The most obvious reason is that when decreasing the minimumfeature size or gate delay, the devices become faster, thus, a better time resolution ispossible. It is believed that TOF measurement will be one of the emerging technologiesused in future applications. D-TOF (direct time-of-flight) is commonly addressed forsingle-point range systems [20]. In scanner-less TOF systems, complexities still exists inthe implementation of a pixel-level sub-nanosecond electronic stopwatch. This techniqueis particularly suitable for SPAD-based TOF systems [20]. This thesis focuses on thedesign of sub-nanosecond stopwatch TDC (time-to-digital converter) in chapters 3, 4,and 5. For an efficient SPAD sensor operating in D-TOF mode, a time stamp mustbe generated for every impinging photon at every pixel detector [20]. This requires thecoupling of per-pixel time digitization circuitry and high-speed array readout, which posesseveral challenges in terms of area, power, and fill-factor compared with single channelarchitectures, as discussed in the literature [22][23].

One of the key components of a 3D TOF system is the per-pixel timing circuitry andglobal TDC that can simultaneously measure the time intervals between a common startsignal from pulsed laser and multiple stop signals from the 2D detector array [23][24].The emphasis in this work has been on developing a time digitization circuit architecturethat is feasible to implement as an integrated circuit using low-cost CMOS technology.The achievable resolution should depend not on the inherent propagation delay of thelogic gates but on the design mechanism. Chapter 3 compares and presents circuit design


mechanisms that may be suitable for the implementation of time-digitization circuitrywith acceptable resolution for 3D TOF system.

Chapter 3

High-Resolution TDCArchitectures

Accurate time interval measurement has played a significant role in the development ofscience throughout history, from analog clocks based on solar motion and water flow to themost accurate cesium resonator available today [25]. The time interval measurement orTDC (time-to-digital converter), has had significant applications in experimental physics[26], including nuclear physics research, measurements of mean lifetime, and particleidentification, where time-of-flight requires a precise TDC integrated circuit [26]. Today,TDC continues to play a significant role in emerging applications, such as time-of-flightrange finders and perception or depth-based 3D TOF cameras [22][23][24]. In 3D TOFcameras, the accurate measurement of the time of the arrival of photons requires theintegration of on-pixel time digitization circuitry [20]. The TDC allows for the precisemeasurement of the time difference between two signal events, start (synchronous withthe light source) and stop (back reflected photons), and then outputs a digital result.

Many TDC architectures have been developed, most of which target specific appli-cations as stand-alone custom integrated circuits; thus, the requirements on their areaand power consumption are quite relaxed [27][28][29]. However, the fabrication of anarray of pixels with TDC has strict demands in terms of geometric fidelity, power con-sumption, and homogeneity in performance [22][23][24]. The design approach for a TDCmay be categorized either as evaluating a time resolution based on the minimum gatedelay available in the target manufacturing process or as using some innovative tech-nique to achieve sub gate-delay resolution. These approaches have their own strengthsand weaknesses. The nature of construction of most of the potential TDC architecturesis based on standard cell blocks, but the design and layout of the converter for on-pixeltime digitization must be addressed as full custom designs and cannot be synthesizedusing automated techniques. To achieve a monotonic and linear transfer characteristic,the design needs to be symmetric and parasitically balanced. The next sections reviewsome of the previously published architectures.

17

18 High-Resolution TDC Architectures

DffD

Qclk

+

DffD

Qclk

DffD

Qclk

Delay Delay Delay

Start

Stop Out

Reg Reg Reg

1

1

1

0

0

�qT Delay � (Varies due to

mismatch)

Out

Start

Stop

inT

stopT

Figure 3.1: Clocked delay line based TDC.

3.1 Clocked delay lines

The clocked delay line is the most basic TDC architecture, comprising a chain of inverterelements into which a start pulse is injected [30][31][32]; it works by effectively countingthe number of sequential inverter delays that occur between two rising signal edges, asshown in Figure 3.1. More precisely, the rising edge of the start signal that represents thefirst event is delayed by a series of inverter gates (ignoring the polarity throughout forsimplicity), each with a delay of Tq. The outputs from each of these inverters are inputsto a register, which is clocked with the rising edge of the stop signal that represents thesecond event. The register output is a thermometer code that corresponds to the numberof delay elements that have transitioned within the measurement interval Tin.

The clocked delay line architecture offers a simple TDC with moderate performance,but a limitation that must be considered is the high cost of increasing its range [32].The increase in the dynamic range of a clocked delay line TDC needs a linear increasein the number of delay elements, which increases the power consumption and decreasesthe maximum sampling rate. For example, for a 10 bit TDC, over a thousand flip flopsand inverters are required. The impact on the layout is high, and linearity is heavily im-pacted by the delay line matching errors. Additionally, the flip flop based TDC circuitshave a critical metastability issue, which results in incorrect output coding if set-up andhold time parameters of every flip flop are not properly followed to ensure operationalconsistency. Another major weakness of this circuit is that the delay through the inverterchain is sensitive to process, supply voltage, and temperature dependent variations. Itrequires the additional implementation of compensation circuitry to correct these varia-tions through a calibration technique. In this technique, the chain of delay elements isembedded with a delay locked loop (DLL) structure [33][34][35], as shown in Figure 3.2,derived from standard phase lock loop (PLL) techniques [36], which further complicatesthe circuit; this technique is thus not feasible for on-pixel array-based architecture.

3.2. Vernier delay lines 19

DffD

Qclk

DffD

Qclk

DffD

Qclk

Delay Delay Delay

Start

Stop

Reg Reg Reg

DffD

Qclk

Reg

Delay

Phase Detector Charge Pump

0Q 1Q2Q nQ

Figure 3.2: DLL base clalibration concept for clocked delay lines.

3.2 Vernier delay lines

The Vernier delay line technique has been adapted for improving the resolution of digitalCMOS TDCs and has been widely documented in literature [37][26][38]. In a simpleexample of Vernier delay lines, two buffer-based delay lines are used with slightly differentunit delays. The basic idea is to stretch the input time interval Tin by delaying both thestart and stop signals with delay chains. With the start signal edge transiting the upperdelay line, the stop signal is presented to the lower, faster delay line, as shown in Figure3.3. The stop signal with the faster delay line gradually catches up with the start signal,as in a Vernier Gauge. As a result, the effective resolution of the Vernier TDC is evaluatedas the difference of the two delays, or, more specifically, Tq = Delay1 −Delay2.

In this design, the layout related effects have an impact on linearity; additionally,calibration and counting circuitry require further silicon area, as reported [38]. There isalso a need for thermometer binary decoder, which results in large area usage, making itimpossible for this technique to be used for array-based implementation.

DffD

Qclk

+

DffD

Qclk

DffD

Qclk

Start

Stop Out

Reg Reg Reg

21q DelayDelay=T �

Start

Stop

inT 1Delay

11

10

0

Out

2Delay

2Delay 2Delay 2Delay

1Delay 1Delay 1Delay

Figure 3.3: Vernier delay line based TDC.


TACresetV

tacCtacI

tacV

t

samplet

� tactacresettac t/C.IV=V �

ADC

System Clock

Coarse Clock

Start

Figure 3.4: Time to amplitude conversion based TDC.

3.3 Time-to-amplitude converters

The time-to-amplitude conversion approach is based on the charging and discharging ofa capacitor with a constant current during the time interval to be measured. The voltagechange in the capacitor is converted to a digital word by an analogue-to-digital converter(ADC) [39][40][41][42][43] (Figure 3.4). In this technique, charge is either drained from acapacitive store or accumulated on-to it for a certain period of time. The resultant voltageis then fed to a flash ADC, where a fine TAC is combined with a coarse clock counter tocreate the full output word. TAC can be susceptible to the impact of kT

Cand power supply

noise, but the implementations also show some interesting performance advantages. Forexample, they can be implemented in a compact and power-efficient manner, which isappealing for the array-based implementations. The conversion capacitance Ctac (Figure3.4) behaves as static memory, which can be useful for pipelined readout and real-timeconversion. They possibly tend to have better linearity compared with their digitalcounter-parts because there is nothing to mismatch; all timing information is stored inthe capacitor [43].

3.4 Time stretchers

Instead of using different mechanisms to minimize the time delay through delay elements,to enhance the TDC resolution, an equivalent or even better effect may be obtained byamplifying or stretching the input start-stop time difference by a known factor just be-fore digital conversion. Only a couple time stretching mechanisms have been reportedin the literature [41][44][45][46], which suggests that this area could be investigated andexploited further. The time stretchers not only inherit some appealing properties of theTAC conversion technique, as discussed in the previous section but they also use ana-logue time expansion, where the time interval to be measured during time to amplitudeconversion is stretched by a factor k depending on the circuit parameters. The expandedtime interval thus obtained can be measured by any TDC with improved resolution.

3.4. Time stretchers 21

1T 2T 4T3T

stretchClk

Pulse

Synchronized pulse

Integrator voltage

Output to TDC

Figure 3.5: The time stretcher or time amplification concept for TDC.

In this topology, a capacitor is charged with a constant current during the time intervalmeasurement and is then discharged with a much smaller current. The ratio between thecharge and discharge current is the stretch factor k. Using an appropriate stretch factorthat must be large enough, a counter-based TDC can be used to measure the discharge(stretched) time interval and thus obtain the original time measurement with improvedresolution. Figure 3.5 presents the timing diagram of a time stretcher where start andstop time are separately measured in relation to a reference clock, and the number ofclock cycles elapsing from one measurement to the other is also recorded as

k =T3 − T2

T2 − T1

. (3.1)

These techniques can be suitable for array-based implementations because of theirachievable high resolution and compact area implementation, but sensitivity to the in-jected noise in the integrating node or non-linearity of the capacitor remains to be inves-tigated. The noise sensitivity can be reduced through the use of two identical capacitors,

CCI k.I

reset

start

stop

same

start stop same t

Q

Figure 3.6: Time stretcher differential concept.


which are than discharged by different currents when the start and stop signals arrive[47]. A comparator identifies the moment when the voltages on the two capacitors areagain the same, as shown in Figure 3.6. The differential architecture seems to be very in-sensitive to supply noise, but it occupies more area and dissipates more power, if targetedfor array-based implementations. Nevertheless, both differential and single ended havedemanding requirements for the comparator in terms of offset and propagation delay.

3.5 Gated ring oscillator-based TDC

Figure 3.7 illustrates the concept of GRO-TDC (gated ring oscillator-based time-to-digital converter) [48][49][50][51], which is similar to the basic cyclic oscillator-based TDC,where it measures the number of delay element transitions during a measurement timeinterval [52][53][54]. In this architecture, instead of long delay lines with a large numberof delay elements, a reduced number of inverters are configured as a ring oscillator,with the final stage output fed back as an input. The key innovation in the gated ringoscillator is that instead of enabling the counters during the measurement time interval,the ring oscillator is seeded with an initialization pulse/condition that is allowed to starttransiting down the oscillator. A counter is incremented when the pulse completes a fullcircuit of the ring. On the arrival of the stop condition, the output word is a combinationof the counter value and the interpolation states of internal nodes of the ring that haveactually transitioned in the clock cycle.

The gated ring oscillator based TDC (GRO-TDCs) have several desirable performancecharacteristics [55]. Because the state of the oscillator is preserved between measure-ments, the residue error occurring at the end of the given measurement interval can bescrambled and transferred to the next measurement interval, resulting in a first-ordernoise shaping operation [50]. Additionally, with first-order noise shaping of quantizationerror, the delay element mismatch can be made first-order-shaped and can be realizedby the sequencing of delay elements for successive TDC conversions, as shown in Figure

Enable

Out

CountersReset

+Registers

Count

Gated Ring Oscillator Enable

Enable

Enable

Enable

Measurement 1

Measurement 2

Measurement 3

Measurement 4

Figure 3.7: (a) Gated ring oscillator based TDC (left) (b) Barrel shift algorithm concept forfirst order noise shaping (right).

3.5. Gated ring oscillator-based TDC 23

3.7. The concept of the well-known barrel-shift algorithm has also been shown, wheremismatch errors from one sample can be passed and subtracted from the following sam-ple. Using this type of oversampling, one can expect that a GRO-TDC architecture canachieve high resolution without calibration, even in the presence of mismatch.

This architecture has fewer metastability issues and performs the conversion in realtime. However, to achieve the smallest gate delay and best time resolution, the single-ended configuration might be preferable to the differential one because, the error fromthe differential non-linearity is first-order-shaped and the single-ended topology has halfthe power and area [53]. Additionally, the power consumption of the GRO-based TDCis appealing for multiple converter systems coping with sparse events (e.g., array-based),because it tends to peak only when the ring oscillator is in operation. For the rest ofthe time, the consumption is dominated by leakage; hence, scalable low average powerconsumption with overall system activity is achievable. This approach can yield a com-pact layout compared with delay line based designs, but to achieve good linearity, carefulbalancing of parasitic capacitances between the ring oscillator elements is needed, partic-ularly at the feedback point. This architecture contains most of the appealing attributesthat could be implemented for array-based systems to achieve acceptable performance.The rationale behind the selected choice and reviewed architectures is summarized inTable 3.1.

TDC Resolution/ Accuracy/ Conversion Power AreaArchitecture Dynamic Precision rate consumption /Scalability

Clk’d Delayline

calibrationpossible metastability,

matchingissues

fixedconstant large,does

not scalewell

Vernier De-lay Line

calibrationpossible metastability,

matching

fixed highdoes notscale well

Time-to-AmplitudeConverter

depends onADC bits

acceptablenon-realtime

lowv-large,does notscale well

TimeStretcher can be very

highimprovedresolution

non-realtime

lowscales well

Gated RingOscillator

minimumgate delay

jitter a con-cern real time low, average small, scales

well

Table 3.1: TDC metrics and Logical reasoning behind TDC architecture selection.

Chapter 4

Time-to-Digital ConverterPerformance Parameters

In a time-correlated imaging system, a significant function of the time-to-digital con-verter is to measure the time differences between an illumination event to a target surfaceor reflected light with a minimum level of uncertainty because it corresponds to respec-tive distance error. Similar to TDC architecture, the main parameters that are usedto measure the performance are time resolution, maximum range, linearity (accuracy),precision, conversion speed, area, and power consumption. The input to the TDC is acontinuous time signal, and the output are digital codes. Due to the influence of mis-match, noise, and non-linearities in the design, the real transfer curve deflects from theideal curve and generates quantization errors, as shown in Figure 4.2. The followingrelation describes the measured time and output digital codes [56].

Tin = TLSB ·k=n−1∑k=0

Dk · 2k. (4.1)

Here, Tin is the measured time interval between Start and Stop, and TLSB is the minimumunit of time measurement. n and D represent the number of bits and the digital codesof the TDC outputs, respectively.

4.1 Time resolution

The time resolution of the TDC is the minimum value of the time span that can beresolved or measured. The key design parameter depends not only on the circuit charac-teristic and noise, but also on the minimum process gate delay. To measure a range TR,with N bits, the resolution can be given as

Tbin =TR

2N. (4.2)

where Tbin represents the bin size of the TDC [56].

25

26 Time-to-Digital Converter Performance Parameters

Figure 4.1: Basis of time-to-digital conversion [56].

4.2 Maximum range

The maximum range of the TDC is architecture dependent and has a direct impact onthe area and power consumption. The maximum range is also related to the width, interms of the number of bits of the converter output data word, and can be expressed bythe relation

TMAX = 2N · TLSB. (4.3)

Here, TMAX denotes the maximum range that can be measured, and N is the number ofbits of the TDC outputs [56]. In the field of TDC, the maximum range is occasionallyreferred as dynamic range (DR). For example, a 10 bit TDC with a time resolution of100 ps would have a maximum possible dynamic range of 102.4 ns.

4.3 Non-linearity

The non-linearity of the TDC characterizes how closely the converted result matches theknown real value. The conversion linearity over the full dynamic range of TDC, expressedin terms of differential and integrated non-linearity, demonstrates the deviation from theknown real value in the same way as for ADCs. The differential linearity is defined asthe difference between each code step from its ideal value, namely TLSB, and is given as

DNLi = Ti − TLSB. (4.4)

where DNLi is the ith value of differential non-linearity and Ti is the width of ith step in

the real transfer curve. Practically, a DNL of less than ±0.5 LSB over the full maximumrange of the converter ensures a monotonic transfer function with no missing codes.

Integral non-linearity can be expressed over the converter full maximum range as thedeviation of a converter’s transfer function between the actual value and a straight linedrawn either as best fit or from the converter’s beginning to its end-points. It can beexpressed as a deviation of the step position from its ideal value of one TLSB [56] andevaluated using the expression

4.4. Conversion rate 27

INLi =i−1∑n=0

DNLi. (4.5)

4.4 Conversion rate

The conversion rate of a TDC is the rate per second at which the converter returns themeasured result. Based on different architectures and application requirements, someTDCs can perform measurements very quickly in real-time, whereas in some cases, thereexists a need to exercise the full-scale dynamic range. It also impacts on power consump-tion.

4.5 Power consumption and silicon area

The power consumption of a TDC is considered for a defined input time interval, or apercentage of a full-scale dynamic range. The power consumption profile can also bearchitecture or application-dependent, i.e., it can be continuous or exhibit peaks duringthe conversion cycle.

Additionally, the silicon area is an important parameter for array-based TDC ar-chitectures. It has a direct impact on the fill-factor of the device. The image sensorfill-factor is defined as the ratio of the light sensitive area versus total area of the pixel,and it is heavily influenced by the actual architecture and the minimum feature size ofthe manufacturing process.

28 Time-to-Digital Converter Performance Parameters

Chapter 5

Time stretcher-based TDC

The goal of this work is to design a time-to-digital converter with an acceptableresolution that can be integrated as a CMOS chip for the first prototype of a 3D time-of-flight camera. Figure 4.1 shows a simplified illustration of the concept and the timingdiagram to motivate the discussion in the coming sections. The radiation from the pulsedlaser diode illuminates the target surface and sets the start timing mark. The reflectedphotons from the target surface are absorbed by single-photon avalanche diodes and setthe stop timing mark. Meanwhile, a capacitor is charged from the rising edge of the startsignal to the rising edge of the stop signal with a constant current. This analog electricalstorage is then discharged with a much smaller current to achieve an appropriate analogtime expansion. The rising edge of the comparator determines the start timing markfor the gated ring oscillator, and falling edge of the comparator will determine the stoptiming mark for the gated ring oscillator based time-to-digital converter. This stretchedtime interval can be measured by counting full clock cycles and registering the states ofan interpolation with improved resolution.

source

SPAD

Start

Stop

refV

Comp REGISTER

Stop

Start

Start-GRO

Stop-Stretch SERIAL OUTPUT

Counter state GTDC

Interpolator state GTDC

REGISTER

Photons

Photons Time StretcherTime

Capacitor Voltage

Timing logic Stop-Stretch

STRETCH TIME

CLK

Start-GRO

TDC-Stop

Stop-inp

COUNT countTInp-stopcountstretch TT T ��

Inp-stopT

Figure 5.1: Time-of-flight distance measurement system with per-pixel time stretcher, GlobalTDC, and timing diagram.

29

30 Time stretcher-based TDC

5.1 TDC architecture selection

The measurement of a time interval with picosecond-level resolution is a big challenge.The conception of time stretching, or time domain amplification, seems to be an effectivesolution; however, the circuit techniques for time amplification are still under-developed[56]. Based on the appealing attributes of the time stretcher and the gated ring oscillator-based TDC [56], an architecture has been selected in which the time stretcher and TDChave been implemented in conjunction to achieve better performance. The simplifiedarchitecture of the time-stretcher based GRO-TDC is illustrated in Figure 5.2. Thefunction of the time stretcher can be considered similar to the pre-amplifier in front-endelectronics. The behaviour of the TS (time stretcher) is given as

Tout = kTS · Tin, (5.1)

where Tin and Tout are the input and output time intervals and kTS is the gain of the timestretcher. If the TDC core is a GRO-TDC, the relationship between the digital outputsof the TDC core and Tout is given as

Tout = Tbin ·k=n−1∑k=0

Dk2k, (5.2)

where Tbin is the bin size of the GRO-TDC, Dk is the digital bit, and n is the number ofbits for the digital outputs. For the time stretcher, we can use equations 5.1 and 5.2 toderive an expression for the time stretcher-based TDC:

Tin =Tbin

kTS

·k=n−1∑k=0

Dk.2k. (5.3)

This equation depicts that the performance of the time stretcher-based TDC dependson both the high-linearity gain of the TS and the precision of the TDC core. Theoretically,

TDC Core

inT outT

011…..010

A

B

oB

oATime words

TS

Figure 5.2: Time stretcher-based TDC.

5.2. GRO-TDC and sub-circuits 31

1st Stop

Start-GRO

Stop-GRO

Final Stop Comparator output

DffD Q

EA

GRO

Registers

8 bit CounterCDES

P1 (reference_Clk)

TDC_Stop

Start

Start-GRO TDC-Stop

1st Stop

End of measurement

cycle

Start

EN / EN

On-chip Global TDC

p1 p2 p3 p4 p5 p6 p7 p8 p9

inp1 inp2 inp3 inp4 inp5 inp6 inp7 inp8 inp9

Stop_q1

b0b1b2b3b4b5b6b7

clk

Enable=1

Start-GRO

TDC input Logic

EA

EN-GRO

EN-GRO

TDC-Stop

Comparator output

Inp3= Select

Time-Stretcher Comparator

Interpolator result

On-chip (in each pixel)

MMV +

EA

Off-chip for test purpose

Figure 5.3: Time-of-flight distance measurement system concept with multiple stop-signals (asdetector matrix).

the conception of time amplification or time stretching can be applied to femto-seconds-level time measurement [56]. This architecture has been chosen for design and simulationas a part of this research work.

Figure 5.3 presents the conceptual block diagram of a time-of-flight distance mea-surement system, where multiple-stop signals can be considered a stop timing mark froma detector matrix. The TDC consists of time stretchers, a comparator, a nine-phasegated ring oscillator, TDC input logic, a timing signal synchronization scheme, registersto store the timing positions within the clock cycle, and a ripple counter for counting fullclock cycles. The on-pixel time stretcher involves two conversions: time to voltage andvoltage to time. The final conversion is performed by a gated ring oscillator-based TDC.The on-pixel analogue voltage is created by charging a capacitor Cconv, during the mea-surement time interval with a constant current. Cconv is then discharged with a fractionof the charging current to the achieve analogue time expansion by the phenomenon oftime stretching. The stretched analogue based time is then converted to digital domainby using a continuous time comparator. The functionality, design, and analysis of eachindividual block are discussed in detail in the papers appended to this thesis.

5.2 GRO-TDC and sub-circuits

Apart from the time stretcher’s requirements of high linearity, and the comparator offset,propagation delay, reliable recording of the timing signal through the counter dual-edgesynchronizer, the gated ring oscillator is considered the heart of the system. It defines thekey performance metrics of the converter; including the time resolution, linearity, powerconsumption, and robustness to power supply variations. The reference clock from thegated ring oscillator is responsible for incrementing the state of the ripple counter, and


Enabled Ring Oscillator Disabled Ring Oscillator(a) (b)

p1 p2 p3 p4

p5p6p7p8p9p9

M2

M3

M4

M1

p1

Enable / EnableEnable

Enable

(c)

0.4 / 0.35 um

0.8 / 0.5 um

Figure 5.4: (a) Enabled GRO (b) Disabled GRO (c) Nine phase GRO.

interpolation is performed to determine the timing position within the clock cycle. Figure5.4 illustrates the practical implementation of gating a ring oscillator using switches. Thegating functionality is added to the conventional inverter-based ring oscillator, with anodd number of stages, by placing two switches in series with a positive and negativesupply of each inverter, where they all share a common state. When the switches areclosed, oscillation is enabled, and it behaves identically to a classical ring oscillator.Conversely, when the switches are open, the oscillation is suspended because the inverterdelay element is unable to charge or discharge the parasitic output capacitance, as shownin Figure 5.4. In this way, during the disabled state, the oscillator phase at the endof the enabled state is held with the charge stored in the parasitic capacitance of delayelements. In this design, an odd number of stages, i.e., all of the nmos switches, arecontrolled by an Enable signal; similarly, all of the pmos switches are controlled by anEnable. Referring to Figure 5.4, the GRO structure only allows the oscillator to performtime interval measurement when it is gated ON by Start-GRO from the rising edge ofthe comparator (Figure 5.3), and it strives to freeze when the time interval measurementhas been made (on the falling edge of the comparator).

The gating of the ring oscillator can offer the advantage of intrinsic scrambling of itsquantization and mismatch error such that the residue occurring at the end of a givenmeasurement interval can be transferred to the next measurement interval. For example,we can write

Tstart[k] = Tstop[k − 1]. (5.4)

If continuous time interval measurements are performed, the above-mentioned featurecan be used to evaluate the overall quantization error of the time interval measurement,and given as

Terror[k] = Tstop[k]− Tstart[k] = Tstop[k]− Tstop[k − 1], (5.5)

where Tstart and Tstop are the start time interval and stop time intervals and k representsthe overall number of measurements. These equations illustrates that Tstop[k] corresponds

5.3. Timing signal interpolation 33

to the first-order noise shaping in the frequency domain.Figure 5.4 shows a simplified schematic of the gated ring oscillator. The W/L is

chosen as a trade-off between the operating current and gate capacitance to achieve theshortest propagation delay. For a 3.3 V core digital supply, the minimum propagationdelay of this element after post layout simulation is≈844 ps. In this design, a single-endednine-stage ring is constructed. It results in an Enable state maximum supply current ofapproximately 62.56 μA being drawn, and the maximum duration drawn current is equalto the frequency of the system stop signal. Additionally, the ring oscillator layout designis critical to the timing resolution and power consumption of the converter. The linearityof the TDC is dependent on the careful balancing of the parasitic capacitances (≈1.72 fF)between each stage. In this design, the oscillator has been laid out in a ring shape, andnon-matched parasitic capacitance is balanced using metal wire. Extracted simulationshave been performed to check for balanced parasitic capacitances at each stage.

5.3 Timing signal interpolation

In the design of the GRO-TDC, the resolution is limited by the gate delay of the tech-nology used. The gate delay is determined from the load capacitances at the outputnode and the driving capability of the buffers used in the gated ring oscillator design.The frequency of ≈ 131 MHz is achieved from the post layout simulations of GRO us-ing a compact structure and minimizing parasitic capacitances at the output node andmaximum width-to-length ratio of buffers to meet the power consumption requirements.The timing signal interpolation is used to obtain better resolution by storing the timingpositions within a clock cycle in the interpolation registers. In this work, the outputsof a single-ended gated delay elements are used as timing signal interpolators. This re-sult is stored in interpolation registers, which are than clocked by the TDC-Stop signalfrom the counter dual-edge synchronizer block. The LSB of the nine-phase gated ringoscillator-based TDC and timing signal interpolator can be derived as

LSB =TCLK

NM, (5.6)

where TCLK presents the period of the gated ring oscillator, and N and M are thephases of the gated ring oscillator and the timing signal interpolator, respectively. Atiming diagram illustrates the principle of using the timing signal interpolator for thestart-GRO signal, as shown in Figure 5.3. The reference CLK is the one phase of thenine-phases (GRO phases) that are used for the counting full clock periods.

Chapter 6

Summary of Appended Papers

Paper A: An Analogue Time Stretcher for a 3D Time of Flight Camera

This paper compares two specific circuit techniques to realize a time stretcher in CMOStechnology. The time stretcher is based on the analogue time expansion technique, wherethe time interval to be measured is stretched by a factor k and can be realized with currentintegration. This type of time stretcher can be used as a time domain amplifier to improvethe precision of the time to digital conversion. A comparison is made between a Millerand an open-loop integrator-based time stretcher with respect to the available linearity,power consumption, and circuit area. The simulations show that the open loop approachwith carefully optimized circuit configurations may lead to a compact and low-powersingle-photon avalanche diode pixel configuration with the required time amplificationproperty. In open-loop integration approach, a wide swing cascode current source/sinkis used as a time stretcher. The application field for the techniques studied in this workis the on-pixel-based time interval measurement unit in 3D time-of-flight cameras basedon a 2D single-photon avalanche diode array.

The author’s contribution was designing the circuit of the time stretcher, creatingthe schematics, and post layout simulations, analyzing and investigating the encounterednon-linearity errors to select an acceptable approach for further integration, and writingthe main part of the manuscript.

Paper B: Time-to-Digital Converter based on Analogue Time Expansion fora 3D Time of Flight Camera

This paper describes the architecture and performance of a time-to-digital converter im-plemented by cascading a time stretcher and a gated ring oscillator-based time-to-digitalconverter (GRO-TDC). The time interval to be measured is stretched by a factor k bycharging a capacitor with a current I, followed by discharging the capacitor by I

k. Time

stretching involves dual conversions: time to charge and charge to time. Whereas, theseare performed in each individual pixel, the final time to digital conversion is performed

35

36 Summary of Appended Papers

by the global GRO-TDC, where a multiphase gated ring oscillator is used to measurethe stretched time interval by counting full clock cycles and storing the states of a ringoscillator to achieve increased resolution. Additionally, emphasis is placed on high lin-earity gain, the time stretcher, precision of the time-to-digital converter, and possiblelimitations. The phenomenon of time stretching can be exploited further with the avail-able circuit configurations to obtain simulation results to design a compact, low-powertime-to-digital converter for 3D time-of-fight cameras.

The author’s contribution was to investigate, draw, and implement a suitable archi-tecture for the time-to-digital converter, using the phenomenon of time stretching, thatcould be integrated later with more electronics to build the first prototype of a 3D time-of-flight camera. The contribution also involves design of schematics and post layoutsimulations with parasitic extraction to verify the performance of the TDC system. Theauthor has also written the entire manuscript.

Paper C: Time Stretcher for a Time-to-digital Converter with a PreciselyMatched Current Mirror

This paper describes an effective method and specific circuit technique that can allowthe precise determination of the stretch factor for a time stretcher. The time stretcheris based on current mirror and precisely matched current sinks with an improved layoutrealization for current mirror matching. This idea is investigated, realized, and evaluatedfor use in conjunction with time-to-digital converter system, with its main focus on thereduced complexity and possible achievable accuracy of stretched time in the aspects ofdistance error. The ratio of the current between the current mirror and the current sinksis 1:k. k represents an appropriate stretch factor that can be achieved with preciselymatched current sinks. This stretched time interval can be realized by a time-to-digitalconverter with improved resolution. This design is validated through simulations in 0.35μm CMOS process technology.

The author’s contribution was to investigate and implement the idea of current mirrormatching to address possible achievable calibration for the magnitude of the stretchfactor. The contribution also involves design of schematics and post layout simulationswith parasitic extraction to verify the alignment and precision of stretch factor. Thedesign constraints have been investigated to validate the circuit implementation. In thismanuscript, the main part has been written by the author, but co-authors were alsoinvolved in the logical and mathematical formulations.

Chapter 7

Conclusion and Future work

7.1 Conclusion

The required property of time stretching, based on analogue time expansion, along withpossible suitable architectures for time-to digital conversion has been investigated inthis thesis. The properties of time stretching and precise time-to-digital conversion cansignificantly improve the achievable time resolution and, thus reduce the distance errorfor 3D time-of -flight cameras.

The research question Q1 was as follows: Do circuit techniques exist that couldminimize the impact of quantization and mismatch error in integrated circuit elementsof state-of- the-art TDCs to improve the resolution?

Yes, To improve the resolution of the time-to-digital converters for 3D time-of-flightcameras, the concept of time stretching can be an effective solution. The circuit tech-niques for time stretching are still under development, and the idea can give a newresearch direction for TDC techniques. A comparison has been made between conven-tional Miller integrator-based time stretcher and simpler wide swing cascode currentmirror-based time stretcher. The simulations results from both designs have provencomparable, with the wide swing cascode current mirror being more compact, low-powerand simpler.

The research question Q2 to investigate was as follows: Is it possible to design andelaborate an architecture for a high-resolution, compact, and low-power time-to-digitalconverter for a 3D TOF camera aimed at cm-level distance error with a dynamic inputrange of 10-15 m?

Yes, This thesis has presented an architecture for the performance of a time-to-digitalconverter implemented by cascading a time stretcher and a gated ring oscillator-based

37

38 Results and Discusion

time-to-digital converter (GRO-TDC). Whereas, the time stretching is performed in eachindividual pixel, the final time to digital conversion is performed by the global GRO-TDC,where a multiphase gated ring oscillator is used to measure the stretched time interval bycounting full clock cycles and storing the states of a ring oscillator to achieve increasedresolution. The phenomenon of time stretching is exploited with the available circuitconfigurations, and the obtained simulation results shows that it is possible to design acompact, low-power time-to-digital converter for 3D time-of-fight cameras.

The research question Q3 was as folllows: Is it possible to design and characterizeprecisely matched circuits for better linearity based on analogue time expansion that canbe used in conjunction with a time-to-digital converter to achieve better resolution?

Yes, This thesis has presented a method that can allow precise determination ofthe stretch factor for a time stretcher based on precisely matched current mirrors andcurrent sinks with an improved layout realization. Additionally, analytical expressionsfor the requirements on output impedances and mismatch of the current mirrors havebeen derived that allow optimal design specifications. The ratio of the current betweenthe current mirror and the current sinks is 1:k. k represents an appropriate stretch factorthat can be determined by the number of precisely matched current sinks. This stretchedtime interval is later measured by a time-to-digital converter with improved resolution.

In conclusion, different circuit techniques have been investigated through analysis,design, and simulations for time-to-digital conversion. From the discussion and results,it is obvious that the concept of on-pixel time stretching and time-to-digital conversionusing a gated ring oscillator has the potential to yield an optimized implementation foran array-based design with improved resolution.

7.2 Further work

The phenomenon of time stretching can be further exploited by implementing a small(8X2) array of on-pixel time stretchers, where the SPADs function as basic detector ele-ments for high sensitivity and ultra-fast response. This SPAD-based time stretcher arraycan be integrated with a GRO-TDC for time-to-digital conversion to achieve improvedresolution for 3D range measurements.

References

[1] Ouk Choi Radu P Horaud Miles Hansard, Seungkyu Lee. Time of Flight Cameras,Principles, Methods, and Applcaitions. Springer, New York, 1st edition, 7 December,2012.

[2] Zanuttigh Pietro Cortelazzo Guido M Dal Mutto, Carlo. Time of Flight Camerasand Microsoft Kinect. SpringerBriefs in Electrical and Computer Engineering, NewYork, 1st edition, 24 January, 2013.

[3] Peter Seitz and Albert J. P. Theuwissen. Single-Photon Imaging. Springer, NewYork, 1st edition, 2011.

[4] Norbert Pfeifer and Christian Briese. Laser-scanning principles and applications.

[5] Febio Remondino and David Stoppa. TOF Range-Imaging Cameras. Springer,London, 2013.

[6] Lauri W Hallman, Kimmo Haring, Lauri Toikkanen, Tomi Leinonen, Boris S Ryvkin,and Juha T Kostamovaara. 3 nj 100 ps laser pulses generated with an asymmetricwaveguide laser diode for a single photon avalanche diode time-of-flight rangefinderapplication. IOPSCIENCE, Measurement Science and Technology, 2012.

[7] Niclass C, Favi C, Kluter T, Gersbach M, and Charbon E. A 128x 128 single photonimage sensor with column level 10 bit time to digital converter array. Solid-StateCircuits, IEEE Journal of, 2008.

[8] Cristiano Niclass, Kota Ito, Mineki Soga, Hiroyuki Matsubara, Isao Aoyagi, SatoruKato, and Manabu Kagami. Design and characterization of a 256x64 pixel singlephoton imager in cmos for a mems-based laser scanning time of flight sensor. OpticsExpress, 2012.

[9] Veerappan C, Richardson J, Walker R, Li DU, Fishburn MW, Stoppa D, BorghettiF, Maruyama Y, Gersbach M, Henderson R.K, Bruschini C, and Charbon E. Char-acterization of largescale non-uniformities in a 20k tdc spad array integrated in a130nm cmos process. In Solid-State Device Research Conference (ESSDERC), 2011Proceedings of the European.

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[12] P. Hariharan. Optical Interferometry. Elseveir, San Diego, 2nd edition, 2003.

[13] Close Range Photogrammetry and Machine Vision. Whittles, 2001.

[14] J Clark and A. M. Wallace. Depth sensing by variable baseline triangulation. InProceedings of BMVC 1995.

[15] T.C Strand. IBM Research Laboratory. Optical three dimensional sensing for ma-chine vision. Optical Engineering, 1985.

[16] Joaquim Salvi, Jordi Pag’es, and Joan Batlle. Pattern codification strategies instructured light systems. Elsevier, 2004.

[17] Ilkka Nissinen and Juha Kostamovaara. A 2-channel cmos time-to-digital converterfor time-of-flight laser rangefinding. In Instrumentation and Measurement Technol-ogy Conference, 2009, IEEE.

[18] R. Schwarte H, Heinol Z. Xu, and K. Hartmann. An new active 3d-vision systembased on rf-modulation interferometry of incoherent light. In Proc. SPIE 2588, In-telligent Robots and Computer Vision XIV: Algorithms, Techniques, Active Vision,and Materials Handling.

[19] Mario Frank. Denoising of continuous-wave time-of-flight depth images using confi-dence measures. Technical report, Department of Computer Science, ETH Zurich.

[20] TOF Range Imaging Cameras. Springer, 2013.

[21] Principles of 3D imaging Tecniques, in Handbook of Computer Vision and Applica-tions. Academic Press, 1999.

[22] Cristiano Niclass, Claudio Favi, Theo Kluter, Marek Gersbach., and Edoardo Char-bon. A 128 x 128 single-photon image sensor with column level 10 bit time-to-digitalconverter array. IEEE Journal of Solid-State Circuits,, 2008.

[23] Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, , and Satoru Kato. A 100m-range 10-frame/s 340x96-pixel time-of-flight depth sensor in 0.18I1

4m cmos. In ES-

SCIRC (ESSCIRC), 2011 Proceedings.

[24] Niclass C, Favi C, Kluter T, Gersbach M, and Charbon E. A 128x128 single-photonimager with on-chip column-level 10b time-to-digital converter array capable of 97psresolution. In Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Tech-nical Papers. IEEE International.

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[25] L. ESSEN and J. V. L. PARRY. An atomic standard of frequency and time interval:A cAsium resonator. Nature, 1955.

[26] Porat Dan I. Review of sub-nanosecond time-interval measurements. In NuclearScience, IEEE Transactions on.

[27] Raisanen-Ruotsalainen, Elvi Rahkonen T, and J. Kostamovaara. An integratedtime-to-digital converter with 30-ps single-shot precision. Solid-State Circuits, IEEEJournal of, 2000.

[28] Mantyniemi A, Rahkonen T, and Kostamovaara J. A high resolution digital cmostime-to-digital converter based on nested delay locked loops. In Circuits and Sys-tems, 1999. ISCAS ’99. Proceedings of the 1999 IEEE International Symposium on.

[29] Karadamoglou K, Paschalidis N.P, Sarris E, Stamatopoulos N, Kottaras G, andPaschalidis V. An 11-bit high-resolution and adjustable-range cmos time-to-digitalconverter for space science instruments. Solid-State Circuits, IEEE Journal of, 2004.

[30] Staszewski RB, Vemulapalli S, Vallur P, Wallberg J, and Balsara P.T. 1.3 v 20 pstime-to-digital converter for frequency synthesis in 90-nm cmos. In Circuits andSystems II: Express Briefs, IEEE Transactions on.

[31] Bailly P, Chauveau J, Genat JF, Huppert JF, Lebbolo H, Roos L, and Zhang Bo.A 16-channel digital tdc chip. In Nuclear Science Symposium, 1998. ConferenceRecord. 1998 IEEE.

[32] Gogaert S and Steyaert M. In Solid-State Circuits Conference, 1995. ESSCIRC ’95.Twenty-first European.

[33] Rahkonen T.E and Kostamovaara Juha T. The use of stabilized cmos delay lines forthe digitization of short time intervals. Solid-State Circuits, IEEE Journal of, 1993.

[34] Ljuslin C, Christiansen J, Marchioro A, and Klingsheim O. An integrated 16-channelcmos time to digital converter. In Nuclear Science, IEEE Transactions on.

[35] Mota M and Christiansen J. A four-channel self-calibrating high-resolution time todigital converter. In Electronics, Circuits and Systems, 1998 IEEE InternationalConference on.

[36] Arai Y and Ikeno M. A time digitizer cmos gate-array with a 250 ps time resolution.Solid-State Circuits, IEEE Journal, 1996.

[37] Dudek P, Szczepanski S, and Hatfield J.V. A high-resolution cmos time-to-digitalconverter utilizing a vernier delay line. In Solid-State Circuits, IEEE Journal.

[38] Rahkonen T, Kostamovaara J, and Saynajakangas S. Time interval measurementsusing integrated tapped cmos delay lines. In Circuits and Systems, 1989., Proceed-ings of the 32nd Midwest Symposium.

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[39] Stoppa D, Borghetti F, Richardson J, Walker R, Grant L, Henderson RKand Gers-bach M, and Charbon E. A 32x32-pixel array with in-pixel photon counting andarrival time measurement in the analog domain. In ESSCIRC, 2009. ESSCIRC ’09.Proceedings.

[40] Young-Ho Lee, Dae-Wook Kwon, Jong-Wan Seo, Ki-Min Lee, Baeg M.H, Seung-HoBaeg, and Tae-Yong Kuc. A new design of interpolator for time to digital converter.In Automation and Logistics (ICAL), 2010 IEEE International Conference.

[41] Raisanen-Ruotsalainen, Elvi Rahkonen T, and Kostamovaara J. A time digitizerwith interpolation based on time-to-voltage conversion. In Circuits and Systems,1997. Proceedings of the 40th Midwest Symposium.

[42] Simpson MLand Rochelle J.M. Current-mode time-to-amplitude converter for pre-cision sub-nanosecond measurement. In Nuclear Science Symposium and MedicalImaging Conference, 1992., Conference Record of the 1992 IEEE.

[43] Raisanen-Ruotsalainen, Elvi Rahkonen T, and Kostamovaara J. A high resolutiontime-to-digital converter based on time-to-voltage interpolation. In Solid-State Cir-cuits Conference, 1997. ESSCIRC ’97. Proceedings of the 23rd European.

[44] Richard Sumner and George Blanar. New techniques for measuring time intervalswith very high resolution. In AIP conference proceedings 1997.

[45] Abas AM, Bystrov A, Kinniment D.J, Maevsky OV, and Russell G. Yakovlev A.V.Time difference amplifier. In Electronics Letters.

[46] Sumner R. and Blanar G. A self calibrating high resolution common stop timedigitizer circuit. In Nuclear Science Symposium, 1997. IEEE.

[47] Raisanen-Ruotsalainen, Elvi Rahkonen T, and Kostamovaara J. An integrated time-to-digital converter with 30-ps single-shot precision. Solid-State Circuits, IEEE Jour-nal, 2000.

[48] Yu Mingyan, Zong Shixin, Tang Xiaochen, and Wang Yongsheng. A temperaturestabilized multi-path gated ring oscillator based tdc. In Computer Science andInformation Processing (CSIP), 2012 International Conference.

[49] Vengattaramane. K, Borremans J., Steyaert M., and Craninckx J. A gated ringoscillator based parallel-tdc system with digital resolution enhancement. In Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian.

[50] Brandonisio F. and Kennedy MP. First order noise shaping in all digital plls. InCircuits and Systems (ISCAS), 2011 IEEE International Symposium.

[51] Brandonisio F and Maloberti F. An all-digital pll with a first order noise shapingtime-to-digital converter. In Circuits and Systems (ISCAS), Proceedings of 2010IEEE International Symposium.

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[52] Nissinen I and Kostamovaara J. Time-to-digital converter based on an on-chip volt-age reference locked ring oscillator. In Instrumentation and Measurement TechnologyConference, 2006. IMTC 2006. Proceedings of the IEEE.

[53] Nissinen I, Mantyniemi A, and Kostamovaara J. A cmos time-to-digital converterbased on a ring oscillator for a laser radar. In Solid-State Circuits Conference, 2003.ESSCIRC ’03. Proceedings of the 29th European.

[54] Rivoir J. Statistical linearity calibration of time-to-digital converters using a free-running ring oscillator. In Test Symposium, 2006. ATS ’06. 15th Asian.

[55] Ping Lu, Ying Wu, and Andreani P. A 90nm cmos digital pll based on vernier-gated-ring-oscillator time-to-digital converter. In Circuits and Systems (ISCAS),2012 IEEE International Symposium.

[56] Integrated High-Resolution Multi-Channel Time-to-Digital Converters (TDCs) forPET Imaging, chapter 16. InTech, 2011.

44 References

Part II

45

Paper A

An Analogue Time Stretcher for a3D Time of Flight Camera

Authors:Muhammad Tanveer, Johan Borg, Juha Kostamovaara, and Kalevi Hyyppa

Reformatted version of paper originally published in:Proceedings of the 2012 International Conference on 3D Converged IT and Optical Com-munications (3DOC 2012)

c© 2012, Future Technology Research Association International (FTRA), Korea Infor-mation Technology Convergence Society (KITCS) Reprinted with permission.

47

An Analogue Time Stretcher for a 3D Time of Flight

Camera

Muhammad Tanveera, Johan Borga, Juha Kostamovaarab, and Kalevi Hyyppaa

a Department of Computer Science, Electrical and Space EngineeringLulea University of Technology, SE-971817 Lulea

[email protected] Department of Electrical EngineeringUniversity of Oulu, FIN-90014, Finland

Abstract

The analogue time expansion technique, where the time interval to be measured isstretched by a factor k, can be realized with current integration. This kind of timestretcher can be used as a time domain amplifier to improve the precision of the timeto digital conversion. Two specific circuit techniques have been investigated for therealization of a time stretcher in a CMOS technology. A comparison has been madebetween a Miller and an open-loop integrator based time stretcher with respect to theavailable linearity, power consumption and circuit area. The simulations show that theopen loop approach with carefully optimized circuit configurations may lead to a compactand low power single photon avalanche diode pixel configuration with the required timeamplification property. The application field for the studied techniques in this work isthe on-pixel-based time interval measurement unit in 3D time-of-flight cameras based ona 2D single photon avalanche diode array.

Keywords: Time to digital converter, 3D time of flight camera, time stretcher, wide swingcascode current source/sink, analogue time expansion, single photon avalanche diode,open-loop integration

1 Introduction

Two dimensional solid-state image sensors can only capture the two-dimensional pro-jection or image intensity map of a scene, discarding all information regarding distanceto different areas of the scene. In contrast, three dimensional image sensors attempt tomeasure this distance by using time of flight. This time of flight is related to the illu-mination of flash from the camera to the scene and back to the camera. Time resolvedimage sensors offer great potential for the development and automation in machine visionwhere it is needed to extract the distance information of the objects in the scene [1]. In

49

50 Paper A

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Figure 1: Time-of-flight distance measurement system using a per pixel time stretcher and aGlobal TDC

3D TOF cameras time information is processed from each pixel to compute the distanceinformation [2]. The aim of this work is to develop a low power on-pixel time stretcherto improve the precision and to simplify the measurement of the arrival times of themeasured pixel responses. It is believed that the proposed pixel architecture results inlow overall power consumption and high integration level in parallel array architectures,especially for portable devices.

Due to high propagation velocity of electromagnetic waves such as light, very hightime resolution is required. As a reference, the distances 1 cm and 20 m corresponds to 67ps and 133 ns [3]. Time interval measurement methods are reported by using techniqueseither digitally, analogically or by interpolation depending on the targeted application [3][4]. The proposed analogue time expansion technique is based on a current integrationtechnique where the time interval to be measured is stretched by a known factor k [5].The time stretching method is known for its good achievable resolution as reported innuclear physics experiments, and in precision laser ranging systems for space applications

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1. Introduction 51

[6] [7]. The expanded time interval thus obtained can be measured by a global on-chipTDC with improved resolution [8]. The time stretching method involves two conversions:time to charge and charge to time. Whereas these are performed in each individual pixel,the final time to digital conversion is performed by the global TDC.

Fig. 1 shows a simplified front-end circuit of the concept for a 3D TOF camera.Radiation from a pulsed laser diode with ultra fast rise time will illuminate the sceneand set a start timing mark for the time measurement. The reflected photons absorbedby a single photon avalanche diode (SPAD) operating in the Geiger mode may triggera current avalanche [9]. This avalanche current is quenched by using appropriate quen-ching techniques i.e., active quenching, passive quenching or mixed active and passivequenching and a digital pulse is generated that will set a stop timing mark [9].

In a time-stretcher a capacitor is charged from the rising edge of the start timing markuntil the rising edge of the stop mark with a constant current. This analogue electricalstorage is then exploited as a time stretcher based on the analogue time expansion wherethe charged capacitor is then discharged with a much smaller current. This discharge(stretch) time interval can be measured by an on-chip multiphase ring oscillator basedTDC by counting full clock cycles and storing the states of the ring oscillator with-in theclock period to obtain improved resolution.

In this work two types of time stretchers have been investigated and compared interms of linearity, stability, power consumption and compactness to select a suitable timestretching approach for further integration with the on-chip TDC. The first time stretcheris based on an opamp Miller-integrator and the second one is a wide swing cascodecurrent source/sink based on open loop integration. They are presented in sections 2 and3 respectively.

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Figure 3: Simplified schematic of Miller-integrator based time stretcher, and transient simula-tion.

52 Paper A

2 Time stretcher based on a Miller-integrator

The Miller-integrator based time stretcher works on the principle of current integrationwhere the conversion capacitor, located in the feedback path of an operational amplifier,is charged by a constant current from the rising edge of the Start signal until the risingedge of the Stop signal. As the feedback keeps the voltage across the current source,the output impedance is (ideally ) unimportant. After integration, the capacitor is dis-charged with a much smaller current to exploit the idea of analogue time expansion withan appropriate stretch factor.

2.1 Conversion stage and time stretching

The conversion stage generates a linearly increasing voltage across the conversion capaci-tor, directly proportional to the Start-Stop interval, charging the capacitor with constantcurrent I1. The conversion capacitor is then discharged with the current I2 by the start-stretch signal where I1/I2 = k. A simplified schematic of analogue part of time stretcherand simulations are shown in Fig. 2 and Fig. 3 respectively. The time stretching opera-tion can be divided into four parts:

• During the idle state the time stretcher is ready to accept a new Start signal:Start-Stop signals are low, the analogue gate is on creating a low resistance pathin parallel with the conversion capacitor. The charging current I1 passes theanalogue gate without charging the capacitor. Vref (e.g 300 mV) is the initial valueof the time proportional output voltage that can be generated by a temperaturecompensated reference circuit.

• The idle state is followed by the conversion state at the arrival of the Start signal,in this state the Stop signal is still low, for the duration of this state the constantcurrent I1 charges the capacitor. The value for the conversion capacitor is selectedto 300 fF as a trade-off between SPAD and time stretcher area, considering fillfactor and performance. The voltage across the capacitor increases linearly with32 mV/ns rate. The constant integration current of 10 μA is used to exploit themaximum 2.6 V output dynamic range of the operational amplifier.

• After the rising edge of the Stop signal both Start- Stop signals are high, whichmake the voltage across the capacitor constant until a preset global timeout (cor-responding to maximum distance measurement has expired).

• The final state is the discharge state. The rising edge of the Start-Stretch signal willstart the discharge of the capacitor with a much smaller current for the analoguetime expansion as shown in Fig. 3. The stretched time can be measured by amultiphase ring oscillator based on-chip TDC, where a counter will count full clockcycles and an interpolator will determine the timing position within the clock cyclewith improved resolution.

3. Open-loop integration based time stretcher 53

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Figure 4: Open-loop integration-based time stretcher schematic, and transient simulation

.

2.2 Operational amplifier

The two stage operational amplifier used in Miller-integ-rator based time stretcher has aninput differential tran-sconductance stage with pmos input that is followed by a commonsource second stage [10]. The common source output stage is optimized for the supplyof an integration current with small area occupation and to maximize the output signalswing for a given supply voltage. The effect of a pole-splitting capacitor on the gain andphase of an opamp has been modified to improve the frequency response of the amplifier.The amplifier has unity gain bandwidth (UGB) of 471 MHz, with 71o phase margin. Inthe opamp design, the slew rate has been improved to 217 V/μs to minimize the deadtime.

3 Open-loop integration based time stretcher

The Miller integration approach is quite sensitive to stray capacitances and the opera-tional amplifier requires a considerable die area and power. Thus an alternative open-loopintegration based approach was studied, where wide swing cascode current source/sinkand a capacitor was used to implement the time stretcher, as shown in Fig. 4. Inopen-loop integration approach current sinks/sources with high output impedance arenecessary.

3.1 Basic operation

The operating principle of the open-loop time-stretcher is similar to the integrator based.During the idle state, the nmos switch is conducting and Vout is zero. Start opens thenmos switch and thereby removes the short circuit across the capacitor. The voltageacross the capacitor increases linearly until the rising edge of the Stop signal as shown in

54 Paper A

Figure 5: Nonlinearity and distance error (a) Miller-Integrator based TS (b) Open-loop inte-gration based TS

.

Fig. 5. The resulting voltage across the capacitor is a linear ramp directly proportionalwith time t: Vout(t) = I1 ∗ t/Cconv , where Cconv = 300 fF is the conversion capacitanceand I1 = 8.5 μA is the constant charging current. After the arrival of the Stop signal, theconversion capacitor is isolated and the voltage across the capacitor will remain constant.A current sink with nmos transistors is used to start the discharge of the capacitor withmuch smaller current I2 = 850 nA. The discharge is started on the rising edge of theStart-Stretch signal. The expanded time interval can be measured by an on-chip TDCwith improved resolution.

4 Results and Discussion

A time stretcher operate like a time amplifier when I2 < I1. The capacitor is charged witha constant current I1 during the measured time interval T and then discharged with amuch smaller current, I2. The stretch factor is defined as I1/I2. The conversion capacitordischarge time is stretched propotionally : Tstretch = Tk. A required resolution can beachieved by selecting the stretch factor k and counting full clock cycles of the multiphasering oscillator, also determining the timing position of an interpolator as shown in Fig.8. The value of the conversion capacitor does not have any direct influence on the stretchfactor. The geometrical size ratio between the two current generators will determine thestretch factor.

Any deviation from the ideal ramp output voltage from either circuit is translatedinto distance error. The integral non-linearity of the converter is defined as maximumdeviation of the actual transfer characteristic of the converter from a straight line [7]. Theaccuracy of the time stretching was evaluated in terms of the deviation from a straight

5. Conclusion 55

line (least squares fit). The integral non-linearity error is translated into correspondingdistance error at maximum dynamic range for both time stretchers as shown in Fig. 6aand 6b.

For the Miller integrator based time stretcher, the switching voltage variations bycharge injection from switches, have an impact on the sensitive integrator that causeglitches and non-linearity at the start as shown in Fig. 7a. The evaluation of theintegral non-linearity shows an error of a few cm for full scale range from 0-12 metersis achievable. The time stretchers are implemented in a 0.35 μm CMOS process withsupply voltage 3.3V. The integrator based time stretcher occupies an area 36×28 μ m2 asshown in Fig. 8a and its current consumption is 646.6 μA. Interestingly, the open-loopbased integrator achieves comparable performance, however with smaller circuit area27×27 μ m2, considerably lower current consumption 27.08 μA and with fairly smoothswitching transitions as shown in Fig. 6b. For Miller-integrator based time stretcher, theidle current consumption of the op-amp is much larger than charge/discharge currents.Whereas open-loop integration without an op-amp thus reduces the current consumptionsignificantly.

5 Conclusion

Two circuits have been investigated as time stretchers for dual conversion: time to chargeand charge to time. The third conversion is time to digital which is done by the globalTDC. Simulation results shows that low power and compact time stretchers can be builtfor on-pixel local analogue electrical storage and later on-chip integration with time todigital converter to achieve a distance error of a few cm. The investigated ideas along withsimulated results, evaluation of integral non-linearity and corresponding distance errors

Figure 6: Layout(a) Miller-Integrator based TS (b) Open-loop integration based TS

.

56 Paper A

are presented. Centimetre-level distance measurement error is achievable by selecting anappropriate approach for time stretchers, considering compact area, low power consump-tion, linearity and stability. The presented idea will be exploited further with on-chipsingle photon avalanche diodes as detectors and an on-chip time to digital conversion.

Acknowledgment

This work has been funded by the ESIS II project at Lulea University of Technology.

References

[1] D. Stoppa, F.Borghetti, J.Richardson, R. Walker, L. Grant, R.K. Henderson, M.Gersbach,E. Charbon, "A 32x32-pixel array with in-pixel photon counting and arrivaltime measurement in analog domain ", ESSCIRC2009.Proceedings, pp.204 a 207.

[2] Seitz, Peter; Theuwissen, Albert J. P. (Eds.), "Single photon detectors for Time-of-Flight Range Imaging ", Vol 160, D. Stoppa, A. Simoni, Springer Series in OpticalSciences, 2011, pp.277-299.

[3] E. Raisanen-Ruotsalainen, T. Rahkonen, J.Kostamovaara, " A time digitizer withinterpolation based time to voltage conversion ", Proceedings of 40th Midwest Sym-posium on Circuit and Systems 1997, vol. 1, pp. 197-200.

[4] Jozef Kalisz, "Review of methods for time interval measurements with picosecondsresolutions ", Institute of Physics Physics, Publishing, 2004.

[5] Blanar, G.; Sumner, R., "A self calibrating high resolution common stop time digitizercircuit”, Nuclear Science Symposium " IEEE, Vol 1, pp 697-699 ,9-15 Nov 1997. .

[6] M. Kanoun, Y. Berube-Lauziere, R. Fontaine, "High precision time-to-amplitude con-verter for diffuse optical tomography applications " , 3rd International conferenceDesign and Technology of Integrated Syst-in nanoscale, pp. 1-4, 2008.

[7] J Kalisz, M Pawlowski and R Pelka, "A method for autocalibration of the inter-polation time interval digitiser with picosecond resolution ", Journal of Physics E:Scientific Instruments, J Kalisz et al 1985 J. Phys. E: Sci. Instrum,Vol. 18, Issue 5.

[8] Keranen, P. ; Maatta, K. ; Kostamovaara, J.; Sergio, Maximilian; Charbon, "Wide-Range Time-to-Digital Converter With 1-ps Single-Shot Precision ", IEEE Transac-tions on Instrumentation and Measurement , Volume: 60 , Issue: 9 , pp. 3162 - 3172,Sept. 2011.

[9] Niclass, Cristiano; Sergio, Maximilian; Charbon, "A Single Photon Avalanche DiodeArray Fabricated in 0.35I1

4m CMOS and based on an Event-Driven Readout for TC-

SPC Experiments ", Proc. of SPIE Vol. 6372 63720S-1, SPIE Optics East, Boston,October, 2006

57

[10] Amana Yadav, "A review paper on design and synthesis of two-stage opamp "

CMOS OP-AMP, International Journal of Advances in Engineering and Technology,Jan 2012.,Vol. 2, Issue 1, pp. 677-688.

Paper B

Time-to-Digital Converter using anAnalogue Time Stretcher for 3D

Time-of-Flight Cameras

Authors:Muhammad Tanveer, Ilkka Nissinen, Jan Nissinen, Juha Kostamovaara, Johan Borg,Jonny Johansson

Reformatted version of paper originally published in:Proceedings of SPIE:9022, IST/SPIE Electronic Imaging 2014:Image Sensors and Imag-ing Systems 2014, edited by Ralf Widenhorn; Antoine Dupret, San Francisco, California,USA — February 02, 2014(http://dx.doi.org/10.1117/12.2036539),

c© 2014, International Society for Optical Engineering, Reprinted with permission.

59

Time-to-Digital Converter based on Analogue Time

Expansion for 3D Time-of-Flight Cameras

Muhammad Tanveera, Ilkka Nissinenb, Jan Nissinenb, Juha Kostamovaarab, JohanBorga, Jonny Johanssona


[email protected] Department of Electrical EngineeringUniversity of Oulu, FIN-90014, Finland

Abstract

This paper presents an architecture and achievable performance of time-to-digitalconverter, for 3D time-of-flight cameras in two levels. In the first level an analog timeexpansion, where the time interval to be measured is stretched by a factor k, is achieved bycharging a capacitor with current I, followed by discharging the capacitor with a currentIk. In the second level, final time to digital conversion is performed by global gated

ring oscillator based time-to-digital converter by exploiting its properties of intrinsicscrambling of quantization noise and mismatch error, and first order noise shaping. Thestretched time interval thus can be measured by counting full clock cycles and storing thestates of nine phases of the gated ring oscillator. The frequency of the gated ring oscillatoris of approximately 131 MHz and an appropriate stretch factor k, give a resolution of 57ps. The combined low nonlinearity of the time stretcher and gated ring oscillator basedtime-to-digital converter can be exploited further to achieve a distance resolution offew centimetres with low power consumption and small area occupation. The carefullyoptimized circuit configuration achieved by using an edge aligner, the required timeamplification property and the gated ring oscillator based time-to-digital converter maylead to a compact, low power single photon configuration for 3D time-of-flight cameras,aimed for a measurement range of 10 meters.

Keywords: Gated ring oscillator, Time-to-digital converter, single photon avalanchediode, 3D Time-of- ight camera, edge aligner, monostable multi-vibrator, Noise shaping,continuous time comparator

1 Introduction

Time resolved imaging in three dimensional image sensors has shown remarkable po-tential in recent years as it offers advantages over conventional intensity based imaging,

61

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source

SPAD TAC Time-Stretcher

Start

Stop

refV

Comp REGISTER

Stop

Start

Start-GRO

TDC-Stop

SERIAL OUTPUT

Counter state GTDC

Interpolator state GTDC

REGISTER

Photons

Photons

STRETCH TIME

CLK

Start-GRO

TDC-Stop

Stop-inp

COUNT countT

Inp-stopcountstretch TT T ��

Inp-stopT

Figure 1: Time-of-flight distance measurement system with per-pixel time stretcher, a GlobalTDC, and Timing diagram for the TDC.

in vision, engineering and medical research[1]. The continual emergence of new appli-cations requiring depth data often surpasses the capabilities of these existing productsand technologies, in attributes such as higher accuracy and precision, reduced acquisitiontime, smaller size and costs. In 3D time-of-flight (TOF) cameras the time informationis processed from each pixel to compute the depth and distance information.[2],[3] Themost critical component involved in the design of picosecond-resolution time resolvedimagers is the time-to-digital converter (TDC). These devices might have a global TDCto acquire fast images over the entire pixel array or many TDCs might be needed toenable independent and simultaneous acquisition and time discrimination at the pixelbasics[1]. However, to integrate many more TDCs on a chip, possibly one per detector,very compact TDCs need to be designed.

1.1 Background

Time interval measurement methods are described in the literature by using either digital,analogical or combined approaches i.e., by using the Nutt method,[5],[6] all depending onthe targeted application. In analog TDCs the time interval is measured by counting cyclesof the low clock frequency and linearly expanding fractional clock cycles.[7],[8],[9],[10],[11]On the other hand, digital interpolation uses a gate delay to estimate the fractional clockcycles.[12],[13],[14],[15],[16],[17],[18],[19],[20] A simple TDC consists of a high frequencyclock and a counter incremented at each clock edge. In such a case, the resolutionis limited by the use of the reference clock frequency. For example, as fclk = 1

�tis

needed for a resolution of �t, then �t = 100 ps implies fclock = 10GHz. This frequencyis not feasible for use across the array of pixels as it can cause several problems atcertain levels, particularly noise, crosstalk and power dissipation. One way to improve theperformance of TDC is to use analog time expansion,[5],[28] based on current integration,where the time interval to be measured is stretched by a factor k. The stretched timeinterval thus obtained can be measured by any TDC with improved resolution. Thetime-stretchers (TS) with precisely matched charging/discharging current can possiblyachieve better linearity than their digital counter parts[8]. Additionally, there mightexist a possibility that by using methods based on in-pixel analog electrical storage and

2. The Architecture of Proposed Time-to-Digital Converter 63

exploiting, such storage using pulse time-stretching techniques a better resolution, lowpower consumption and high geometry fidelity can be achieved.[11],[12],[13] The majorityof published devices mentioned above function as stand-alone custom integrated circuits,and hence the requirements on their area and power consumption are much relaxed.However, the fabrication of an array of pixels with in-pixel TDCs places strict demandsin terms of fidelity of geometry, power consumption and homogeneity in performance[1].

1.2 Aim and Proposed Idea

The aim of this work is to develop a high precision time-to-digital converter as an inte-grated CMOS chip to be used in 3D time-of-flight cameras for a number of applicationfields, such as obstacle recognition, automotive industry and video surveillance by mea-suring the depth and distance of an optically visible object. In this paper, we proposean architecture for a global gated ring oscillator-based time-to-digital converter (GRO-TDC) along with per pixel time stretchers as analog blocks. To achieve sensitivity toindividual photons and to extract 3D time-of-flight information, the time stretcher needsto be coupled to each pixel. Additionally, in an efficient SPAD sensor operating in directtime-of-flight mode, and to reduce parasitics associated with the detector, a time stampmust be generated for every impinging photon at every pixel detector. This necessi-tates the combination of per-pixel time-stretcher with a global TDC (time-digitizationcircuitry). Fig. 1 show a simplified front-end circuit and timing diagram of the concept.Radiation from a pulsed laser diode with short (≈ 100ps) pulse width will illuminatethe target surface and set a start timing mark. The reflected photons are absorbed bythe SPAD,[21],[25],[26],[27] which will set a stop timing mark. Meanwhile a pixel-basedcapacitor is charged from the rising edge of the start timing mark until the rising edge ofthe stop timing mark with a constant current. The charged capacitor is then dischargedwith a much smaller current functioning as a time stretcher based on analog time expan-sion. The global GRO-TDC is run during the discharge of the capacitor, between thetiming marks Start-GRO and TDC-Stop as shown in Fig. 2. This discharge (stretched)time interval is thereby measured by the GRO-TDC by counting full clock cycles andregistering the states of interpolators within the clock period.

2 The Architecture of Proposed Time-to-Digital Con-

verter

The conceptual block diagram of the time-of-flight distance measurement system withmultiple-stop signals at different time intervals is illustrated in Fig 2. The system consistsof pixel-based time-stretcher and comparators, TDC-input logic, nine-phase gated ringoscillator (GRO), edge aligner (EA) and registers for storing the state of the ring oscillatorby the timing signals (EN-GRO and TDC-Stop). A monostable multivibrator (MMV)can be used to generate an output pulse of a duration with a time interval correspondingto the final stop signal as presented in references.[28], [29] The logic level signal from

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1st Stop

Start-GRO

Stop-GRO

Final Stop Comparator output

DffD Q

EA

GRO

Registers

8 bit CounterCDES

P1 (reference_Clk)

TDC_Stop

Start

Start-GRO TDC-Stop

1st Stop

End of measurement

cycle

Start

EN / EN

On-chip Global TDC

p1 p2 p3 p4 p5 p6 p7 p8 p9

inp1 inp2 inp3 inp4 inp5 inp6 inp7 inp8 inp9

Stop_q1

b0b1b2b3b4b5b6b7

clk

Enable=1

Start-GRO

TDC input Logic

EA

EN-GRO

EN-GRO

TDC-Stop

Comparator output

Inp3= Select

Time-Stretcher Comparator

Interpolator result

On-chip (in each pixel)

MMV +

EA

Off-chip for test purpose

Figure 2: Time-of-flight distance measurement system concept with multiple stop-signals (asdetector matrix).

the comparator and TDC-input logic block will start and stop the GRO for stretchedtime interval measurement. The global TDC operates by counting full clock cycles fromthe rising edge of the comparator output (Start-GRO), which will start the GRO. Thefalling edge of the comparator output (TDC-Stop) will disable the GRO, and hence, thecounter is also settled. The registers determine the timing position within the clock cycle.The resolution of the GRO-based TDC can be defined by dividing the period of the ringoscillator by the number of phases of the gated ring oscillator, divided by the stretchfactor k.

2.1 Time Stretcher and Sub-circuits

The time stretching method converts the measurement time interval first to a corre-sponding analog voltage. In the second step, this analog voltage is then stretched by afactor k to achieve time amplification. Hence, two conversions are performed: time tocharge and charge to time. Whereas these will be performed in each individual pixel,the final time to digital conversion is performed by the global GRO-based TDC. Thesimplest topology to obtain a time-stretcher is similar to the Wilkinson ADC.[22] ,[23] Inthis topology the analog voltage is created by charging a capacitor during the measure-ment time interval and then discharging the capacitor with a much smaller current afterthe arrival of the stop signal. The ratio between the charge and the discharge currentsdetermine the stretch factor k. If the stretch factor is large enough, even a low resolutionTDC can be used to measure the discharge time(stretched-time), and finally, the originaltime measurement with improved resolution can be obtained. The sensitivity to noisein the integrating node and non-linearity in the capacitor can be minimized by using adifferential design with two identical capacitors that are discharged by different currentson the arrival of the start and stop signals [24]. Other design challenges are demand-ing requirements in terms of the comparator offset, propagation delay stability and areaconstraints that must be considered for 3D image sensor composed of pixel array-basedstructures. For an in-pixel solution, the area is especially critical. Therefore, to save area


convCStart

ddV

M2

M1

M3

M4

M5

M6

M7 M8

M9

M10

M11

M12

M13

M14

M15

M16 M17

M18

Stop

ddV

1I

kII 1

2 �

GRO-Start

Ms

Vout-TS

1I

2I

refV

convCStart Stop

GRO-Start

Vout-TS

refV M9

vout

ddV

refV

M1 M2

M3

M4

M5

M6 M7

M8M11

M10

M12

M13

Start_GRO

Comparator output

Vout-TS

Figure 3: a) Wide swing cascode current source/sink based time stretcher (left) b) SymetricalOTA based comparator with positive feedback and output logic gate (right).

a single-ended solution is selected for the work presented in this paper.

Design and operation of open-loop integration based time stretcher

An open-loop integration-based approach was studied previously[3], where wide swingcascode current source/sink and a capacitor were used to implement the time stretcher,as shown in Fig. 3a. In an open-loop integration approach based on current sinks/sources,important features that need to be considered are high output impedance, high linear-ity and small area. This is achieved by using wide-swing cascode structures[38]. Theschematic of the time stretcher comprises a wide-swing cascode current source and sink,a conversion capacitor Cconv, and switches to initialize the circuit and to control chargingand discharging of the capacitor. In the schematic Fig. 3a, M1 is the current source,M2 through M5 correspond to the biasing transistors, and M6 through M9 form acascode current source. Similarly in the current sink, M11 serves as the current sink,M10 through M14 correspond to the biasing transistors, M15 through M18 serve as thecascode current sink. The Start opens the nmos switch Ms and the voltage across thecapacitor increases linearly until the Stop signal arrives. Upon arrival of the final stop,the conversion capacitor is discharged with much smaller current to achieve analog timeexpansion. The final stop that also corresponds to the rising edge of the comparator, willsimultaneously start GRO-TDC for time interval measurement.The operating principle of the open-loop integration based time-stretcher is simple. Dur-ing the idle state, the nmos switch Ms is conducting and Vout-TS is at Vref . Startopens the nmos switch Ms and thereby removes the short circuit across the capacitor.The voltage across the capacitor increases linearly from a reference level Vref = 500 mV,common to the reference level of the comparator, until the rising edge of the Stop signalas shown in Fig. 7(a). The resulting voltage across the capacitor is a linear ramp directlyproportional with time t : Vout(t) = I1 ∗ t/Cconv, where Cconv = 300 fF is the conversioncapacitance and I1 = 8.4 μA is the constant charging current. After the arrival of the

66 Paper B

Stop signal, the conversion capacitor is isolated and the voltage across the capacitor willremain constant until the final stop has arrived. A current sink with nmos transistors isused to start the discharge of the capacitor with much smaller current I2 = 557 nA froma timing mark set by the final Stop.

Design of the comparator

For the realization of the stretched time interval, an analog decision circuit such as acomparator is required for each pixel. The comparator design and performance presentsmajor obstacles to achieving high-precision conversion. The parameters of the compara-tor, considered in our design, include a) minimum detectable input voltage, b) smalldelay to reduce non-linearity, and c) small offset and gain variation[31]. Additionally,to reduce the pixel area, while conserving the fill factor, it is important to simplify thecomparator structure to operate at low supply voltage in a specific technology. Thereare design trade-offs that might be necessary e.g., among architecture complexity, areaefficiency, delay requirements and power consumption. Here, a comparator with internalhysteresis has been selected for its robustness, compactness, low power dissipation, re-duced offset and low noise. The comparator with internal hysteresis also achieves shortdelay response and has good linearity[31].

The continuous time comparator shown in Fig. 3b consists of a PMOS M1 and M2 inputdifferential pair, that sets the transconductance and speed of the comparator, and alsocontributes an equal current at the detectable operating point by keeping the differentialpair tail’s current in saturation. The decision circuit is the heart of the comparator andmust be able to discriminate mV level signals. The circuit uses positive feedback fromthe cross-gate connection of M6 and M7 to increase the gain of the decision element.The input step (initial saturated input condition) of the comparator is Vout-TS, whichis driven to the output trip state at Vref = 500 mV as shown in Fig 3. (a), (b). The logicoperation AND between the output of the comparator and Start-GRO give an outputpulse as a realization of the stretched time interval as shown in Fig. 7 (a), which enablesthe GRO and also sets the stop timing mark for the global TDC as TDC-Stop.

2.2 Proposed GRO based TDC and sub-circuits

The basic TDC architectures are based on linear delay elements as shown in Fig. 4aand discussed earlier in section 1.1. These architectures basically operate on the risingedge of the Start signal, representing the first event, which is then successively delayedby a series of inverter gates ( ignoring polarity), each with an average delay Tq. Theoutputs from each of these inverters are inputs to a register, which is clocked with therising edge of the Stop signal representing the Stop event. The registers at the outputgenerate a thermometer code, which corresponds to the number of delay elements thathave transitioned within a measurement interval Tin. The average mapping from inputtime difference, Tin to digital code output Out has a limited resolution and nonlinearitydue to mismatch between delays elements.


DffD

Qclk

+

DffD

Qclk

DffD

Qclk

Delay Delay DelayStart

Stop OutReg Reg Reg

1

1

1

0

0�

qT Delay � (Varies due to mismatch)

Out

Start

Stop

inT

stopT

p1 p2 p3 p4

p5p6p7p8p9

p9

M2

M3

M4

M1EN

ENB

p1

EN / EN

Figure 4: a) TDC architechture based on linear delay elements (left), b) Gated Ring Oscillator(right).

The main idea of the gated ring oscillator-based TDC [32],[34],[35] as shown in Fig. 4bis similar to an oscillator-based TDC with a counter[33], as it measures the clock cyclesand the number of delay element transitions, generated by the ring oscillator structureduring the time interval measurement. However, unlike traditional oscillator-based TDC,the GRO structure only allows the oscillator to perform time interval measurement whenit is gated ON, by Start-GRO, from the rising edge of the comparator, and strives tofreeze when the time interval measurement has been made (on the falling edge of thecomparator). Fig. 4b shows a practical implementation of the GRO. Gating functionalityis added to the conventional inverter-based ring oscillators by placing two switches inseries with the positive and negative supplies for each inverter. When the switches areclosed, oscillation is enabled, and the oscillation is suspended when the switches are open.Two important factors that improve the performance of the GRO-TDC are quantizationnoise scrambling and mismatch of first-order shaped delay elements,[32],[34],[35] whichcan improve the linearity even in the presence of considerable mismatch. A number ofGRO with differential delay elements are also used in TDCs to achieve good differen-tial nonlinearity performance, mitigating the mismatch between rising and falling edges.However, a single-ended configuration may be preferable because differential nonlinear-ity is first-order shaped, and requires only modest levels of complexity that could beimplemented with smaller area and reduced power consumption.

vddEN_In

EN

ENB

One inverter delay

Only NMOS turn on Only PMOS turn onOS

EN

ENB

EN

ENB

p1p1

Without edge aligner With edge aligner

DffD Q

DffD Q

p1 (Ref Clk)

DffD Q

A

B

Select

inp3

Stop_q1

DffD Q

TDC_Stop

A

B

NOR

out

MUX

clk

clkclk Enablecounter

CDES

q2

q3

Shncronized_signal

A B

C

Figure 5: a) Edge aligner (left) b) Counter dual edge synchronizer structure (right)

68 Paper B

GRO-TDC operates by counting the pulses during the stretched time interval andrecording the states of its nine phases at the moment of arrival of the timing signals.The clock signal P1 in the timing diagram for the operation of the 9-phase GRO-TDC,as shown in Fig. 2, corresponds to one phase of the GRO. A counter is started by thenext rising edge of clock P1, after that GRO is enabled (for counting of the stretchedtime interval), and the counter is stopped by the next rising edge of the clock after theTDC-Stop signal as shown in Fig. 2. Special attention has been given to the layoutdesign of the GRO. The GRO inverters are placed in two rows but in opposite directions,to minimize the variation in parasitic loading of capacitances at each stage.

Edge Aligner and GRO-TDC input logic

If a time difference is present between EN/ENB i.e., if they are not perfectly alignedas shown in Fig 5a, only PMOS or only NMOS turns on during one inverter delay,contaminating the timing regions. Hence, the intrinsic phase storing ability of GRO-TDC will contain unwanted inband noise[35]. Therefore, GRO-TDC uses an edge alignerto generate perfectly aligned timing signals in order to achieve lower inband quantizationnoise and stronger noise shaping. In the edge aligner, SR latch with an inverter hasbeen used to generate perfectly aligned single-ended to differential-ended signals for theGRO-TDC. The output of the comparator is fed to TDC-in-logic block, which containsan edge aligner and a digital flip-flop (DFF) as shown in Fig. 2. This input logic blockdetects the rising edge of the comparator and generates the start signal EN-GRO for theGRO through a DFF. The falling edge of the comparator puts the stop timing mark forCDES of the GRO-TDC as TDC-stop. To achieve effective resolution, and to operate theGRO-TDC in the vicinity of ideal first-order noise shaping, the EN-GRO signal for GROis again directed into the edge aligner to turn on/off PMOS and NMOS simultaneouslyand to generate perfectly aligned EN/ENB signals as shown in Fig. 5a.

9 1 2 3 4 5 6 7 8 9876 1 2 3 4 5 6 7 8 9 1 2 3 4

p1 (Ref Clk)

Stop

q2

q3

Synchronized_signal

Counter

p1 (inverted Ref Clk)

0 1 2 3

inp

Stop (metastable state)

Figure 6: Counter dual edge synchronization timing diagram.


Counter Dual Edge Synchronizer

The timing signals (EN-GRO and TDC-Stop) are typically asynchronous inputs to thesynchronous measurement logic. Their arrival is expected at any time within the clockperiod, even when the signal recording by the registers is uncertain. This may cause ametastability problem, i.e., if the propagation delay, setup and hold times are violated[36].Additionally, the differences in register processes, layout parameters, differences in rout-ing and noise can shift the recording of the timing signal in the counter to the next clockcycle, creating an error of one reference clock cycle in the final GRO-TDC result.

This metastability problem can be handled by a dual edge synchronization scheme[36],where the counting is delayed by one reference clock cycle and the counter control (en-able/disable) is headed into the correct, safe position by the settled register result, asshown in Fig. 6. The counter dual edge synchronization [37] block consists of four flip-flops. The flip-flop A records the TDC-Stop timing mark, which is also a stop timingmark as Stop-q1 for interpolator registers as shown in Fig. 5 (b). The parallel flip-flopsB and C in Fig. 5 (b) records the falling and rising edges of the reference clock signal P1from GRO along with the arrival of stop timing mark TDC-Stop.

The stop signal TDC-Stop is also synchronized to both the rising and falling edges of thereference clock of the GRO. In Fig. 2, inp3 determine whether stop-q1 appeared duringthe negative or positive half cycle of the clock signal. The selection of interpolatorresult inp3 for the counter control is made on the basis of the next rising edge of thereference clock P1. The counter, synchronized by using a dual edge synchronizationscheme, ensures reliable recording of the timing signals, as one of the two flip-flops alwayshas enough delay between data change and the clock edge. It is evident from Fig. 6 thatthe counter is enabled/disabled one clock cycle later because the counter is also clockedin conjunction with the rising edge.

Time Stretcher

TDC input Logic

GRO

Interpolation Registers

CDES

8-bit counter

150 um

100 u

m

65 um

22 um

Figure 7: Time stretcher and Global GRO-TDC layout.

70 Paper B

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Figure 8: a) Time stretcher waveform and comparator output (left), b) Time stretcher linearityand error (right).

3 Results

The design discussed above has been implemented in a 0.35 μm CMOS process witha supply voltage of 3.3 V. The complete architecture (GRO-TDC and time stretcher)occupies an area of 150x100 μm as shown in Fig. 7. The per-pixel time stretcher canbe configured further to occupy an area of 40x40 μm, and a fill-factor of ≈ 25% can beobtained by using 35x35 μm SPADs. Simulations have been performed using CadenceSpectre with post-layout parasitics effects included. The waveform of the time stretcherand comparator output is shown in Fig. 8(a). The analog voltage Vout-TS is createdon the on-pixel capacitor for time interval measurement, and stretched by a factor ofk to achieve time amplification and sufficient resolution. The capacitor and the com-

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.

4. Conclusion 71

Table 1: Design Comparison

Ref Tech TDC core area Vdd ER Range Power[μm] [μm] [V] [ps] [ns] [mW]

[39] 0.13 CMOS 400× 400 1.2 20± 16 400 16[40] 0.35 CMOS 410× 630 3 78.5± 37 985 72[32] 0.13 CMOS 157× 258 1.5 1 2000 21[41] 0.35 CMOS 400× 300 43.4-3.7 57.3± 3.5 38 3.5[42] 0.35 CMOS 500× 450 3-4 50± 1.1 250 0.75

This work 0.35 CMOS 150× 150 3.3-3.6 56 75 2.423

parator are at the same reference voltage Vref = 500 mV, in order to exploit the linearoutput dynamic voltage range for the time interval measurement. A resolution of ≈ 57ps is achievable with an LSB=844 ps of the GRO and utilizing a stretch factor k=15.The linearity of the stretched time interval can be improved even further by increasingthe output impedance of current sources/sinks and designing perfectly matched currentsources/sinks. The nonlinearity error shown in Fig. 8(b) for the time interval measure-ment is also evaluated by dividing it by the stretch factor resulting in an error of lessthan half LSB as required. Figs. 9(a),(b) show the gated ring oscillator mismatch andcorresponding differential (DNL) and integral nonlinearities of the interpolators frompost layout simulations. The standard deviation of the interpolator is under 10 ps andINL is 24.7 ps, which is very small compared to the LSB of the GRO-TDC. Hence, theirimpact on the precision is minimal. The proposed design can result in very low currentconsumption even during the time interval measurements. The average current consump-tion of the design, when measurements are performed, is 2.4 mA. The obtained resultsare comparable to already published designs as shown in Table 1.

4 Conclusion

The concept of time amplification has been exploited by using an in-pixel time stretcher toachieve sufficiently improved resolution. Additionally, a gated ring oscillator-based time-to-digital converter is described that takes advantage of quantization noise scrambling ofmismatch error and first order noise shaping. The simulation results show that by usingan appropriate stretch factor and suitable frequency of the ring oscillator, a distanceresolution of a few centimeters can be obtained. This design is comparable to otherpublished designs in aspects of low power consumption, compactness and high resolution.The design can be exploited further to achieve a reasonable fill factor and good linearityfor in-pixel signal processing for the first prototype of 3D time-of-flight camera based on2D arrays of single photon avalanche diodes.

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Acknowledgment

This work has been funded by the ESIS II project at Lulea University of Technology.

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[20] Tisa, S.; Lotito, A.; Giudice, A.; Zappa, F. " Monolithic time-to-digital converterwith 20ps resolution " Solid-State Circuits Conference, 2003. ESSCIRC ’03. Proceed-ings of the 29th European , 16-18 Sept. (2003) , pp. 465 - 468

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[32] Straayer, M.Z.; Perrott, M.H. ; " A Multi-Path Gated Ring Oscillator TDC WithFirst-Order Noise Shaping " Solid-State Circuits, IEEE Journal of, Vol. 44, Issue 4,pp. 1089-1098, Sept. (2009) .

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Paper C

Time Stretcher for aTime-to-digital Converter with a

Precisely Matched Current Mirror

Authors:Muhammad Tanveer, Johan Borg, Jonny Johansson

Reformatted version of paper submitted to:27th IEEE International System-on-Chip Conference 2014

77

Time Stretcher for a Time-to-digital Converter with

a Precisely Matched Current Mirror

Muhammad Tanveera, Johan Borg a, Jonny Johanssona


[email protected]

Abstract

This paper presents an approach for the design of a time stretcher based on charging anddischarging a capacitor by currents with a ratio equal to the desired stretch factor. Thestretched time interval can be measured by using a time-to-digital converter to achieveimproved system resolution. Expressions for the current source output impedance andtransistor area required to reach a specified linearity and matching are derived. Therealization uses wide-swing current mirrors to achieve the required output impedance atan acceptable voltage swing at the capacitor. The derived expressions and the overalldesign are validated with schematic and extracted simulations in a 0.35 μmCMOS processtechnology.

1 Introduction

The performances of time-to-digital converters are mainly determined with finite SNRs(signal-to-noise ratios) and mismatching of integrated elements [1]. Measuring time withpicoseconds-level resolution is a tremendous challenge. To minimize the impact of fi-nite SNRs and mismatching of integrated elements, the concept of time stretching oranalogue time expansion can be an effective solution. Time stretching processes smalltime difference and outputs a larger time difference, which can improve the resolution oftime-to-digital converters.

In this work, an analogue time stretcher with a stretch factor is designed from standardbuilding blocks, such as current mirrors. The most significant features for determining thefeasibility and performance of the current mirror are the following: acceptable accuracy,high output impedance, high linearity and small area [2][3][4]. This work is divided intoseven sections. Section II presents a current mirror-based time stretcher. In section III,the design constraints are discussed in detail. In sections IV and V, we focus on thepractical design, layout and simulations. The results are presented in section VI. SectionVII briefly describes about the layout strategy. This work is concluded in section VIII.

79

80 Paper C

TDC Core

inT outT

011…..010

A

B Time wordsTS

Figure 1: Architecture of TDC based on time stretcher.

2 A current mirror-based time stretcher

In analogue time expansion [5][7], the time interval to be measured is stretched by a factork, realized by charging a capacitor with a constant current I, followed by discharging thecapacitor by a constant current I

k. This stretched time interval can be measured with a

time-to-digital converter with a lower resolution[5].

The design consists of a current mirror, current source and precisely matched currentsinks and dummy elements. Constant current I

kis produced in the current sink and is

copied in similar current sinks to achieve an appropriate stretch factor. Dummy elementsare added to provide identical temperature gradients and similar boundary conditions.The operating principle of the current mirror-based time stretcher is shown in Fig. 2.During an idle state, the nmos switch conducts and Vout is zero. Start opens thenmos switch and thereby removes a short circuit across the capacitor. The voltageacross the capacitor increases linearly until the rising edge of the Stop signal. Theresulting voltage across the capacitor is a linear ramp that is directly proportional totime t: Vout(t) = I1 ∗ t/Cconv, where Cconv is the conversion capacitance and I denotes theconstant charging current. After the arrival of the Stop signal, the conversion capacitoris isolated, and the voltage across the capacitor remains constant. A current sink withnmos transistors is used to initiate capacitor discharging with I

k, a fraction of the charging

current. Using this design technique, the constant current I is an exact copy of Ik, but

with a stretch factor k, and thus achieves an analogue time expansion that may be usedto improve the time-to-digital conversion resolution [5][7]. The current mirror-based timestretcher schematic circuit with stretch factor k=4 is shown in Fig. 2.

3 Design Constraints

3.1 Current mirror matching

The time stretcher design challenge is a trade-off between complexity, current mirrormatching, area and low power consumption, considering the constraints for a particular

3. Design Constraints 81

Stop

convC

ddV

Start

Stretch

refV

Comp-out

kI

I I

kI

kI

kI

kI

Current sinks

Current mirror

Figure 2: Time stretcher schematic.

application. Additionally, precise stretch factor matching is required [8]. If the currentmirrors are not precisely matched, the design may suffer from gain error. An estimationhas been performed based on the Pelgrom’s MOS transistor-mismatching model devicesto determine the relationship between area and mismatching [12]. The threshold voltagemismatch can be written as

σΔ Vt =AV T√WL

. (1)

The conductance parameter mismatch can be written as

σΔβ

β=

Aβ√WL

. (2)

Considering the standard deviation of the drain source model that is valid in all regionsof operation, we can write

σΔIDID

=

√(σΔβ

β)2 + (

gmID

)2(ΔVt)2. (3)

Table 1: Requirements set for design constraints

Parameter By analysis

Current mirror matching(σ(ΔIDS

IDS)) 1%

Overdrive Voltage (Vov) 300 mVVerror from full voltage swing 1% of 2 V

Linear dynamic range 70 ns≈ 12 metersktC

(Capacitor noise) 50 fF ↔ 0.029 mV

Output Impedance ≈ 25 MΩ

82 Paper C

This equation can further be simplified to identify an appropriate MOS transistor channellength as:

(σΔIDID

) =

√A2

β

(WL)+ ((

2IdVov

)(1

Id)(

AV T√WL

))2, (4)

(σΔIDID

) =1√WL

√A2

β + (2

Vov

× AV T )2, (5)

√WL = (σ

ΔIDID

)

√A2

β + (2

Vov

× AV T )2. (6)

Additionally WL

for all devices can be calculated using the drain current as shown in thisequation

W

L=

2IDμn,pCoxVov

. (7)

3.2 Required linearity and output impedance

The required output impedance is directly related to the integral non-linearity. In ourdesign, this non-linearity is translated into error in respective time and distance measure-ments. With the proposed circuit design, a numerical evaluation was performed regardingthe required output impedance as a function of linearity.The time stretcher can be modeled as a simple RC circuit, as shown in Fig. 3(a), with acurrent source, resistance R and a capacitance C, having an initial voltage V0. We canwrite

refV

error

V

tmaxV

mintmaxt0V

Volta

ge/V

time/ns

RI

(a) (b)

convC

Figure 3: Time Stretcher modelled as RC circuit.

3. Design Constraints 83

dV

dt= − V

CR− I

C, (8)

and the voltage across the capacitor can be derived as a function of time with

Vt = (V0 + IR)× e−tRC − IR. (9)

In Fig. 3, Vref represents an ideal ramp voltage between extreme points tmin and tmax.The integral non-linearity can be defined as the maximum deviation of the actual transfercharacteristic from a straight line, where the line is

Vref (t) = (Vtmax − Vtmin)× tmin

tmax − tmin

+ Vtmin. (10)

From Fig. 3, the integral non-linearity Verror can be written as the maximum deviationfrom Vref as a function of time,

Verror = max(Vt − Vref (t)). (11)

Combining equations 9 and 10, we can write

Verror = max | (V0 + IR)× e−tRC − IR− (V0 + IR)

× (e−tmax

RC − 1)× t

tmax

− V0 |, (12)

Verror = max | (V0 + IR)

×A︷︸︸︷

(e−tRC − t

tmax

.× (e−tmax

RC − 1)−1) | . (13)

Solving A to evaluate t at the point of maximum error,

dA

dt=

1

RC× e

−tRC − 1

tmax

× (etmaxRC − 1), (14)

and solving for t,

e−tRC = − RC

tmax

× (e−tmax

RC − 1); (15)

84 Paper C

Thus,

t = −RCln(RC

tmax

× (1− e−tmax

RC )). (16)

Expanding eq. 12 using Taylor’s expansion

t = −RC

× ln(1− 1 +tmax

RC− (

tmax

RC

2

)1

2)), (17)

t ≈ −RC × ln(RC

Tmax

× (tmax

RC− (

tmax

RC)2)

1

2)), (18)

t ≈ −RC × ln(1− tmax

RC× 1

2), (19)

t ≈ −RC(−)× ln(tmax

2RC). (20)

Assuming t << RC, we find t for the maximum error as

t ≈ (tmax

2). (21)

Using eq. 12 and eq. 21, the following simplifies to:

Verror = (V0 + IR)× (e−tmax2RC − 1

2(e−tmax

RC − 1)− 1), (22)

thus

Verror = (V0 + IR)×D︷︸︸︷

(e−tmax2RC − 1

2e−tmax2RC − 1

2) . (23)

Expanding D using Taylor’s expansion, we can obtain an expression for Verror, which canbe further simplified to achieve an approximate value for the required linearity outputimpedance:

D ≈ 1

8(tmax

RC)2 − 1

4(tmax

RC)2 = −1

8(tmax

RC)2. (24)

Thus,

Verror =IR

8(tmax

RC)2 =

I

8C2× t2max(

1

R), (25)

solving for R yields the required output impedance,

R =I

8(tmax

C)2(

1

Verror

). (26)

4. The high swing cascode current mirror 85

3.3 Conclusion from design constraints

Table 1 presents the system-level design requirements to be used in determining ourrequired design specifications. In section III.(A) AV T , Aβ and μCox represents constantsthat are technology dependent. The value of σ(ΔIDS

IDS) has been assumed to be 1%. In

section III.(B), the output impedance was calculated assuming a Verror = 1% of 2 V(output voltage swing). For this work, we used a charging current of I= 2μA anda capacitance of C=50 fF. The kt

Cnoise associated with the capacitor was 0.029 mV

rms, which corresponds to a fraction of centimeter in distance error. tmax represents thedynamic range of the time stretcher, with a design value of 70 ns ≈ 12 meters in distancemeasurement.

Based on the design requirements, equations (6), (7) and (26) were evaluated todetermine the required output impedance and device sizing for matching. The outputimpedance evaluated during capacitor charging was 25 MΩ. The output impedance fordischarging is k times that required for charging. The transistors

√WL, as evaluated with

derived equations (6) and (7) are ≈2.5 μm and ≈3 μm, for nmos and pmos, respectively.The final device sizes used for the design are listed in Table 2.

4 The high swing cascode current mirror

A high swing cascode current mirror is the preferred topology for the proposed timestretcher (Fig. 4), due to its low voltage operation, capability of output voltage swing,simplicity, small area and reasonable degree of precision [9][10]. The circuit is charac-terized by its moderately low input impedance Rin = 1

gm4(∼ kΩ) and moderately high

output impedance Rout = ro1gm2ro2 (∼ MΩ) [9]. The notations: ro and gm representMOS transistor small-signal output resistance and transconductance respectively, wherero1 represents the source/sink and ro2 presents the small-signal output resistance forcascodes.

Fig. 4(a) demonstrates the high swing cascode current source based on pmos tran-sistors used for charging the capacitor with constant current. The main current sourcedevices are Mp1 and Mp3, with Mp2 and Mp4 acting as cascode devices and Mp5 asa biasing transistor that sets the desired VDS, by ensuring that the rest of the devicesremain in saturation. The value for VOV was chosen based on the required linear output

Table 2: Design specifications

Parameter Proposed Structure#1

PMOS (W2

L2= W3

L3) 1500nm / 3200nm

PMOS (W1

L1= W4

L4) 1500nm / 1500nm

NMOS (W1

L1= W2

L2= W3

L3= W4

L4) 1500nm / 4000nm

VDD 3.3VNo Of Transistors 5

86 Paper C

Mp5

Mp4

Mp3 Mp1

Mp2 Mn5

Mn4

Mn3 Mn1

Mn2

REFI REFI

REFI REFIOUTI

OUTI

ddVddV ddV

(a) (b)

11 LW

22 LW 33 LW

44 LW

11 LW

22 LW 33 LW

44 LW

Figure 4: High swing cascode current mirror architecture (a) High swing cascode current source(b) High swing cascode current sink.

voltage swing for the time stretcher. The main current source devices Mp1 and Mp3must be precisely matched to achieve the low output current variation specified for thesource current. As the current varies inversely with transistor channel length, the channellength of transistors Mp1 and Mp3 were high, as presented in section III. The typicalVOV for the current sources Mp1 to Mp4 and current sinks Mn1 to Mn4 were chosen as300 mV and 350 mV, respectively. The values for VOV were selected as a compromisewith respect to the required output voltage swing and high output impedance for thetime stretcher. In this design, Iref,pmos ≈ 2 μA for the pmos-based current source and forthe nmos-based current mirror with k=4 Iref,nmos = Iref,pmos/4 = 0.5 μA were selected(Fig.2).

The current sinks are implemented using nmos transistors for capacitor dischargingand mirroring, as shown in Fig. 4 (b). As previously discussed, the channel lengths of themain current source devices Mn1 and Mn3, presented in section III are high to minimizemismatches. In both cases, the cascode device mismatches do not significantly contributeto the output current matching. Although not applied here, the channel length of the

��

� MIVRout

out 36�

��

� MIVRout

out 250

Figure 5: Output current in terms of output voltage (pmos), and Output current in terms ofoutput voltage (nmos).

5. Implementation 87

Figure 6: Layout analysis by increasing Stretch Factor for improving distance error.

cascode devices could be smaller as a trade-off to save area and to minimize the outputcapacitance at the output of current source and sink outputs.

5 Implementation

The proposed high swing cascode current mirror-based time stretcher was designed andsimulated in a 0.35 μm CMOS process. The design was implemented for stretch factork=4, k=9, k=14 and k=19, to understand the influence of the parasitics and possibletrade-off between time stretcher area and resolution for time-to-digital converter. Themismatch due to random variations is kept at a manageable level by using appropriatedevice sizing as derived in section (III). A common centroid layout technique for thecurrent mirrors was used in order to minimize the impact of systematic errors [11]. Atime stretcher with k=4 occupies an area of 24×32 μm2, k=9 occupies an area of 52×46μm2, k=14 occupies an area of 67× 47 μm2 and k=19 occupies an area of 78× 48 μm2,respectively.

6 Results

To verify the performance in terms of output current variations, simulations were per-formed. Fig. 5 illustrates the DC characteristics of the current mirrors. The averageoutput impedances for the nmos and pmos-based current mirrors are significantly abovethe requirements as presented in section III for an output voltage range of 0.5-2.5 V. From

88 Paper C

� ��

��

��

� ��

��

�

�

�

� ��

��

�

�

�

� ��

��

�

�

�

� ��

��

�

�

�

��

��

��

��

��

��

��

44

Figure 7: Time stretcher transient simulation with k=4, and output linearity (schematic vslayout) for different stretch factors with multiple stop timing marks

Monte Carlo simulations, the observed mismatch with 150 runs for nmos and pmos-basedcurrent mirrors are in the range of -0.85% ∼ 1.01 % and -0.78% ∼ 1.45 %, respectively,for an 1.5 V output voltage. Schematics and post layout simulations were performed toanalyze the impact of the parasitics involved, as shown in Fig. 7, and Fig. 8. The designwas evaluated and compared using four different stretch factors. The main factors thatnegatively affect stretch factor matching are comparator offset error and dispersion andnon-linear in the transfer characteristics of the time stretcher.

Figure 8: Distance error from schematic simulations, and distance error from layout simula-tions.

7 Conclusion

This paper presents an approach for the design of a time stretcher. Design constraintshave been discussed for achieving output linearity and current mirror matching. The

References 89

design was implemented for a precise magnitude of the stretch factors. Considering thenon-linearity, transfer characteristics of our time stretcher and current mirror matching,attaining a distance error of a few centimeters for a distance range of 10-15 meters waspossible. This concept of a precisely matched time stretcher with high linearity gaincan be used in conjunction with any time-to-digital converter to achieve an increasedresolution and minimum distance error.

References

[1] Jozef Kalisz "Review of methods for time interval measurements with picosecond res-olution"IOP science Journal, Volume 41, Issue 1 , DOI:10.1088/0026-1394/41/1/004

[2] Rajput, S.S. and Jamuar, S.S. ; "Advanced current mirrors for low voltage analogdesigns" Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conferenceon, 7-9 Dec. 2004 , DOI 10.1109/SMELEC.2004.1620882

[3] Meaamar, A. ; Othman, ; "Low-Voltage, High-Performance Current Mirror CircuitTechniques" Semiconductor Electronics, 2006. ICSE ’06. IEEE International Confer-ence on , Oct. 29 2006-Dec. 1 2006, Page(s): 661 - 665 .

[4] Hitesh and Anuj Goel ; "Performance Parameters of Improved Swing, Wilson andRegulated Cascode Current Mirrors" International Journal of Advanced Research inComputer Science and Software Engineering , March 2012, Volume 2, Issue 3.

[5] Blanar, G. ; Sumner, R. ; "A self calibrating high resolution common stop timedigitizer circuit" Nuclear Science Symposium, 1997. IEEE , 9-15 Nov 19972, Page(s):697 - 699 vol.1 .

[6] Raisanen-Ruotsalainen, Elvi ; Rahkonen, T. ; Kostamovaara, J. ; "A time digitizerwith interpolation based on time-to-voltage conversion" Nuclear Science Symposium,1997. IEEE , 3-6 Aug 1997 , Page(s): 197 - 200 vol.1 .

[7] Raisanen-Ruotsalainen, Elvi ; Rahkonen, T. ; Kostamovaara, J. ; "A time digitizerwith interpolation based on time-to-voltage conversion" Nuclear Science Symposium,1997. IEEE , 3-6 Aug 1997 , Page(s): 197 - 200 vol.1 .

[8] R. Jacob Baker. [ CMOS: Circuit Design, Layout, and Simulation, Third Edition.]Wiley-IEEE Press, ISBN 978-0-470-88132-3, 3rd Edition, 2010 , Chapter 1, pg 8.

[9] Ramirez-Angulo, J. ; Sawant, M.S. ; Lopez-Martin, A. ; Carvajal, R.G. ; "Compactimplementation of high-performance CMOS current mirror" Electronics Letters , Vol-ume: 41 ,12 May 2005, Issue: 10, Page(s): 570 - 572 .

[10] Khairul Affendi Rosli, Md. Mamun, Mohammad Arif Sobhan Bhuiyan, and HafizahHusain ; "A Low Loss Wide Swing Cascode Current Mirror in 0.18-I1

4m CMOS Tech-

nology "Journal of Applied Sciences Research , 2012, ISSN 1819-544X.

90 Paper C

[11] Mao-Feng Lan, Anilkummar Tammineed and Randell Geiger ; "Current Mirror Lay-out Strategies for Enhancing Matching Performance "Analog Integrated Circuits andSignal Processing, 28, 9a26, 2001 .

[12] Martinez Brito J.P. , Klimach, H. ; Bampi, S.; "A Design Methodology for MatchingImprovement in Bandgap Reference" Quality Electronic Design, 2007. ISQED ’07. 8thInternational Symposium, 26-28 March 2007, 586 - 594, San Jose, CA .

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