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Two RF/Microwave Software Programs Used in Tandem Streamline the Design of Power Amplifiers

Ivan Boshnakov, Jon Divall Aerial Facilities Ltd, Aerial House, Asheridge Road,

Chesham, Bucks, HP5 2QD, UK www.aerialfacilities.com

This article describes a procedure for the design and development of power amplifiers using harmonic-balanced software in tandem with impedance matching network synthesis software. For this purpose a particular design problem will be discussed. The Design Problem

A new amplifier had to be developed to replace an existing amplifier which had been a sound product for many years, but the RF bipolar power transistors used in it had become obsolete. This pre-existing amplifier works in Class A mode and delivers P1dB in excess of 20W in a 20MHz bandwidth. Its center frequency is tunable from 380 to 470 MHz. It is in a 2 stage single ended configuration with gain of more than 23.0 dB and the input/output return loss of better than 20dB. This amplifier has been designed by “cut and try” modification of the schematics and topologies suggested by the manufactures of the transistors. The topology is mixed - microstrip, lumped capacitors, porcelain tuning capacitors and coils with ferrite beads are used. The tuning in production takes some time, but it is fairly consistent and straightforward. Very often two of these amplifiers are used in parallel, in a balanced configuration, to produce P1dB of more than 40W. The two amplifiers and the hybrid couplers are in connectorized packages and are connected together by coaxial cables. The New Design Approach

For the new design the idea was to use the most up-to-date devices and design methods in order to achieve optimum performance. Additionally, substantial reduction of the cost of components and production was desired. The RF power transistor was selected to be MRF9045 - one of the Motorola LDMOS transistors. These transistors are supplied with very good non-linear models available in most of the well-known harmonic-balance simulators. The preliminary analysis showed that a single stage balanced amplifier would give sufficient gain and more than 40W (46dBm) of P1dB when biased at 23 V and 3.0A per transistor and very good input/output return loss over the whole bandwidth of 380 – 470MHz. For this design effort two EDA software packages were used in tandem. Microwave Office from Applied Wave Research (www.mwoffice.com) was used for its non-linear (harmonic balance) simulation capabilities. MultiMatch Mosaic by Ampsa (www.ampsa.com) was used to synthesize the broadband impedance matching networks. Arbitrary impedances specified in “real frequency” format can be matched with Mosaic. The two programs work smoothly together because the synthesized solutions of Mosaic can be exported as Microwave Office schematic. The Design Procedure The design started with a schematic in Microwave Office. The schematic consisted of the RF transistor and two tuners at the input and at the output of the transistor (Figure1). The tuner selected to be used in this design from the Element Catalog has integrated bias tee, which allowed the appropriate biasing to be applied directly, without adding any other elements or influencing the RF performance. The biasing was organized in another sub-circuit and added to this schematic. It supplied 23V and constant current to the LDMOS transistor. The tuner at the output of the transistor was used to extract the reflection coefficients of the optimum load for which maximum P1dB is achieved at a set of frequencies in the required bandwidth. The input tuner was only used to maximize the gain to reduce the required input power levels.

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Figure 1. Optimum load extraction schematic The set of frequencies was selected to be from 375 to 500MHz with a 25MHz step. For each frequency the input power was swept in an appropriate range and the tuners were tuned “manually” until maximum P1dB was achieved. At each setting of the output tuner P1dB was found graphically. Figure 2 shows how this is done: The first step is to put a marker somewhere where the gain is flat and maximum. Then the next marker is put where the gain has compressed 1dB. The third marker is at the same input power where the gain has compressed 1dB, but on the Pout versus Pin graph and so it gives the P1dB.

Figure 2. P1dB defining graph

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When P1dB was considered to be at its maximum value, the magnitude and phase angle of the tuner was recorded. The “manual” tweaking of the output tuner is a tedious process, but still in a few hours the data for all the frequency points was taken.

The design continued in MultiMatch Mosaic where the conjugate reflection coefficients were typed in the Terminations window of the Specifications menu (Figure 3). Then all the other specifications, requirements and constraints were determined. The network to be synthesized was chosen to be mixed lumped-microstrip, and it was restricted to have only microstrip transmission lines and capacitors. A very useful feature of Mosaic is that the lumped components can have predetermined attachment/solder pads and connecting lines. The parasitic series inductor of the capacitors can also be specified in advance. The transmission lines in the synthesized schematics of Mosaic are ideal (electrical). During the translation to its own layout Mosaic compensates for the discontinuities at the microstrip junctions changing the lengths of some of the lines at the particular junction. The same is done when the schematic is exported into Microwave Office schematic. The appropriate discontinuity elements are also placed at the junctions.

Figure 3. Terminations window in Mosaic

After the synthesis is run there are up to ten solutions to choose from. Figure 4a shows the schematic of the solution chosen in this case. Figure 4b shows the same solution in more detailed form. Its main advantage is that the high impedance shorted stub on the left can be used to supply the drain bias required. This solution is also insensitive as indicated by the increase in the mini-max error from 0.31% to only 0.62% when the line lengths and the capacitor values are changed by1%.

Figure 4a. Mosaic schematic solution window

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Figure 4b. Mosaic detailed schematic

The layout of this solution is shown in Figure 5. The layout created by Mosaic gives the designer a very good visual idea what the final layout will look like. The meandering of the microstrip line on the right can be done either in Mosaic or in Microwave Office. Both software programs have layout editing features which are easy to use and help to speed up the layout design.

Figure 5. Mosaic layout solution This solution was exported into a Microwave Office schematic script file. The script file was

executed in Microwave Office to create the Microwave Office schematic and the associated layout. The translation of the Mosaic solution into Microwave Office is very simple and happens in less than a minute. A very important feature of Microwave Office is that the schematic and the layout are one object in the software data base.

In Microwave Office a few small changes were made in the schematic and correspondingly to the layout. All the capacitors were replaced by models and values from the existing libraries. The high impedance stub was shorted by capacitors. Figures 6a and Figure 6b show the Microwave Office output network schematic and layout.

Figure 6a. Microwave Office schematic for the solution

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Figure 6b. Microwave Office corresponding layout

With the load (output) network in place, the transistor and an input biasing network were added next (Figure 7). The input biasing network has also a stabilizing effect on the amplifier. Simulations were performed and some tuning was done to achieve maximum and flat P1dB over the bandwidth. It was optimized by tuning to be better than 44.5dBm.

Figure 7. Adding the RF transistor and input biasing network

In order to synthesize the input impedance matching network, the small signal S-parameters of the circuit as designed up to this point and its operational gain were required. A simulation was performed at low signal level and with a frequency sweep from 375 to 500 MHz with a step of 25MHz. Table 1 shows the simulated transducer gain (GT) and operational gain (GP). GT is the gain of the amplifier as designed (Figure 7) and GP is the gain if the input reflection coefficient (S11) was conjugate matched.

Frequency [MHz]

dB(GT) dB(GP)

0.375 17.919 26.871 0.4 17.07 26.035 0.425 15.95 24.779 0.45 15.536 24.297 0.475 15.158 23.969 0.5 14.835 23.73

Table 1. Simulation results for GT and GP

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The next steps were first to export an S-parameter file out of Microwave Office and then to import it into Mosaic to perform the new synthesis task. When the S-parameter file is imported into Mosaic a dialogue window opens and the designer has to select whether S11 or S22 is to be used as the load (ZL) or the source (Zs) impedance. In this case S11 was chosen to be the ZL. Then the Terminations window opens (Figure 8). S11 is already automatically filled in the columns for the reflection coefficient of the load. As it can be seen from Table 1, the GP of the amplifier is sloping down quite substantially. In order to achieve flat gain, corrective values were entered in the last column of the Terminations window.

Figure 8. Terminations window

The schematic and the layout solution that were chosen after the synthesis was performed are shown in Figure 9a and 9b. This solution was exported to Microwave Office and Figure 10 shows the layout of the final solution. The final simulated performance (gain and input/output return loss) is shown in Figure 11.

Figure 9a. Mosaic schematic solution for the input matching network

Figure 9b. Mosaic corresponding layout

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Figure 10. Final layout in Microwave Office

Figure 11. Simulated performance A final balanced amplifier configuration was not simulated. This single-ended amplifier layout was exported to another drawing software package, where a full-blown PCB was designed for the balanced version. The performance of the first prototype built (gain and return loss) is shown in Figure 12. For comparison purposes it also shows the simulated gain. The return loss is of course very good because of the balanced nature of the amplifier. The P1dB performance is shown in Figure 13.

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Figure 12. Measured performance for Gain and RL

Figure 13. P1dB measured performance The performance of the amplifier satisfies the requirements with adequate margin in any 20MHz of the overall 380 – 470MHz bandwidth. Broadband measurements of the S-parameters and the calculated stability k-factor showed that the amplifier is unconditionally stable.

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Figure 14 shows a flowchart with the main steps of the described design procedure.

Figure 14. Design procedure flowchart

Summary and conclusions It is obvious that, mainly because of the relatively broadband matching networks, this amplifier will need very little or no tuning during production. The two LDMOS transistors for this new 40W amplifier cost the same as the two RF bipolar transistors in the 20W amplifier, and the overall material cost is substantially less. All the components on the PCB except the RF transistors are surface mount and “pick and place” (Figure 15). There are no coil inductors and no ferrite beads which would require hand-mounting work. Finally it was found by simulation and experimentation that if the current is reduced from 3.0A to 1.8A per transistor, the amplifier delivers more than 20W of P1dB. In this way the same amplifier satisfies the needs for both 20W and 40W amplifiers.

Extract the reflection coefficients of the optimum load for maximum P1dB in Microwave Office.

Synthesize the output matching network in Mosaic and import it into Microwave Office.

Add the transistor and an input biasing network, tune if necessary for maximum P1dB over the frequency bandwidth and export an S-parameter file.

Import the S-parameter file into Mosaic, set up the corrective values for flat gain and synthesize the input matching network.

Import the input matching network in Microwave Office and tune if necessary for the required gain over the bandwidth.

Create full-blown PCB design and the necessary documentation to build prototypes.

Build and test prototypes.

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Figure 15. Photo of the first prototype

It is also obvious that the chosen design method leads to “first time right” designs. The design process is very straightforward. The synthesis runs in Mosaic are very quick once the initial specifications and constraints have been determined. It is usually necessary to run a few iterations with selecting different topologies, characteristic impedances of the microstrip lines and/or constraints for the lumped components, but for a relatively experienced designer it could be down to half an hour per matching network. The design procedure described reveals how to use Microwave Office (a non-linear simulator) and MultiMatch Mosaic (impedance matching synthesis software) in tandem in order to realize a highly productive design process and cost effective designs. Acknowledgements The author would like to thank Muhammad Iqbal of Aerial Facilities Ltd. for his assistance with the documentation, building and testing of the prototypes and Ron Broom of Aerial Facilities Ltd. for his expert editing assistance.

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