PAn

PI

PSr,sRK

RO

SBp

SCr

SHp

SLp

SMSO

Pause and display result for 0 1 x «sbefore continuing to process thecurrent command string. If n is zero,await the 'continue' command fromthe console keyboard.Picture integrate;

fc=oPicture shift; bUj <-aj+rj+s

Rank of pixel a(j among its 8neighbours in that 3 x 3 windowcentred on (/, /).Robert's gradient operator (GonzalezandWintz)11

Bit-slice function. Set those bits in fly-specified by the octal number p tozero. Result in Z>,7.Retain r of the most significant bits:B <- (A + 26 ~r) x 26 "r where *denotes the integer-divide function.Shift intensities B <- if A > 63-pthen 63 else

beginif A + p < 0 then 0 else A+pend

A by an amount p. A similaractually a trapezoidal dis-is described by Hale and

THp,q

XM

SUTB

Slantprocess,tortion,Saraga.2

Halve the intensities;B+-A + 2Sobel gradient operator; equivalent toread original; GP1, 0 , - 1 , 2 , 0 , - 2 ,

1 , 0 , - 1 ; NE; MI; store temporaryresult

read original; GP 1, 2, 1, 0, 0, 0, - 1,— 2, — 1; NE; MI, store temporaryresult

then use either MI or AD to combinethese two temporary results.Subtract B «- (A - B + 63) + 2Test for a black picture; abort thecommand string if A is all black

YXYMTHp,qZEStandardpictures:

Input/outputoptions:

Threshold: B<- if A>p andthen 63 else 0Find the median value of x. Calculatethat value of p which satisfies127 P 127 127

1J L,au = L L au;=Oi=o tJ j=oi=p+i'J

Exchange x- and ̂ -axes; bit, <- ait {

Find the median value of y (similartoXM).Zero picture;/! «-0

Wedges (2 options)Cone (Fig. 4b)Random pictures (many)Test cardAny of these can be processed to yieldother 'standard' pictures

Read intensities from paper tapePunch intensities on paper tapePunch run-codes on paper tapePunch chain-codes on paper tapeSample a.d.c. input, to generatepicture from analogue tape recording(maximum sampling frequency50 kHz).Figs. 6a and 6b were generated in thisway.Modcomp IV/Susie data link, facilitiesprovided:(a) Intensities (Modcomp IV to Susie)(b) Run code (Modcomp IV to Susie)(c) Chain code (Modcomp IV to Susie)(d) Intensities (Susie to Modcomp IV)(e) Run code (Susie to Modcomp IV)(/) Chain code (Susie to Modcomp IV)(g) Control Modcomp IV via Susie,Uses Susie as a 'telephone exchange'Camera (function CA) (digitisationtime 5-2 s).

Design of counter registersFerdynand Wagner

Indexing terms: Counting circuits, Sequential circuits, Shift registers

Abstract: The paper describes a method of designing counter registers. Two important features of the methodarc that it produces a minimal design and that it is guaranteed to avoid jamming. The method may be appliedto the synthesis of any counter registers used, for example, as binary-sequence generators, word generators,counters, pseudorandom binary-sequence generators etc. The paper contains examples which demonstratethe design procedure, and gives some results relating to minimal counter registers.

1 Counter registers

A counter register is a shift register with a feedback circuitas shown in Fig. 1. The output of the feedback circuit,

Paper T337C, first received 11th September 1978 and in revisedform 8th January 1979Prof. Wagner is with the Instytut Elektroniki, Politechnika Slaska,ul. Pstrowskiego 16,44 — 101 Gliwice, Poland

which is a function of the register outputs Qn _,, Qn _ 2 , . . . ,Qo, forms the serial input to the shift register. The serialinput of the register is a flip-flop, usually J-K or D type.Another name for a counter register of this type is a 'feed-back shift register'.

Counter registers find many applications. They are usedas counters (e.g. ring counters, Johnson counters) because

70

0140-1335/79/020070 + 05 $01.50/0

COMPUTERS AND DIGITAL TECHNIQUES, APRIL 1979, Vol. 2, No. 2

of simple decoding. Linear registers are also used to gen-erate pseudorandom binary sequences. Another frequentuse for counter registers is as sequence and timing gener-ators.

The synthesis of linear registers is well known and dis-cussed in many publications.2 In fact, if we want to builda pseudorandom binary-sequence generator we use tableswhere we find the switching function of the feedbackcircuit (in the form of the modulo-2 sum of several re-gister outputs). This is shown in Table 1.

The method presented in the paper may be applied tothe synthesis of any counter register.

2 Self-starting problem in counter registers

When designing counter registers, we have to calculate thenumber of shift-register stages and find the switchingfunction of the feedback circuit. The main problem whenapplying counter registers is the problem of nonpermissiblecycles or states. The counter register which can be guaran-teed to switch from a nonpermissible cycle (state) to apermissible cycle is called a self-starting counter register.The synthesis of the switching function of the feedbackcircuit must take into account the self-starting problem.

The problem is solved by proper interpretation of the'don't care' states. The 'don't care' states in sequentialcircuits differ from those in combinational circuits. 'Don'tcare' conditions are such conditions for which we havechosen not to specify the response of the circuit on theassumption that they do not arise in practice. 'Don't care'conditions can be used to reduce the circuit equationsand, hence, the complexity of the circuit. When designingsequential circuits we have to be more careful in takingadvantage of 'don't care' states. There is always the possibi-lity that the sequential circuit will find itself in an unusedstate (e.g. after switching the power supply on). This caseoccurs frequently in counter registers.

3 The method of synthesis

The method consists of the following steps:(a) Write a binary number which corresponds to the

required output; this may represent a timing diagram orbinary sequence. Write the number in the form of a column.

(b) Construct a Table as follows. Immediately to theright of the column, write the column a second time butshifted one bit position cyclically downwards. Repeat theprocess, testing after each new column is added, to seewhether the binary numbers formed by the rows of theTable are all different. As soon as they are, stop the pro-cess. The numbers form the state sequence correspondingto the binary sequence (see Appendix 7.1).

(c) Using the first column (i.e. the most significant bitof the shift register) and the state sequence, build thetruth table for the T and/or D serial input of the shift re-gister. For a T input stage, write 0 if the next state of them.s.b. does not change, and write 1 if it does change.For aZ) input stage, write the next state of the m.s.b.

(d) Build Karnaugh maps for the T and D signals. If theall-0 and all-l states in the Karnaugh maps are not used,complete the maps by writing Is in both cases in the mapfor the T signal, and 1 for all Os and 0 for all Is in the mapfor the D signal (see Appendix 7.2). To get3"4 the Karnaughmap for the / signal, write the 'don't care' states for m.s.b. =1 in the map for T signal, and for the K signal, write the'dont't care' states for m.s.b. = 0 (see Appendix 7.3).

COMPUTERS AND DIGITAL TECHNIQUES, APRIL 1979, Vol. 2, No. 2

Table 1: Feedback functions for linear registers

n Switching function of feedback circuit

3 O0@Ql

4 Q0®Q.5 Q0®Q26 Q 0 ®Q.789

101112131415 o . a16 Qo ® Q4 © Q 1 3 © Q1S

QoQo

Qo

Q°o

Q!

® Q ,

:i®Q1 4

® Q

. 0

l a

C

feedbackcircuit

clock input —

ii

0

J-K (D) s n i f t

C register

Fig. 1 Counter register

n . i—i •

Fig. 2 Periodic square wave for example 1

(e) Write the switching functions for T, J, K and/or Dsignal, and choose the simplest solution.

(f) Draw a state diagram to check whether the circuit isself starting. If it is not, complete the questionable statesin the Karnaugh maps and repeat steps (e) and (f).Example 1: Design a circuit which generates the periodicsquare wave shown in Fig. 2.

Following the above-described algorithm we get:

(a) (b) m.s.b.

000010011

(c)

000010011

100001001

State

63108429

12

100021023

000010011

000010011

T

000110101

100001001

110000100

D

000100110

310042146

Q3000010011

Q2l00001001

QiIl0000100

Qo011000010

6310842912

71

(d) See Fig. 3

T=Q2Q0+Q3Q2

J = Q7Q0

K = Qo

D = Q3Q2Q0+Q3Q2Q0 = Q2Q3®Qo

The simplest solution is given by the equations for / andA'.

(f) The state diagram of the counter register with thefeedback circuit described by the / and K switching func-tions is shown in Fig. 4a. Because the state diagram showsthat the counter register is self starting, the job has beenfinished, and Fig. 4b presents the scheme of the circuit.

Q1 Qo Qi Qo00 Oi n 10

00Q 0 00 01 u 10 Q,Q.

3 Q 2

1

00

V,ft

0 1

0

0 1 3

0u12

8

2 T3

1

0

0

0

0

1

0

0

1

0 U

12

8

0 1 3 2 D3

Fig. 3 Karnaugh maps for example 1

J QCK 0

socR Q

0-2

S QCRQ

S QCRQ

they are seen to be very similar, and when realising thecircuit using NOR gates, both solutions use the samenumber of gates. However, the solution in Reference 1is not self starting; the circuit sticks in the all-Os state.To overcome this, Reference 1 suggests decoding the all-Osstate and introducing the decoder output signal into thefeedback circuit.

Another example is shown in Fig. 6. The well knownfeedback functions for linear registers (see Table 1) alwaysgive circuits which stick in the all-Os state. However, thefunction given by the method presented here is guaranteedto avoid this problem. The scheme for a 4-bit linear registeris shown in Fig. 6b.

22115189U217242830157192512

Q4Q3Q2Q1Q0

10 1100 10 110 0 10 110 0 100 10 0 10 0 10 0 0 110 0 0110 0 01 1 1 0 01 1 1 1 00 11110 0 11110 0 11110 0 1

1 0 0

0 001

0 1

Q , Q 0

Q/.ChCKOOOl 11 10J8oJ001011010110111101100

Q1Q000 01 11 10

0 1 3 2

0010110101 10111101100

J(JV11

•J

00

1

1.

00

0

1

1;

000

clock

Fig. 5 Example 2

a Truth tableb Karnaugh maps

Fig. 4 Example 1

a State diagramh Circuit

Example 2: Design a circuit which generates serially-by-bitthe following sequence of binary numbers: 9 ,8 ,7 ,6 . '

Fig. 5 presents in condensed form the design procedure.The shaded area of the Karnaugh map for the T signalcorresponds to the most significant bit (?4 having thevalue 1. Hence, the map for the T signal may be used asthe map for the J and K signals.

Comparing the result

D = Q3Q0 + Q3&Q0+Q4Q3Q7

with the solution in Reference 1

D = Q3Q0 +G3G1G0+G4G1G0

D4 =Q3Q0_+Q

c State diagram

Fig. 6 Linear register

a Without self-starting featureb With self-starting feature

72 COMPUTERS AND DIGITAL TECHNIQUES, APRIL 1979, Vol. 2, No. 2

Table 2: Number of s-state codes generated by an n-bit counterregister

23456789

10i111213141516

79786

11168

Table 3: Switching functions of the feedback circuit for 2-bitcounters modulo-s

J K Code

1-0-21-0-2-3

Table 4: Switching functions of the feedback circuit for 3-bitcounters modulo-s

K Code

3_1_0-4-63_1_0-4-6-73-1-0-4-2-5-63-1-0-4-2-5-6-7

Table 5: Switching functions of the feedback circuit for 4-bitcounters modulo-s

K Code

9 Qo

10 Qo

12 Q , < B Q 0

13 Qo

14 QQ+Q2

15 Qo

16 Qo

Q ® Q1 0

Q 2 © Q o

~QT~+~QO

Q2 ®Qo

Qn + (Q

Q2Q0

7-3-1-0-8-4-10-13-147-3-1-0-8-4-10-

13-14-157_3_1_0-8-4-2-9-

12-14-157-11-5-2-1-0-8-4-

10-13-14-157-3-1 -0-8-4-10-5-2-9-12-14-157-3-1-8-4-10-5-2-9-12-6-11-13-147-3-1-0-8-4-10-5-2-9-12-6-11-13-147-3-1-0-8-4-10-

13-6-11-5-2-9-12-14-15

4 Minimal counter registers

There are many applications for counters other than purebinary ones,e.g. decade counters using b.c.d. representation.In those cases, the counter register might be the bestsolution, considering its simplicity and speed of operation(the counter register is the fastest type of synchronouscounter).

The number of different codes that can be generatedby a counter register of given length has been calculated,6

and some of the relevant results are presented in Table 2.The codes included here are only those that satisfy therule that an n-bit counter is used to count modulo-p, where

2""1 + 1 < p < 2 "

The switching functions of feedback circuits for all 2-, 3-and 4-bit counter registers have been calculated, and thesimplest (minimal) solutions are presented in Tables 3—5.The counters are self starting. By removing the expressionsin the brackets, one gets simpler solutions, but without theself-starting feature.

5 Conclusions

The method of designing counter registers presented in thepaper always leads to the minimal solution. Proper inter-pretation of the 'don't care' states for all-Os and all-Isstates in the Karnaugh map for the serial input signal ofthe shift register always gives circuits which are self startingand need no antilocking logic. In very rare cases, someother 'don't care' states must be considered. Example 2provides a good ilustration of the method; proper valuesin the all-Os and all-Is states give a solution with a self-starting feature which is comparable to a known solutionwithout such a feature.

6 References

1 MORRIS, R.L., and MILLER, J.R.: 'Designing with TTLintegrated circuits' (McGraw-Hill, New York, 1971), pp. 304-305^

2 GOLOMB, S.W.: 'Shift register sequences' (Holden Day Inc.,San Francisco, 1967)

3 WAGNER, F.: 'Electronic counters in industrial controlcircuits' (in Polish, WNT, Warszawa, 1971)

4 WAGNER, F.: 'Uber die Synthcse synchroner Zahler', Elvktro-nikpraxis, 1971 11, pp. 7-9

5 WAGNER, F.: 'Counter-register codes'(in Polish), ArehiwumAutomatyki i Telemechaniki, 1976, 2, pp. 225 232

6 WAGNER, F.: 'Designing short counter-registers' (in Polish),Zeszyty Naukowe Pol. SI, 1977, p. 526

7 WAGNER, F.: 'Binary and state sequences generated bycounter-registers', Digital Processes (to be published)

7 Appendixes

7.1 Basis of the design methodLet a,- represent the state of the output from a counter-register stage. Then, the operation of the counter registermay be described by Table 6:5'7

Table 6: Operation of counter register

3 c . •

n columns

The columns of the Table represent the binary sequences atthe counter-register outputs. The first column of the Tabledescribes the Qn-X output, the second, the Qn-2 output,the last, the Qo output. Therefore, the Table contains ncolumns, where n is the number of counter-register outputs.

The rows of the Table define the states of the counterregister; their number is equal to s.

The Table corresponds to a real circuit if all states(binary numbers formed by the rows) are different. This isthe necessary and sufficient condition for a sequentialcircuit to be realisable.

COMPUTERS AND DIGITAL TECHNIQUES, APRIL 1979, Vol. 2, No. 2 73

The relation between the register states and the registeroutputs can be written in the form of a set of equations:

1 ar

2n~xar

= *n

= xn+l

where xn represents the register state as a decimal value ofthe binary number defined by the nth row of the Table.

Consider any two of the above equations:

IfX{ ~ Xk

then

at = ak

For a given s one could test for all p < s whether theexpression (2s — 1)/(2P — 1) is an integral number. If itis, then subdivision into p identical parts may be possible.

For example, for s = 1 2 , (212 - 1)/(2P - 1 ) is anintegral number for p = 2,3,4 and 6. Therefore, a 12-statebinary sequence may consist of 2-, 3-, 4- and 6-state parts.

From a practical point of view, the question of whetherthe sequence consists of identical parts would normallybe answered by visual inspection. For example, the 9-statesequence 101101101 is immediately seen to consist ofthree 101 sequences and would be realised as a 3-bit se-quence.

7.2 'Don't care' states and the self-starting methods

The self-starting problem in counter registers may be solvedby an analysis of all 'don't care' states in the Karnaugh map.The analysis enables one to determine whether a given'don't care' state may be safely treated as such or whetherit should have a definite value of 0 or 1 assigned to it. Suchcorrection always results in a self-starting circuit. However,this precedure is rather awkward.

There are two states, all-Os and all-Is, in the Karnaughmap, for which the correct values of D or T signals areidentical for all counter registers. The circuit leaves thesestates for the following values of D and T signals:

D

T

00

1

1

.0 11

0

1

1

This explains the special treatment of these two states.Experience show that this condition is always sufficient tomake the circuit self starting. Only in very rare cases mustthe Karnaugh map be further corrected by examining other'don't care' states.

i.e. corresponding elements of the two binary sequences kand / must always be equal.Hence, it follows that

(a) The shift-and-add method produces a realisablesolution as long as the binary sequence cannot be sub-divided into two or more identical parts.

(b) If condition (a) is fulfilled, the realisation of thecircuit demands a register with at most (s — 1) outputs.When condition (a) is not fulfilled, the output sequencecan be written in the following form:

L = A + 2PA + 22pA + . . . + 2(S/P~1)PA

where

L is the sequence expressed in the form of a binarynumber

A is the portion of the sequence that is repeatedp is the number of bits in the repeated portion

Summing the above series

2 s - 1L = A

2P -

It is thus possible to introduce an algebraic conditionwhich tests whether or not subdivision of the sequence ispossible:

7.3 Relationships between J-K signals and T signals

Comparing the excitation Tables for T and J-K signals:

0

0

l

I

0

l

0

I

0

1

1

0

40

1

-

—

Kk

—

-

1

0

where — signifies the 'don't care' condition, it is seen that

Jk = Tk for Qk = 0

and

Kk = Tk for Qk = 1

This means that to get the Karnaugh map for Jk signals,take from the map for the T signal only conditions definedfor Q" = 0; the area where Qn = 1 consists of 'don't care'states. For the K signal, on the other hand, write the 'don'tcare' conditions for the area where Qn = 0.

74 COMPUTERS AND DIGITAL TECHNIQUES, APRIL 1979, Vol. 2, No. 2