Register and Counter Design
description
Transcript of Register and Counter Design
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Register and Counter Design
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Registers in the Basic Computer
• Registers are basic building blocks in digital systems.– store information– auxiliary circuits may modify stored
information or “steer it” to and from register
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Registers and Counters
A register is a set of flip flops, often supplemented by additional circuits to control input and output.
- can have parallel I/O or serial I/O or combinationUsually, registers are used to store a set of related
bits.-bits that collectively represent an integer value
- bits of an ASCII character code -status bits for a device in a computer system (disk
controller)
Counters are registers that store numeric values alongwith circuits to increment/decrement the stored value.
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counters
- up-counters, down-counters, up-down counters
- generalized counters- BCD counters, gray-code counters, ...
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Simple Parallel Load Register
Four bit register» if LD is high when clock
rises, new values are stored» LD should change only while
CLK is highRegisters using gated
clocks• can lead to timing
problems.• increases clock skew• may lead to violations of
flip-flop setup, hold time specs
• extra care needed to ensure correct operation
• safer to avoid clock gating whenever possible
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Preferred Parallel Load Register
Multiplexer for each register bit.
» new value loaded when LD is low otherwise, old value stored, No gated clock,
- minimizing clock skew.» simplifies checking of
setup and hold time specs.
» can focus on delays between connected flip flops Increases gate count by about 30%.
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4-bit Shift Register
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2-bit Register
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Serial-in-serial-out Shift Register
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Design of SR FFlibrary ieee;use ieee.std_logic_1164.all;entity ff is
port ( s,r : in std_logic;q,qbar : out std_logic
);end ff;architecture behave of ff isbegin
processbegin
if (s = '0' and r = '0') thenq <= '1';qbar <= '0';
elsif (s = '0' and r = '1') thenq <= '0';qbar <= '1';
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SR FF (cont..)
elsif (s = '1' and r = '0') then
q <= '1';
qbar <= '0';
else
q <= '0';
qbar <= '0';
end if;
end process;
end behave;
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D-flip flop
library ieee;use ieee.std_logic_1164.all;
entity dff isport (d, clk : in std_logic;
q, qbar : out std_logic);
end dff;
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architecture behave of dff issignal temp : std_logic;begin
process (clk)begin
if (clk'event and clk = '0') thentemp <= d;
end if;q <= temp;qbar <= not temp;
end process;end behave;
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SR flip-flop (process)
library ieee;
use ieee.std_logic_1164.all;
entity ffclk is
port ( s,r,clk : in std_logic;
q,qbar : out std_logic
);
end ffclk;
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architecture behave of ffclk issignal temp,tempbar : std_logic;begin
process (clk)begin
if (clk = '1') thenif (s = '0' and r = '0') then
temp <= '1';tempbar <= '0';
elsif (s = '0' and r = '1') thentemp <= '0';tempbar <= '1';
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elsif (s = '1' and r = '0') thentemp <= '1';tempbar <= '0';
elsetemp <= '0';tempbar <= '0';
end if;else
temp <= temp;tempbar <= tempbar;
end if;q <= temp;qbar <= tempbar;
end process;--q <= temp;--qbar <= tempbar;
end behave;
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counter
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity counter4bit is
port (load,clear, clk : in std_logic;d : in std_logic_vector (3 downto 0);q : out std_logic_vector (3 downto 0)
);end counter4bit;
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architecture behave of counter4bit issignal temp : std_logic_vector (3 downto 0);begina:process (clk,load,clear,d)
beginif (load = '1') then
temp <= d;elsif (clear = '1') then
temp <= "0000";elsif (clk'event and clk = '1') then
temp <= temp + "0001";else
•
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temp <= temp;end if;
end process a;q <= temp;
--b: process (clk)--begin
--if (clk'event and clk = '1') then--q <= temp;
--end if;--end process b;
end behave;
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With second process (b)
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Serial-in-parallel-out Shift Register
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Synchronous Counter
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Ring Counter
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Up/down counterlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;-- up/down counterentity counterupdown is
port (load,reset, clk : in std_logic; -- control signaldir : in std_logic; --
directiond : in std_logic_vector (3 downto 0);q : out std_logic_vector (3 downto 0)
);end counterupdown;
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architecture behave of counterupdown isbegina: process (clk,reset,d)
variable temp: std_logic_vector (3 downto 0);begin
if (clk'event and clk = '1') thenif (reset = '1') then
temp := "0000";elsif (load = '0') then
temp := d;else
if (dir = '1') thentemp := temp + "0001";
else temp := temp - "0001";end if; end if;
end if; q <= temp;end process a; end behave;
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Waveform (up/down counter)
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Binary counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity binarycounter is
port (clk : in std_logic;
q : out std_logic_vector (3 downto 0)
);
end binarycounter;
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architecture behave of binarycounter issignal temp : std_logic_vector (3 downto 0);begina:process (clk)
beginif (clk'event and clk = '0') then
temp <= temp + "0001";end if;q <= temp;
end process a;end behave;
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Waveform (binary counter)
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Mod 2 counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mod2 is
port (clk : in std_logic;
q : out std_logic_vector (3 downto 0)
);
end mod2;
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architecture behave of mod2 issignal temp : std_logic_vector (3 downto 0);begina: process (clk)
beginif (clk'event and clk = '0') then
if (temp = "0010" ) thentemp <= "0000";
elsetemp <= temp + "0001";end if;
end if;q <= temp;
end process a;end behave;
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Waveform (mod 2 counter)