Design of a Radiation-Hardened Curvature Compensated Bandgap Reference Circuit

Subtitle as needed (paper subti

António Manuel Gomes Negrita Fitas Instituto de Telecomunicações

Instituto Superior Técnico Lisboa, Portugal

antonio.fitas@gmail.com

Nuno Horta Instituto de Telecomunicações,

Instituto Superior Técnico nuno.horta@lx.it.pt

Jorge Guilherme

Instituto de Telecomunicações, Instituto Superior Técnico

jorge.guilherme@ipt.pt

Abstract—The work presented in this paper belongs to the scientific area of electronic design and dimensioning of analog integrated circuits, more specifically the design of a bandgap voltage reference (BGV) generator with 2nd compensation. The developed circuit provides a steady voltage at the output, stable to noise, temperature and power source drifts, which works as a reference voltage for other circuit blocks. The main purpose of the work is to obtain a BGV generator of a voltage of 1.25V with a performance that can surpass a circuit previously. The FOM that primarily characterize the circuit and that will be the focus of improvement are the PSRR, the TC and the current consumption. The results achieved by the circuit in this paper are a PSRR of -81.93 dB, a TC of 2 ppm/ºC and a current consumption of 2.34 mA.

Keywords—Analog Integrated Circuits Design; CMOS: Voltage Referenceres; 2nd Order Compensation Bandgap Voltage References.

I. INTRODUCTION In analog and digital ICs there are blocks, which the

purpose is purely to generate a reference DC voltage or current that can be used by different other blocks. This reference should not fluctuate significantly under various operating conditions, such as moving temperature or power supply and process, to enable other circuits to generate predictable and repeatable results. Instituto de Telecomunicações at IST proposed as Master Thesis the redesign of a BGV generator, a reference circuit that is specially design to produce voltage independent of temperature variations. By having well characterized temperature dependent voltages and currents, one can manipulate these to produce an adjusted compensated response, categorized according to the curvature degree of compensation. It is expected a 2nd Order Bandgap Voltage Reference Generator design to be achieved.

This paper is organized as follows: Section II presents the background to BGV design. Section III describes the proposed circuit. Section IV discuses the simulation results and in section V the conclusions are drawn.

II. BANDGAP VOLTAGE REFERECE The BGV achieves the temperature independence by

cancelling the negative temperature dependence of a PN junction with a positive temperature dependence from a PTAT circuit, characterized in Figure 1.

Figure 1 Contrasted voltage independent components

waveform - VCTAT and VPTAT – and reference waveform – VREF.

The metric used to evaluate the fluctuations of the voltage across the temperature is expressed in equation (1).

𝑇𝐶!"# =!

!"#"$"%&"!"#$#%#&'#

!"#$%#&'()&#×10! 𝑝𝑝𝑚 ℃ (1)

A. PN junction Due to its well-known dependence with the temperature

and high availability in ICs, the PN junction is the main choice to produce the reference. The junction can be extracted from a forward-biased diode or base-emitter junction in a PNP transistor[1].

The diagram in Figure 2 is the most universally used blueprint to produce a BGV generator using a PNP transistor and can be a representation of several different topologies. The PTAT voltage is achieved by amplifying the voltage difference between two base emitter junction and the CTAT from a single base-emitter junction.

Figure 2 Diagram BGV temperature compensation

mechanism.

The base-emitter voltage can be written as a function of its collector current and temperature as shown in equation (2), where 𝑇 and 𝑇! represent the temperature, 𝐽! and 𝐽!! the collector current density, 𝑉!" and 𝑉!"! the base-emitter voltages, 𝑚 and k are a BJT temperature constant and Boltzmann’s constant correspondingly and 𝑉!! ≈ 1.206 𝑉 the extrapolated bandgap voltage at 0℃ which gives the name to the circuit. The 0 index in 𝑇!, 𝐽!! and 𝑉!"! represent the values at the reference temperature.

𝑉!" = 𝑉!! 1 − !!!

+ 𝑉!"!!!!+ !"#

!𝑙𝑛 !

!!+ !"

!𝑙𝑛 !!

!!!

(2)

The obtained PTAT is an amplified difference of two 𝑉!" biased at different collector current densities as shown in (3) where 𝑉! =

!"!

is the thermal voltage.

∆𝑉!" = 𝑉! − 𝑉! =!"!ln !!

!! (3)

Adding equation (2) and (3) results in the out reference, shown in (4).

𝑉!"# = 𝑉!! +!!!

𝑉!"!!! –𝑉!! + 𝑉!"!!!!+

!"#!ln !

!!+ !"

!ln !!

!!!

(4)

By making 𝜕𝑉!"# = 0 at the reference temperature 𝑇 = 𝑇!, the equation (5) emerges where the left is 𝑉!"# at 𝑇! leading to the right side being approximately 1.24𝑉. This value can be tuned by suiting the gain 𝐾 and the current densities.

𝑉!"! + 𝐾!!!ln !!

!!= 𝑉!! + 𝑚 − 1 !!!

! (5)

B. Curvature Compensation To achieve higher accuracy in bandgap reference circuits, it is essential to implement a higher order compensation type, being the most common the 2nd order correction also called curvature compensation, where in addiction of cancelling first order components of the BJT base-emitter voltage, there is also an attempt to approximately eliminate the second order terms. Some of the most known 2nd order correction techniques [2] that could be applied to BGV circuit are:

• PTAT2: compensate the negative temperature dependence of the logarithmic term in 𝑉!" with a positive parabolic term – example of waveforms in Figure 8;

• Temperature dependent resistor: exploit the temperature dependence of the resistors as a factor of correction;

• 𝛽 compensation: manipulate the forward-current gain 𝛽 to address the non-linear behavior of the diode voltage, as 𝛽 ∝ 𝑒!

!!.

• Piecewise-Linear Current Mode: generate a piecewise-linear current signal to correct selected parts of the reference voltage.

Figure 3 Waveform representation of PTAT2 2nd order

correction.

III. PROPOSED CIRCUIT The proposed circuit was an adaptation on the circuit

proposed in [3]. The fact that its results exceeded the threshold imposed and that the design endures the modifications needed for radiation-hardness requirements made the circuit a good candidate for implementation.

The basic 1st order bandgap circuit is presented in Figure 4. The CTAT current is achieved when forcing the voltages 𝑉!"# and 𝑉!"# due to the amplifier virtual short circuit producing a current flowing in the same value resistors 𝑅! and 𝑅!, which is proportional to 𝑉!" as seen in equation (6).

𝐼!"#" = 𝐼!! =!!"!!

(6)

Figure 4 1st order BGV circuit.

The current that passes through 𝑅! and through the PNP transistor has the desired PTAT characteristic, described by equation (7).

𝐼!"#" = 𝐼!! =!! !"!!!

(7)

The current that is mirrored by the MOS current mirror composed by 𝑀!, 𝑀! and 𝑀! is the sum of the PTAT and CTAT. If taking into account the effect of the operation amplifier offset, 𝑉!", the reference voltage is the current passing through 𝑅!, expressed by (8).

𝑉!" = 𝐼!𝑅! = 𝑅! !! !"!!!

+ !!"!!+ 𝑉!" (8)

A. Operational Amplifier The amplifier used in the implementation was a 2 stage OTA with Miller [4] compensation due to its high impedance at the input that makes this topology suitable for the feedback assembly. The Figure 5 represents the OTA circuit.

Figure 5 2 Stage OTA with Miller Compensation circuit.

B. Bias Generator The objective of the bias generator is to create the current bias of the OTA and the voltage to the cascade stage implemented in the current mirror, in order to decrease the noise injected in the circuit through the power source. The circuit, represented in Figure 6, receives the general available to every circuit bias current and adjusts this current through the MOS ratios to the desired value of the OTA bias current.

Figure 6 Bias generator circuit.

The voltage provided to the cascade stage is generated by adjusting the dimensions of the 𝑀!"#$ transistor that is

working in triode region while the current that passes through 𝑀!"#$ is fixed at the bias current value.

C. Startup Circuit The non-linear current-voltage relationship of a diode connected BJT and a N times larger diode connected BJT with a resistor in series has two crossing points that represent its stable points. One of those stable points is when there is no current in the circuit and to ensure that the circuit does not stabilizes at that point, there is the need to implement a startup circuit. The startup circuit proposed is represented in Figure 7.

Figure 7 Startup Circuit.

The function of the proposed circuit is explained next: the current of the BGV is mirrored into 𝑀!!, thus, in case of the circuit preserves in the no current state, the voltage at 𝑅!! at a a low level. This will make the voltage at the exit of inverter 𝐼! to pull the gate of 𝑀!! to the ground, making a short-circuit of the node at the exit of the amplifier to the ground – this action causes the mirror to flow some current translating the stable point to the desired. As the current starts flowing, the resistor 𝑅!! voltage at a high level will make the exit voltage of 𝐼! to shut 𝑀!! and stop the startup mechanism. This method has no influence in the voltage reference, as there are no injections in the main branches that compose the reference output.

D. 2nd order implementation The 2nd order compensation circuit is inspired in the solution introduced in [5] and is represented in Figure 8. The correction is done by sampling the already created CTAT and PTAT current and passed them through a new BJT, 𝑄!. The objective is to correct the terms by subtracting the 𝑉!" obtained from a junction with a PTAT current from a junction with the constant current and the 𝑉!" obtained from a junction with a PTAT current. The current in transistor 𝑄! it PTAT while the current in 𝑀! is almost temperature independent, therefore, if the current mirrored is injected in 𝑄! it is generated a 𝑉!" with constant current. Resistors 𝑅!!"# and 𝑅!!"# will drain an additional current from 𝑀! and 𝑀! proportional to the above mentioned 𝑉!" difference that balances the output curve.

Figure 8 2nd order correction circuit.

E. Radiation-Hardness Since the circuit purpose is to be implement in a IC for a aerospace application, some particular attention on the radiation was required when designing the layout:

• Every current branch needed at least 10𝜇𝐴 to avert radiation turbulence;

• The isolation field oxide around MOS devices is narrow enough to the point that radiation could induce adverse effects in those components. A special transistors type called ELT [6] was used to halt the negative reactions to radiation in typical MOS.

IV. SIMULATION RESULTS The full circuit is tested in typical, 40 different corner cases

and Monte Carlo statistical simulations. The tools used includes the Mentor Graphics Eldo© as the simulator selected to evaluate the circuit, which includes the graphical waveform environment EZwave™, version 13.1, the Cadence® Virtuoso: Schematic Editor + Simulation Environment and AIDA-C, a state-of-the-art analog IC sizing and optimization tool [15].

A. AIDA-C AIDA-C is an optimization tool developed in Instituto de Telecomunicações at Instituto Superior Técnico. AIDA-C targets the sizing of the devices in analog circuits and it is based in multi-objective multi-constraint optimization techniques and addresses robust design requirements by taking into account worst cases corners. The tool requires that the user provide a netlist of the circuit and a setup XML file where the testbench, constraints and simulation options are configured. AIDA-C has a graphical interface where it is possible to follow the evolution of the optimization and also do single and parametrical simulations. The best solutions for each iteration of the optimization, feasible or not regarding the defined constraints, are presented graphically. The solutions that comply with the constraints are represented in a Pareto Optimal Front like in Figure 9.

Figure 9 Example of a POF of the OTA with objectives “max.

PSRR – min IDD”.

B. BGV with Compensation Results The Table 1 contains the result for the major metrics used

to evaluate the performance of the circuit.

Table 1 Summarize performance of the 2nd Order BGV implemented.

Measure Results

Typical Worst Case Corner 𝑇𝐶 [𝑝𝑝𝑚/℃] 2 10.991 𝑉!"#[𝑉] 1.249 1.247/1.251 𝐼!![𝑚𝐴] 0.737 0.962 𝑃𝑆𝑅𝑅[𝑑𝐵] -84.406 -81.926

1. Output Voltage

The output voltage for typical results is presented in Figure 10, showing the expected waveform for a bandgap with 2nd order correction. The voltage range is about 0.1𝑚𝑉, from 1.2949𝑉 to 1.2489𝑉.

Figure 10 Output BGV Voltage waveform in the typical

conditions.

The Figure 11 displays the graphical results of the statistical analysis of Monte Carlo simulations. The mean value for the temperature coefficient is 23.29𝑝𝑝𝑚/℃ with a standard deviation 𝜎 = 17.63𝑝𝑝𝑚/℃.

Figure 11 Output BGV voltage waveforms for Monte Carlo

simulations.

1) Stability The approach adopted to simulate the stability of the circuit and the effectiveness of the startup circuit is the Unique DC Operating Point test. This test consists in opening the startup control loop and entering a sweeping voltage source that would activate the startup mechanism and then turn it off. By maintaining the state, is shown that the circuit is stable after disconnecting the startup and that the circuit functioning will not slip to other point of operation. The Figure 12 presents the results of the test for the Corners case.

a)

b)

Figure 12 a) Output BGV voltage for the Unique DC Operating Point simulation output. B) Control voltage source

at the startup input.

2) Power Down mode The power down mechanism was implemented in the circuit. The results are presented in Figure 13 and the simulation consisted in switch on the Enable signal with an arising time of 100𝑚𝑠 and after 2.5 seconds, the Enable signal is switch off with a decreasing time of 100𝑚𝑠.

Figure 13 Output BGV voltage for Power Down simulation

in corners conditions.

3) PSRR An AC simulation where is possible to get the PSSR results in Corners cases, at the frequency of 1Hz, are presented in Figure 14.

Figure 14 Output BGV voltage in frequency for Corner

cases.

4) PTAT, CTAT and Correction Currents Observation In Figure 15 there is a representation of the currents that summed comprise the BGV reference voltage, where the red curve corresponds to the CTAT current flowing through 𝑅!, the yellow curve to the PTAT current flowing through 𝑅! and 𝑅!, the orange curve to the current flowing through the resistor 𝑅!, the blue curve to the current glowing through the BJT in the 2nd order branch and the green and purple curve to the current flowing through the resistor 𝑅!!" and 𝑅!!" correspondingly. When inspecting the orange curve of the current that flows through 𝑅! it is possible to conclude that the resistors have a large impact on the design. It is expected that this curve would be already temperature independent and would be proportional to the voltage curve, which is largely independent to temperature. However the current is already compensating the resistor temperature influence and that is why the current does look unsteady regarding temperature variations.

Figure 15 Behaviors of the currents that generate the BGV

voltage.

5) Comparison with 1st Order Results Comparing the results obtained with the circuit developed

without 2nd order compensation with the results with 2nd order compensation leads to the conclusion that the compensation has great effects in improving the temperature compensation. The normalized curves at the desired reference temperature 1.25𝑉 are displayed in Figure 16 where the 1st order curve has a temperature coefficient of 10.28 ppm/℃ and it is much more wider that the 2nd order curve.

As the correction names indicates, the 1st curve resembles a quadratic function and the 2nd order curve a third degree function – the dominant 2nd order component is not present anymore.

Figure 16 1st order BGV output curve – blue – and 2nd order

BGV output curve - orange.

V. CONCLUSIONS The work presented in this thesis accomplished its principal

objective of designing a complete BGV circuit with 2nd order correction, with a two stage OTA with Miller Compensation, a Startup circuit, and a Bias Voltage and Current. The results obtained are in line with the other BGV circuits developed found during the study of the state-of-the-art, as shown in Table 2.

Table 2 Comparisons of 2nd order BGV circuits.

Ref. Performance

𝑽𝑹𝒆𝒇 [𝑽] 𝑻𝑪 [𝒑𝒑𝒎/℃] PSRR[dB] Technology [7] 2.6 7 -90 CMOS 0.8 𝜇𝑚 [8] 0.858 12.4 -69 CMOS 0.35 𝜇𝑚 [9] 1.24 8.36 -100 CMOS 0.18 𝜇𝑚

[10] 0.82 16.62 -95.56 CMOS 0.18 𝜇𝑚 [11] 1.66 48.7 -74 CMOS 0.18 𝜇𝑚

This work 1.249 2 -84.406 CMOS 0.35 𝜇𝑚

AIDA-C proved to be an useful tool that can be easily integrated in the designer’s workflow and can even be considered a pivotal point the dimensioning of the circuit without replacing the role of the designer in the development of an IC. It is principally powerful when the fine-tuning of the circuit is performed, reducing the time of a tedious a not so glorifying task. The tool also settled as a great environment for manual dimensioning, where it is possible to perform parametric sweep simulations and verify constraint infractions for metrics of the circuit.

A. Future Work The intention is that for the future the work developed in

this thesis is extended. As a suggestion:

• Broaden the validation of the stability of the circuit can be an interesting point. This can include implementing the methods presented in [12] and [13];

• Achieve a trimming section for post-fabrication tuning of the resistor values;

• Introducing chopping techniques [14] in the OTA which decreases the noise and the offset voltage of the amplifier.

ACKNOWLEDGMENT Would like to acknowledge my supervisors Doctor Nuno

Horta and Doctor Jorge Guilherme for the guidance during the developing of this work. Thanks to the IT Analog Integrated Systems team, especially to Ricardo Póvoa and Nuno Lourenço. Thanks to my family and friends for the support and boost.

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