Design of a CMOS Current Conveyor-Based

Field-Programmable Analog Array

Vincent Charles Gaudet

A Thesis submitted in confomity with the requirements

for the degree of Master of Applied Science in the

Graduate Department of Electrical and Cornputer Engineering

University of Toronto

O Copyright by Vincent Charles Gaudet 1997

395 Wellington Street 395, nie Wellington Ottawa ON KI A ON4 Ottawa ON K I A ON4 Canada Canada

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Vincent Charles Gaudet

Master of Applied Science, 1997

Department of Electrical and Cornputer Engineering

University of Toronto

Abstract

To date, al1 published CMOS field-programmable analog array (FPAA) designs have operated

under lMHz bandwidths. This thesis develops circuit methods allowing the development of a

CMOS FPAA operating at greater than lMHz frequencies. For this purpose the second-

generation current conveyor (CCII) is used. IC test results of a O.8p-n CMOS chip containing

four configurable analog blocks based on the CCII, as well as an interconnection network

based on transmission gates, are presented. The test results show that bandwidths exceed

IOMHz. The four CABS and interconnect occupy a core area of 1551.8 x 741.2pm2. The

thesis also proposes an FPAA design based on current conveyors and similar to a commercial

bipolar FPAA, but operating at higher bandwidths; as well, a novel voltage comparator based

on the CClI is proposed.

Many people and organizations have helped me on the road to where 1 am today. There is no

space on this page to thank them all, but I do wish to mention a few.

I wish to thank my supervisor Professor Glenn GuIak for his assistance and flood of great

ideas. It has been a privilege and a pleasure to work with him and 1 am looking fonvard to

collaborating with him in the future.

Continued financial support from NSERC, Micronet, and ITRC, as well as fabrication support

from CMC are much appreciated.

1 also want to thank al1 my friends and colleagues in LP392 and the EECG, and wish them

well in Our chosen field. Included are Ali, Andy, Aris, Aron, Billy, Dave, Jarnil, Jason A.,

Jason P., Javad, Jeff, Jordan, Keith, Ken, Khalid, Marcus, Mark, Mazen, Nirmal, Qiang, Silas,

Steve, Vaughn, Wai Ming, Warren, and Yaska.

I wish to thank Christophe, Dean, Khoman, and Bryn for their technical advice and assistance,

and Peter, Fred, and Jaro for being there when 1 needed them.

My gratitude goes out to Burton, John, Mary, Sehdev, and the rest of the Massey College

community for my two enjoyable years there.

Morn, Dad, 1'11 be on page 104 soon. Watch out!

'"Those three men,' said he, 'have carried into space al1 the resources of art, science, and

industry. With that, one can do anything; and you will see that, some day, they will corne out

al1 right."' -Jules Verne

in Frorn the Earth to the Moon

This thesis is dedicated to the memory of Greg Hartman.

Table of Contents ........................................................................................................... iv

List of Tables ..................... ......... .................................................................................. vii

List of Figures ................................................................................................................. viii

List of Symbols .................................. ............................................................................. xi

Chapter 1: Introduction ............................................................................................... ........................................................................................................... 1 1 Motivation

..................................................................................................... 1.2 Thesis Outline

Chapter 2: Field-Programmable Analog Array Background ....e.................e..... a.

........................................... 2.1 Description of Field-Programmable Analog Arrays

................................................................................... 2.1.1 A Conceptual FPAA

2.1.2 FPAA CAD Methodology .......................................................................... ........................................................................... 2.1.3 FPAA Mapping Example

2.2 Previous FPAA Designs ...................................................................................... .................................................................................. 2.2.1 Early FPAA Designs

................................................................................. 2.2.2 Lee and Gulak FPAA

.......................... 2.2.3 IMP Electrically Programmable Analog Circuit (EPAC)

.................................................................................. 2.2.4 Motorola MPAA020

2.2.5 Zetex Totally Reconfigurable Analog Circuit (TRAC) .............................. 2.2.6 Other Proposed FPAA Designs ...................................................................

............................................................................................ 2.3 FPAA Design Issues

............................................................ 2.3.1 FPAA Performance Quantification

.......................................................... 2.3 -2 Continuous-Time vs . Discrete-Time

2.3.3 Operational Amplifiers in FPAA Designs ..................................................

Chapter 3: Current Conveyor Background ................. ....... ...................................O.... ......................................................... 3.1 The Second-Generation Current Conveyor

3.1.1 Theory ........................................................................................................

3.1.3 Comparator ................................................................................................ ...................................................... 3.2 Reasons for Current Conveyor-Based FPAA

...................................................................................... 3.2.1 Area Requirement

............................................................................................ 3.2.2 Compensation

................................................................................... 3.2.3 Constant Bandwidth

...................................................................... 3.3 Previous Current Conveyor FPAA

3.4 Commercial Current Conveyors .........................................................................

.......... Chapter 4: A CMOS Current Conveyor-Based Configurable Analog Block

................................................................................ 4.1 Configurable Analog Block

....................................................................................... 4.1.1 Current Conveyor

........................................................................................... 4.1.2 Transconductor

4.1.3 Programmable Capacitor Array ................................................................. ......................................................................................................... 4.1.4 Buffer

................................................................................................ 4.1.5 Bias Circuit

4.2 Interconnection Network .................................................................................... 4.2.1 Transmission Gate Response ..................................................................... 4.2.2 Transmission Gate Into X Node ................................................................. 4.2.3 Transmission Gate Into Y Node .................................................................

............................................................................................................. 4.3 Test Chip

......................................................................................................... 4.4 Test Results

4.4.1 Amplifier .................................................................................................... .................................................................................................... 4.4.2 Integrator

.............................................................................................. 4.4.3 Differentiator

4.4.4 Adder ........................................................................................................ 4.4.5 Low Voltage Testing .................................................................................. 4.4.6 Summary of Test Results ...........................................................................

Chapter 5: Future Current Conveyor-Based FPAAs. ..................... ........................... 5.1 Current Conveyor Irnplementation of the Zetex TRAC .......................................

........................................................................................................ 5.1.2 Layout

..................................................................................... 5.1.3 Simulation Results

...................................................................... Fully-Differential Implementation

............................................................................................................. Summary

Chapter 6: Conclusion ........................ ........................................................................ ................................................................................. Summary and Conclusions

........................................................................ Suggestions for Future Research

................................................ Field-Programmable Mixed-Signal Arrays

................................................................................................. CAD Tools

FPAA On-Chip Memories ......................................................................... Low Power Supply Voltage ........................................................................

............................................................................ Performance Limitations

Appendix A: Empirical Comparison of Area Requirements for Digital and Analog

Filters ................... ....................................................................e...............m............... ......................................................................................................... A . 1 Introduction

...................................................................................................... A.2 Digital Filters

A.2.1 Definitions ................................................................................................. ........................................................ A.2.2 Area Requirements for Digital Filters

...................................................................................................... A.3 Analog Filters

A.3.1 Definitions .................................................................................................. ....................................................... A.3.2 Area Requirements for Analog Filters

............................................................................................... A.4 Area Cornparisons

A.4.1 Cornparison ................................................................................................ ..................................................................................... A.4.3 Study Conclusions

............................................................... Bibliography ..................................... .........*.....

3.1 Example Current Conveyor-Based Building Blocks ................................................ 24

3.2 Performances of Existing Current Conveyor Architectures .................................... 32

4.1 Equivalent Resistances and Linearities of Large Resistance Transconductor for Bias

............................................................ Voltages Ranging from VDD.0.5V to VDD+0.5V 37

4.2 Equivalent Resistances and Linearities of Small Resistance Transconductor for Bias

............................................................ Voltages Ranging from Vm-0.5V to VDD+0.5V

............................................................................. 4.3 Area Requirements for Test Chip

................................................................................. 4.4 Surnrnary of Test Chip Results

................................................................ 6.1 Surnrnary of FPAA Cad Tool Capabilities

............................ . A 1 Areas of Standard Cells in Mississippi State University Library

......................... A.2 Areas in h2 of Programmable and Non-Programmable W Filters

..... A.3 Areas of Fully-Differential Analog Building BIocks in 1.2 Fm CMOS Process

....................................... A.4 Building Block Requirements for Various Analog Filters

.... A S Areas of Programmable and Non-Programmable Active Filters from Table A.4

...................... A.6 Area Comparison Between Same-Order Non-Programmable Filters

.............................. A.7 Area Comparison Between Same-Order Programmable Filters

........................................................ B.l Characteristic of Existing Commercial FPAAs

vii

Y... v- . -=-- .. ...................................................................................... 2.1 FPAA Conceptual Diagram

......................................................................................... 2.2 FPAA CAD Methodology

..... 2.3 Phase-Locked-Loop (a) Diagrarn (b) Technology Mapping (c) FPAA Mapping

......................................... 2.4 Lee-Gulak FPAA Showing Embedding of Filter Biquad

............................................................................ 2.5 Diagram of the IMP 5OE 1 0 EPAC

.................................................... 2.6 Motorola MPAA020 Configurable Analog Block

.................................................................. 2.7 Motorola MPAA020 Array Architecture

.................................................... 2.8 Zetex Semiconductors TRAC Array Architecture

............................................................. 2.9 Pierzchala et al Configurable Analog Block

............................................. Chang et al Switched-Current Multi-Function Block

........................ Kutuk and Kang Switched-Capacitor Configurable Analog Block

............................................ Faura et al Field-Programmable Mixed-Signal Array

................................... FPAA Frequency Response Characterization (not to scale)

................................................................................ Switched-Capacitor Integrator

.............................................................................. Four MOSFET Transconductor

...................................... Op-Amp Open- and Closed-Loop Gain Characterization

Current Conveyor Symbol ..................................................................................... 20

Mode1 for CCII+ ...................................................................................................... 21

Mode1 for CC& ....................................................................................................... 22

Impedance Mode1 for Current Conveyor .................................................................. 22

............................................................. Current Conveyor-Based Voltage Amplifier 23

........................................................................................... CCII-Based Comparator 25

DC Response of CCII-Based Comparator . Output Vmmp is shown versus input Vin. for

............................................................................................ of~O.lV.O.OVyandO.lV 26

Transient Response of CCII-Based Comparator . the input sine wave is shown. along with

. .................................... 3 outputs VcOmpy corresponding to Vth of .O.LVy O.OVy and O IV 26

3.9 (a) Op-amp and (b) Current Conveyor-Based Amplifiers ......................................... 28

3.10 Response of Current Conveyor-Based Amplifier ............................................... 28

................................. 3.12 Architecture of Prérnont et al Locally-Interconnected FPAA 30

................................................. 3.13 Transconductor Implementing Grounded Resistor 30

...................................................... 3.14 Level Shifter that Shifts Vin Up by Voltage Vc 31

.............................................. 4.1 Current Conveyor-Based Configurable Analog Block 34

....................................................... 4.2 The Oliaei-Loumeau CMOS Current Conveyor 35

......................................................................... 4.3 CMOS Double Pair Transconductor 36

. 4.4 Large Resistance Transconductor 1 vs V response for 5 Control Voltages .............. 38

4.5 Small Resistance Transconductor 1 vs . V response for 5 Control Voltages .............. 39

4.6 Temperature Dependance of Transconductor - 1 vs . V characteristics are shown for T = - 50°C, 30°C and 1 10°C ..................................................................................................... 39

.............................................. 4.7 Programmable Capacitor Array with Two Capacitors 40

4.8 Continuously Programmable Capacitor .................................................................... 40

........................................... 4.9 Impedance Mode1 for Connection Between Two CCIIs 41

4.10Temperature.StableBiasCircuit ............................................................................. 42

................................................................................................... 4.1 1 Transmission Gate 43

........................ 4.12 Small Signal Mode1 of Transmission Gate Connection to X Node 44

4.13 Effect of RT (Magnitude, top; Phase, bottom) on Ix, for RT ranging from OC2 (top curve),

...................................................................................................... 100Q 200Q and 1 ka ........................ 4.14 Small Signal Model of Transmission Gate Connection to Y Node

4.15 Test Chip Schematic ............................................................................................... ................................................................................... 4.16 Die Photograph of Test Chip

4.17 Transient Response of High-Gain Amplifier . Vin Top. Vau, Bottom ..................... . ...................... 4.18 Transient Response of Low-Gain Amplifier Vin Top. Vaut Bottom

.................................... 4.19 Frequency Response of Amplifier at Four Different Gains

..................................................... 4.20 Harmonic Distortion of the Amplifier at lOkHz

4.21 Transient Response of Integrator . Vin Top. Vaut Bottom ....................................... .......................................................................... 4.22 Frequency Response of Integrator

4.23 Transient Response of Differentiator . Vin Top. V,, Bottom .................................

4.25 Instantiation of Adder on Test Chip ........................................................................ 4.26 Transient Response of Adder to 200kHz and lMHz Inputs ................................... 4.27 Amplifier Operating at 4V with High Gain . Vin Top. Vaut Bottom .......................

4.28 Amplifier Operating at 4V with Low Gain . Vin Top. V,,, Bottom ........................

........................................................... 5.1 TRAC-Like CCII-Based FPAA with 6 CABS

.................................................................................... 5.2 Switchable CC11 Mechanism

......................................................... 5.3 Adder on the CCII-Based TRAC-Like Circuit

.............................................................................. 5.4 Switchable Z Output Mechanism

.................................................................................... 5.5 Layout of TRAC-Like FPAA

5.6 Biquad Embedding ont0 TRAC-Like FPAA ............................................................ 5.7 Low-Pass and Band-pass Biquad Responses ............................................................

............................................................................. 5.8 Fully-Differential CC11 Amplifier

5.9 Fully-Differential CAB Utilizing the Four MOSFET Transconductor .....................

6.1 Conceptual Field-Programmable Mixed-Signal Array Diagram ..............................

A . 1 Structure of Infinite Impulse Response (IIR) FiIter ................................................. .............................. A.2 Multiplication of Signal A by Constant 43 Using Only Adders

&(s) Current conveyor Ix to IZ response

A. Op-amp DC gain

&(s) Op-amp open-loop response

Op-amp closed-loop gain

Current conveyor IZ/lx gain

Gate capacitance per unit area

Clock frequency

Input current

Current out of current conveyor X terminal

Current out of current conveyor Y terminal

Current out of current conveyor Z terminal

Diode saturation current

Transmission gate total current

Transistor conductivity parameter

Transistor length

Carrier mobility

Swi tched-capacitor clock

Bias circuit control resistor

Equivalent resistance

Input resistance

Op-amp input resistance

Output resistance

Transmission gate equivalent resistance

Temperature

Programmable capacitor control voltage

Programmable capacitor and transconductor control voltage

VComp Comparator output voltage

- - Positive supply voltage

Transconductor control voltage

Transconductor control voltage

Bias circuit low output voltage

Bias circuit high output voltage

Negative supply voltage

Thermal voltage

NMOS transistor threshold voltage

NMOS transistor threshold voltage

Equivalent threshold voltage

Comparator threshold voltage

Voltage on current conveyor X terminal

Voltage on current conveyor Y terminal

Voltage on current conveyor Z terminal

Transistor width

Pole angular frequency

Op-amp unity gain angular frequency

xii

Chapter 1: Introduction

1.1 Motivation

Recent trends in hardware design have seen a marked increase in the use of programmable

devices such as PALS, CPLDs, FPGAs @ro92], and more recently field-programmable analog

anays (FPAA) [DMe97]. Programmable devices reduce the time and cost of hardware

prototyping. Design using field-programmable devices is automated through the use of

sophisticated cornputer-aided design (CAD) tools, which synthesize circuits from schematic,

high-level, or behavioural descriptions into usable hardware. This automated CAD ffow

reduces the need for detailed design expertise in developing working hardware and thus makes

hardware design open to a greater number of consurners.

For many real-time signal processing applications requiring low precision (approximately 10

bits or less), analog ICs require smaller area and lower power than their digital counterparts, in

addition to not requiring anti-aliasing filters and signal converters. For these reasons analog

circuitry is advantageous for wireless and remote applications where compactness and low

power consumption are important. Overall, applications where analog ICs are finding

continued usage include signal processing, wireless communications, control and monitoring,

as well as neural networks. An area cornparison of analog and digital filters is presented in

Appendix A.

As line widths decrease, there is greater possibility of including analog functionality on

primarily digital ICs. However, in cases where the proportion of analog circuitry on a chip is

as low as 20%, as much as 80% of the design time rnay be spent on the analog section

[TouBO]. For this purpose, FPAAs, which offer rapid prototyping on a single IC, are proving

to be a very useful tool requiring reduced levels of analog expertise to design working analog

and mixed-signal ICs. Several commercial FPAA designs have now been released, operating

in both the continuous-time and discrete-time domains [Gau97]. Many university-based

FPAAs have also been proposed.

based and have operated at audio frequencies (100kHz bandwidths). Another frequency range

where FPAAs could find a niche is the video frequency range. The NTSC video frequency

range extends to 4.5MHz [Ben86], and cable television channels are allocated 6MHz slots

[Cou93]. Thus an FPAA that operates up to lOMHz may be of use in certain video

applications.

In order to increase bandwidths of CMOS FPAAs to video frequencies, new architectures

where the bandwidth is not Iirnited by the frequency response of a simple operational

amplifier, must be developed. As a replacement, current conveyors [Sed70], which do not rely

on a compensation capacitor for stability, have shown promise.

This thesis deals with the design of a CMOS FPAA operating in the video frequency range

(10MHz). For this purpose the second generation current conveyor is used in the FPAA

design. Design and test of an architecture for an FPAA chip are achieved in this work. On-

chip programrning mernories, a development board, and a CAD tool remain to be designed.

1.2 Thesis Outline

This thesis contains six chapters and one appendix. Chapter 2 gives background information

on FPAAs, including a survey of existing industrial designs and university-based research

designs. Chapter 3 gives background information on current conveyors, and describes some

current conveyor-based circuitry. Chapter 4 describes the design and testing of a CMOS

current conveyor-based field-programmable analog array prototype. Chapter 5 discusses two

different realizations of FPAAs; one is similar to the Zetex TRAC, and includes no switches

in the interconnection network; the other uses fully-differential signalling. Chapter 6

concludes this thesis and presents suggestions for future work. Appendix A gives an area

comparison for digital and analog filters.

Chapter 2: Field-Programmable Analog Array Background

This chapter serves as a description of field-programmable analog arrays (FPAAs). Section

2.1 gives an overview of FPAAs and their functionality. Section 2.2 is a survey of existing

FPAA designs. Section 2.3 describes issues relevant to the design of high-frequency FPAAs.

2.1 Description of Field-Programmable Analog Arrays

2.5.1 A Conceptual FPAA

A field-programmable analog array is an integrated circuit, which can be configured to

implement various analog functions using a set of configurable analog blocks (CAB) and a

programmable interconnection network [Lee92], and is programmed using on-chip memories.

Programming of an FPAA is done both in tems of the topology of the circuit to be

instantiated, and in terms of its parameters.

Figure 2.1 shows a conceptual FPAA containing several CABS connected together through the

use of an interconnection network. The configuration bit string is stored in a shift register.

Some bits in the bit string are used to configure the connectivity of the interconnection

network. Other bits are used to program the functionality of the CABs. A CAB could

norrnally be programmed to implement one of several analog functions such as adders,

multipliers, voltage-controlled oscillators, amplifiers, integrators, and so on. Finally some bits

are used to program the parameters defining the various functions realized in the CABs. For

example, parameters could include the gain of an amplifier or the corner frequency of a lossy

integrator.

Interconnection networks can take the form of a tree [Leeglb], crossbar [Lee95b], datapath

[IMP], or other network [And97]. In field-programmable gate arrays, switches regularly take

the form of pass-transistors. However this is not possibIe for FPAAs since pass transistors

introduce circuit non-idealities, which are detrimental to the performance of analog circuits.

[LeegSb] are used. On another FPAA, CABS can be tumed off, electrically disconnecting the

outputs from the inputs [Brad96].

Function parameters, such as gain and corner frequency, are usually programmed using a

voltage in a continuous range between the power supplies. These continuously variable

parameters are loaded into the shift register in digital forrn, and can be converted to an analog

value using signal converters. The analog value is then used to control transconductors and

variable capacitors .

The CABS on an FPAA may be al1 alike, or may be different. For example, an FPAA could

contain specialized CABS which have the potential to realize only a few different functions,

and where programmability corning from the configuration of the interconnection network

[IMP], or the FPAA could contain CABs which are homogeneous but can be configured as

many different functions [And97].

Finally, CABs may be realized at different functionality levels, including transistor, sub-

circuit, building bIock, macro block and sub-system leveIs. A study done in [LeegSa]

CA33 A CAE? B

in out in out .a.

1 - I + - -

Ca

-54 -- = O - Interconnection Network

-- i% + .55; - 25 +, - -

Configuration bits -

1 1 1 1 1 1 l l l l l l l l l l l l l l l l D I I D 1 1

~hi f t in interconnection network I shift out

Figure 2.1: FPAA Conceptual Diagram

Circuit representation c Decomposi tion and synthesis 1

l Placement and routing I

Macro models for Verification 4 op-amp, routing

channels, etc.

No Yes Configuration bit generation

Figure 2.2: FPAA CAD Methodology

determined that the optimal level, with respect to silicon area, in which to implement a CAB is

the building block level, which includes operational amplifiers, transconductors, capacitors,

diodes, and current conveyors.

2.1.2 FPAA CAD Methodology

The flow chart illustrated in figure 2.2 details the computer-aided design (CAD) methodology

which is used in designing an analog circuit using an FPAA. In a schematic editor, the user

enters a schematic netlist of the desired circuit; the schematic can be at one of many Iogical

Ievels, from behavioural (such as filtorX-generated [Ous90]) to transistor-level, depending on

the synthesizing capabilities of the CAD tool. The CAD tool then decomposes the schematic

into basic units and synthesizes it in tenns of the resources available on the FPAA. Then the

circuit is placed and routed, and the original schematic is back-annotated. Verification is

perfonned to see if the mapping of the circuit ont0 the FPAA meets al1 design specifications.

l n 37- out

in wl i , - LPF L --- - A

I I . . 1 . . . . . . I , , Block t Block ? Block 3

r-- 1 i lr-mr--- I I I

Block 4 Block 5 Block 6

. lntcrconneccion Block BIock Block Bluck Block Block -

network 1 2 3 4 5 6

FPAA IC

I I U I I I I I I I lu Figure 2.3: Phase-Locked-Loop (a) Diagram (b) Technolugy Mapping

(c) FPAA Mapping [Lee95a]

If not, the whole procedure can be repeated within a matter of minutes. When design

specifications are met, a configuration bit string is generated by the CAD tool and downloaded

ont0 the FPAA IC, instantiating the designer's circuit. The downloading is often performed

using the parallel port of a persona1 computer. If the designer decides to change the circuit,

then redesigning and reprogramrning the IC can be done in a matter of hours instead of the

months it would take to redesign and fabricate a new ASIC.

In some CAD tools, design entry is done using a schematic editor; the CAD tool then maps

the circuit ont0 the FPAA architecture. Some other CAD tools only show a floorplan of the

FPAA, and the user has the responsibility of doing the placement and routing directly.

Another feature some CAD tools include is a simulator to simulate the design before

downloading ont0 the IC.

2.1.3 FPAA Mapping Example

Figure 2.3 shows a mapping example of a phase-locked loop (PLL) ont0 an FPAA. As seen in

figure 2.3(a), the PLL is composed at a high level of a phase detector, low-pass filter and

voltage-controlled oscillator (VCO). Resources available on the FPAA include multipliers,

integrators, amplifiers, and lossy integrators. Figure 2.3(b) shows the PLL synthesized in

lossy integrator, respectively. The VCO is constructed using a multiplier, integrator and

amplifier. Finally, the mapping is shown in figure 2.3(c). CAB 1 is the phase detector. CA8

2 is the iow-pass filter. CABs 4 through 6 realize the VCO.

2.2 Previous FPAA Designs

Several industrial and university-based research groups have released FPAA designs. This

section describes sorne of them.

2.2.1 Early FPAA Designs

An early conceptual FPAA design is the Proto-chip by Sivilotti [Siv88]. The Proto-chip's

CABs are designed at the transistor level, and the interconnection network is based on a tree

structure. Its target application was for the prototyping of analog neural networks.

An early successful physical design was the one by Lee and Gulak [Lee9lb]. It was based on

sub-threshold techniques and operates below lOOkHz frequencies. Its target application was

for the hardware implementation of neural networks.

2.2.2 Lee and Gulak FPAA

The next design by Lee and Gulak [Lee921 is a fully-differential continuous-tirne CMOS

design based on operational amplifiers and a modification to the Czarnul four MOSFET

transconductor [Dup90]. Its target application is for signal processing applications in the

audio range, with IC test results presented for biquad filter, squaring, rectifier and VCO

circuits. The CAB contains an op-amp as well as switchable feedback capacitors, and can

also be used to implement a comparator by turning off the compensation capacitor. In this

design, switches in the interconnection network are implemented using the transconductor,

which acts as a programmable linear resistor. The transconductor is also used to realize a four

quadrant multiplier. Figure 2.4 shows a mapping of a biquadratic filter containing two op-

arnps as well as several resistors and capacitors, ont0 the FPAA. Note that two CABS are

used, as well as four transconductors. A PC-based CAD tool is used to program the FPAA.

Vin

Config. Interconnection Analog Network Blocks

Figure 2.4: Lee-Gulak F M Showing Embedding of Filter Biquad [DMe97]

2.2.3 IMP Electrically Programmable Analog Circuit (EPAC)

IMP Inc. has released two commercial FPAA-like products, the 50E10, and 50E30 [Kle96,

IMP971, and has plans for a third, the 50E20. Al1 are discrete-time designs based on

switched-capacitor technology. Figure 2.5 shows a diagram of the 50E10 EIectrically

Programmable Analog Circuit (EPAC). It includes an input analog rnultipIexer,

programmable amplifiers, routing bus, and output modules. The input and output blocks can

add programmable offsets. The input multiplexer can route either 16 single-ended or 8 fully-

differential signals. The EPAC 50E10 is programmed using a 200-bit configuration bit string.

Bandwidths are limited to 125 kHz (clock frequency of 1MHz) due to the use of switched-

capacitor technology. The 50E10 is targeted to signal conditioning applications; the 50E20

will be a field-programmable gain amplifier; the 50E30 is targeted to monitoring applications,

Figure

Single-Ended Operation

L

- voXo

2.6: Motorola MPAAOSO Conjgurable Analog Block [Mot971

Custorn Functions I

Figure 2.7: Motorola MPAA020 Array Architecture [Mot971

As with the EPAC family, the clock speed is IMHz, limiting bandwidths to 200kHz. A PC-

based CAD tool accompanies the MPAAOZO. Programming of the MPAA020 is done via the

same IC, so as to create a field-programmable mixed-signal array (FPMA) - an IC containing

both and WAA and an FPGA, in addition to a mechanism to convert signals to and from the

analog domain to the digital domain. No A/D and D/A converters will be included on the

Motorola FPMA; signals will be directly converted through the use of comparators and

similar blocks.

2.2.5 Zetex Totally Recodigurable Analog Circuit (TRAC)

Zetex Semiconductors Ltd. has introduced the Totally Reconfigurable Analog Circuit (TRAC)

[Zet97, Brad961, a continuous-time, log-domain bipolar design operating up to 4MHz. The

TRAC includes 20 CAIBs, organized in two rows of 10 CABs, each capable of implementing

one of the eight following functions: log, anti-log, non-inverting pass, addition, negating pass,

op-amp, half-wave rectification, and off. The interconnection network is hard-wired, as

shown in figure 2.8. The leftmost pins act as inputs whereas the rightmost pins act as outputs.

The intermediate pins can be configured either as inputs or outputs, depending on the

configuration of the CAB to the immediate left of the pin. Topological programming is

implemented by turning CABs off, and by extemal wiring of the pins. By turning a CAB off,

its inputs and output are electrically disconnected, allowing the designer to use the output as

an input to the subsequent CAB. Amplifier gain is determined by using off-chip resistors.

Input pin

Y Input/ Output pins Output pin

Figure 2.8: Zetex Semiconductors TRAC Array Architecture

t r A f

te A t r A A Out -- B --

i) O U ~ O U ~ d D O U ~ B B -- B

A A k- A Out Out . i Out

- B B - B

A

0 0 0 O

b-

out - B

used to configure the TRAC; the CAD tool includes a simulator to simulate a circuit before

being downloaded ont0 the FPAA IC.

2.2.6 Other Proposed FPAA Designs

Many other FPAA designs have been proposed. One continuous-time design is the

Pierzchala-Perkowski bipolar design [Pie94], for which the CAB is illustrated in figure 2.9.

The CABS are organized in an array structure, with local interconnection. The Embabi et al

CMOS current copying design [Emb96] uses a current copying integrator, with gain

4' +... + Programming signais

1 l I I Control 1

--

Figure S . 9: Pierzchala et al Conjigurable Analog Block [Pie941

Figure 2.10: Chang et al Switched-Current Multi-Function Block

Figure 2.1 1: Kutuk and Kang Switched-Capacitor Configurable Analog Block

deterrnined by turning on multiple copies of an identical current-mode circuit. The design

Prémont et al are proposing is based on current conveyors [Pre96]. It is described in section

3.3.

The Chang et al multi-function block (MF'B) [Chan961 is a discrete-time current mode CAB

implemented using CMOS switched-current technology [Tou93], as depicted in figure 2.11.

The MFB implements current copying with programmable gain and phase, current

cornparison, an output switch, and a current reference. Functionality is controlled by the Bo-

Bs signals, which open and close the switches SI and SZ. AS with other discrete-time designs,

the clock frequency is limited to lMHz, limiting signal frequencies to the audio range.

The Kutuk and Kang design [Kut96] is based on switched-capacitor technology and includes

two op-amps in a feedback loop configuration, so as to have the potential for second-order

filtering functions on a single CAB. The CAB is depicted in figure 2.11.

The [Fau97] design is a field-programmable mixed-signal array (FPMA) containing an FPAA

I Ce11 Analog I I Interface Cells I

I I

block similar to the EPAC 50E10. It also includes an on-chip microprocessor, as depicted in

figure 2.12. The FPMA is targeted to microcontrollers for coin-operated mechanisrns.

Ananth and Gulak [Ana921 developed a signal processing structure based on pulse density

modulated signals, converted from analog signals using delta-sigma modulators. The

resulting stochastic bit streams are processed on a digital FPGA using logic gates, and then

reconverted to analog signals.

On-Chip

A similar design approach is used for the pulse-based signal processing system, from the

University of Edinburgh [Pap96a, Pap96bl. Pulse-width modulated signals are used instead of

analog signals. The signals are operated on through the use of integrators and logic gates.

Functionality is demonstrated using a 4th-order Palmo filter.

2.3 FPAA Design Issues

Digital

Section 2.2 described several existing FPAA designs. Al1 those realized in CMOS technology

operate at audio frequencies. Designs can be categorized as continuous-time or discrete-time,

and al1 thus far are operational amplifier-based. This section describes challenges towards

designing video-frequency FPAAs. First, an overview is given to the issues limiting FPAA

performance. Then, a comparison of continuous-time and discrete-time irnplementations is

I pP Core 4 D I

I Memory

C. 4 1

I I

+ !2 rC

C. D Memory Cells

Config. , S

Y A

design.

2.3.1 FPAA Performance Quantification

FPAA performance can be quantified in several ways. One performance measure is called

"versatility" [Lee95a], and quantifies the number of circuits implementable on an FPAA in a

given area.

Another, different performance measure is signal bandwidth. Figure 2.13 illustrates several

key components limiting the high- and low-frequency responses of an FPAA. High-frequency

performance is limited in the high end by the maximum transconductor frequency, as well as

maximum frequencies for other blocks such as programmable capacitors, switches and

diodes. Where comparators are required, performance is limited by the maximum comparator

frequency.

Current FPAA designs have op-amp unity-gain frequencies (a,) in the 1-1OMHz range. This

lirnits operating frequencies for single CABS to IOOkHz for realistic gain values. Furthermore

when CABS are cascaded, the frequencies decrease to a greater extent since the 3dB point

gain [dB]

1 OOk 1 M op-amp 10M f [Hz] f t

Figure 2.13: FPAA Frequency Response Characterizution (not to scale)

Discrete-tirne circuit performance is limited by the maximum clocking frequency. Due to the

Nyquist theorem, actual signal frequencies are significantly less than half the clock frequency,

and can be up to one tenth thereof. However, continuous-tirne performance is not limited by

clocking frequencies.

Low-frequency performance is limited by the RC time constants available. RC constants are

limited by capacitor size and impedances of transistors. Furthemore capacitors, large and

small, must be well-matched, limiting the range of capacitance values available.

2.3.2 Continuous-Time vs. DiscretelTime

As seen from the designs detailed in section 2.2, FPAA designs can be categorized as either

continuous-time or discrete-time. Discrete-time designs offer programming in terms of

capacitor ratios, which can be matched to 0.2% [Joh97], and in terms of clock periods, but

operate at low bandwidths. Continuous-time designs offer higher bandwidths, and the

absence of input and output anti-aliasing filters for real-time signal processing applications;

however, they are more difficult to program and can often have higher distortion.

A generic switched-capacitor integrator is pictured in figure 2.14 [Sed89]. In the input stage,

CI is connected to the switches Si and S2. When the clock 9 is high, Ci is charged to Vin,

with the total charge on the capacitor equal to Clvin. When $ goes low, Cl is discharged, with

al1 of its charge flowing into Cs. We therefore have an average current of fclkCIVin flowing

through the switches and into C2, where fclk is the clock frequency. The voltage across the

switches is equal to Vin. We thus see that the average resistance across the switches is equal to

l/fclkC1. Thus the resistance is easily programmed by modifying either CI or more easily by

varying the period of $.

Since the clock frequency fclk is limited by the RC time constants of the nodes in the resistor

block, the clocking frequencies of switched capacitor designs are limited. Furtherrnore, for

Vin

Figure 2.14: Switched-Capacitor Integrator

Vin+O T - ,ut+

v . 2 4

Vin- 0 'out-

Figure 2.15:

accurate signal representation in the

greater than the Nyquist rate (often 8

Four MOSFET Transconductor

discrete domain, the circuit must be clocked at much

to 10 times faster than the base signal frequency), thus

further limiting the bandwidths of discrete-time circuits. Al1 existing switched-capacitor

FPAAs are clocked at 1 MHz, limiting signal frequencies to the 100-200kHz range. Switched-

capacitor clock rates are lower for FPAAs than for other ASICs since the routing,

programmability, and performance requirements add more capacitance to circuit nodes, thus

leading to greater RC time constants, and a lower clock rate than for specialized designs.

In continuous-time designs, programmable resistors are realized using transconductors, where

the transconductance is programmed using a reference voltage generated by a signal converter

or multi-valued memory. Transconductors are realized using transistors operating in either the

linearize the transconductance. Transconductors generally have very high bandwidths. For

example, the four MOSFET transconductor [Cza86], depicted in figure 2.15, has a bandwidth

in the order of lOOMHz for a 1.2pm CMOS process [Lee95a]. Its cross-coupled transistors

ensure highly linear operation.

2.3.3 Operational Amplifiers in FBAA Designs

To date, al1 published FPAAs designed at the building block Ievel have used op-amps as their

basic active element. This section examines the performance issues relative to op-amps.

A study done using the PowerDesign op-amp design tool [Rez95], found unity gain

frequencies for simple operational transconductance amplifiers (OTAs) could reach 34MHz to

43MHz for 4mW power consumption and from 42MHz to 52MHz for 8mW power

consumption at 5V. Higher bandwidths could potentially be obtained by specifying a higher

power dissipation.

However, in order to obtain significant gain from a simple op-amp-based amplifier, a designer

must settle for significantly lower frequencies.

4 s )

Figure 2.16 shows the open-loop gain of a

Closed-loop bandwidth, (bandwidth of amplifier)

a&

Figure 2.16: Op-Amp Open- and Closed-Loop Gain Characterization

designer must settle for a bandwidth of o,/A,.

In order to get a gain of 20dB in the OTA example cited above, bandwidth would be lirnited to

between 3 and 5MHz; when such amplifiers are cascaded, frequencies would be limited to

lower than the video range. For this reason the simple CMOS operational amplifier is not a

viable option towards designing a video-frequency FPAA.

There are three potential options. The first would be to design an op-amp with greater

frequency response. However, such an op-amp would occupy much greater die area and

consume more power. A second option would be to use a programmable compensation

capacitor [Gra84], where op-amp bandwidth can be extended where a high gain is desired. A

third option is to use a block different than the operational amplifier, of which one possibility

is the second-generation current conveyor. The next chapter describes the second-generation

current conveyor, which offers some advantages over simple CMOS op-amps, including

possible higher frequency operation.

Chapter 3: Current Conveyor Background

Current conveyors were first developed by Smith and Sedra [Smi68]. The second-generation

current conveyor (CCII) [SedirO] was developed shortly thereafter and offers several

advantages over the conventional operational amplifier in analog signal processing designs.

This chapter first describes both current conveyor theory and applications. Then an argument

is made in favour of using current conveyors rather than simple op-amps. Finally, the chapter

closes with a description of a recent proposa1 for a current conveyor-based FPAA.

3.1 The Second-Generation Current Conveyor

3.1.1 Theory

A current conveyor [SedBO] is a building block similar to an operational amphfier and which,

when used in conjunction with other components such as resistors, capacitors and diodes, can

implement several useful analog sub-systems such as amplifiers, integrators, and rectifiers.

The second generation current conveyor is a three terminal device. Its symbol is shown in

figure 3.1. The current conveyor's response is given by equation 3.1.

Figure 3.1: Current Conveyor Syrnbol

impedance is finite and must be taken into consideration in the circuit design. When a voltage

is applied at node Y, that voltage is replicated at node X. This is similar to the virtual short on

an op-amp; however there is no need for negative feedback to achieve it. Also, when a

current is injected into node X, that same current gets copied into node Z. The notation CCII+

denotes a positive Z output current conveyor (p = +1) whereas CCII- denotes a negative Z

output current conveyor (p = -1).

One model used to analyze a CCII+ is shown in figure 3.2 Wi1841. The op-amp in unity-gain

feedback configuration ensures that Vx is equal to Vy, and the current mirrors ensure that Iz is

equal to IX. Here the op-amp's output stage has an infinite output impedance.

Figure 3.2: Mode1 for CCII+

A CCII- is obtained from a CCII+ by adding two current mirrors in the output stage, inverting

the output current, as depicted in figure 3.3 [Wi186]. There has been Iittle practical use for the

CCII-, and thus unless otherwise specified al1 current conveyors used in this work are CCII-t,

and will be referred to as CCII.

A model of the impedances for a CCII+ current conveyor [Pre97] is depicted in figure 3.4.

For optimal circuit performance, it is desirable to have Ry and RZ + -, and Rx -t O.

Figure 3.3: Mudel for CCII-

Figure 3.4: Impedance Model for Current Conveyor

3.1.2 Building Blocks

Continuous-time analog functions can be realized by hooking up other elements to the various

terrninals of the CCII, as detailed in this section. Figure 3.5 illustrates an amplifier

constructed using a current conveyor and two resistors, RI and R2. Here, an input voltage Vin

1 applied at node Y is replicated at node X. This produces a current Ix equal to Vi, ,R, coming

1

out of node X. That same current gets copied out of node 2, and flows into resistor R2,

an amplifier with programmable gain is obtained.

Figure 3.5: Curren t Conveyor-Based Voltage Amplifier

Table 3.1 shows examples of useful analog functions implemented using current nveyors,

resistors, capacitors and diodes. An integrator is implemented by replacing resistor R2 in

figure 3.5 with a capacitor. A differentiator is implemented by replacing resistor RI with a

capacitor. The exponential function can be implemented by replacing resistor RI with a

diode; similarly the log function could be implemented by replacing resistor R2 by a diode. A

comparator that uses two current conveyors is described in section 3.1.3. Also, various

rectifiers can be implemented.

3.1.3 Comparator

A useful analog building block is a comparator. Comparators have two inputs and determine

which input has a larger value; the output is a bit value stating which input is larger.

Comparators are used in analog-to-digital converters as well as in precision rectifiers and

other signal processing subsystems. To the author's knowledge a current conveyor-based

voltage comparator has yet to be published.

Figure 3.6 shows a possible voltage comparator, implemented using two current conveyors

and two CMOS inverters. The X nodes of the two current conveyors are tied together, and the

Z output of each of the two current conveyors is tied to the input of a CMOS inverter.

II&

Vin O- CC11 z "5." Amplifier

vaut - 1 - - - Vin S R I ~ ~ Vin CF

Table 3.1: Example Current Conveyor-Based Building Blocks

CCII Z Y

0 V o ~ In tegrator

Figure 3.6: CCIi-Based Cumparator

The input voltage Vin, is applied to CCII 1's Y node. The threshold voltage Vth, is applied to

CC11 2's Y node. Both current conveyors attempt to copy their Y voltage ont0 the common X

node. Current flows from the current conveyor with the higher voltage to the one with the

lower voltage, via the X node connection. That current is then copied out of CCII 1, either

charging or discharging the input capacitance to the CMOS inverter. If Vin is higher than Vthp

then current will be drawn out of CCII 1, and the inverter will be charged, resulting in a low

V,,,,., output voltage. Similarly, if Vin is lower than Vthp then current will be drawn from the

inverter, resulting in a high VcOmp output voltage. Both cornparison polarities are available by

using either of the two output CMOS inverters.

The comparator has been simulated, with its DC response shown in figure 3.7 and its transient

response in figure 3.8. Simulations have been performed for Vthr of -O.lV, 0-OV, and O.1V.

Offset error, defined as being the difference between the input voltage where VComp crosses

2.5V and Vthp is 9.4mV. Resolution, defined as the difference in input voltages for output

voltages of 0.W and 4SV, is 6.3mV. Switching time, defined as the time interval between

when the input voltage crosses Vm, and when VComp reaches 90% of its target value, is 30ns

given a 0.5Vpp input sinusoidal wave centred around Vthr

........................................... ..'

........... W . . " . . . . . . . . . . . . . . . . . ".."'.""..~ .... .................................. .... """" ... .. "'." ...... '

v ............ a . o -.. :

.............. ................................................................................ 1 2.,5 a - : = .......................................................... .............. ........ L 2 . 5 0 ' i ....... '

......... ."" .. P.25o - ".' ."" "."""............... " """".,""'

........... ............................... .............. ............... - ".<"' " " """""""'

Figure 3.7: DC Response of CCII-Based Cornparator - Output VW is shown versus input Vi:,, for Vh of -0.IV 0.W and 0. IV

This is faster than unclocked comparators, such as an op-amp with no compensation capacitor.

However, some clocked designs operate faster and with Iower offsets [Joh97].

The comparator presented here can be used as a fully-differential comparator by setting Vin+

on the Vin node and Vin- on the Vthr node. Output polarity remains as shown in figure 3.6.

, .?En- . .

, .,, ,... q , 0 5 0 -...

q . -... -"'

. J .Zoo -..

.........

.........

...........

""".." .... " ................. .......... i .............. A..... .......... ................ ' i...,.

.......... (................ +... """""'..".., .........*....

-"'..".."..""" .." ................. """" ""

P . O -... 760

-"'.."" , , 2 5 0 -"'

. O - . .

7 6 0 0 n . , .

. on -...

. z 5 0 on -.... o . , ,

""

........

...................................

c .."'-"".."" .................

.i ................. i ............ ................. " ;. ..'.'..'.' ................. ................ : :

....................... .............

............... .""".."""

o . 200.ON qOO.oN 6OO.OW BOO.ON 1 .OU 1.2OU

f 1 M E CLIN1 1 .?OU

Figure 3.8: Transient Response of CCZI-Based Comparator - the input sine

wave is shown, along with 3 outputs Vcomp, corresponding to Vth of -0.1 y 0.0x and 0.1 V

.......... ............... ' .'.

"" ......, "" ............. :

.... """ .......................... .. ....................... ""..."""""

......... .... '.'.""""""" "

............................

i

;

"." "...

............ ..........

. . . R.;.[ .;..;;

"'.'.."'

"..'""' ""

......... ................ ' i....

......... ............... < .< I . O . I J

....

............. l &!L--- .'.".','

............. j """"' """'4

.............

.......................... : ........ "' "'.'".... .. "'

........ "". ............ -... "..""", ..-.................

............. '..."..'..... ""

............. ..........................

"..' ".'

' , " >

""

......... "'.....".."....... "" "'..."' ................ ........... ......... .: .;, ..., ,..-

il . ~ i ...I...,...,.. i...i...i...i a

. . . ""

""

""

..".... "' ....+ " " W . . j ".. -..- .... ""-

Section 2.3.3 detailed some reasons as to why the simple operational amplifier rnight be

insufficient in the effort to develop a video frequency FPAA. The following subsections make

an argument in favour of the current conveyor as a replacement for the simple op-amp.

3.2.1 Area Requirement

A standard simple op-amp uses 10 transistors, a compensation capacitor, and a bias stage. A

common version of the current conveyor uses 12 transistors and a bias stage. These two are

comparable in area requirements. An op-amp designed for higher frequency operation could

use the same number of transistors, but would have a higher power consumption.

3.2.2 Compensation

As seen in section 2.3.3, an operational amplifier-based sub-system usually requires negative

feedback. However, where the open-loop response A(s) of an uncompensated op-amp is

greater than unity in magnitude, and the phase shift nears 1 80°, there can be instability. For

this reason, a compensation capacitor is used to reduce the unity-gain frequency of the op-amp

to a point with larger phase margin, thus ensuring stable operation. This procedure results in

an op-amp incapable of producing significant gains at high frequencies.

However, as seen in table 3.1 current conveyor-based building blocks do not use feedback.

Stability is ensured since the gains in current and voltage from one node to another are unity.

There is thus no need to compensate a current conveyor [Bru95j. A current conveyor-based

design may thus be able to operate at higher frequencies than its op-amp-based counterpart,

and still produce significant gains at a savings in silicon area.

3.2.3 Constant Bandwidth

Another advantage of using current conveyors rather than op-amps is that current

conveyor-based amplifiers have a constant bandwidth [Bru95]. This is in contrast to

op-arnp-based amplifiers, which have a constant gain-bandwidth product.

Vin

Figure 3.9: (a) Op-amp and (b) Current Conveyor-Based Amplzjiers

Take the op-amp-based ampIifier shown in figure 3.9(a). Assuming the open-loop response of

the op-amp is given by A@), the response of the amplifier is given by equation 3.2.

Notice in equation 3.2 that the bandwidth of the amplifier is dependent on RI and R2, since the

irnpedance of R2 is seen in parallel with (RIIIR2) A(s).

Now take the cuvent conveyor-based amplifier in figure 3.9(b). Assuming the responses

note constant bandwidth

-. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.. . . . . . . . . . . . . . '..... ............... d

I i i i i i i i i l 1 0 0 , O ; 1 1 1 1 1 1 1 1 I I 1 1 1 1 1 1 1 0 , , a 5

I O . O K 1 . o n

HERTZ [ L O G 1 1 O . O X

1 0 0 . o x

frequency [Hz] Figure 3.10: Gain in dB of Current Conveyor-Based Amplifier

Here we see that the bandwidth of the amplifier is not dependent on RI nor R2, but only on

Al(s) and A2(s). This is further evidenced by simulation results of the above CC11 amplifier,

shown in figure 3.10. Here RI is varied from 1 kS2 to 9kQ while R2 = IOkSL

3.3 Previous Current Conveyor FPAA

Prémont et al [Pre96] have proposed a current conveyor-based FPAA design. The CAB,

depicted in figure 3.1 1, contains two current conveyors arranged in a feedback loop. The

feedback arrangement allows the implementation of gyrators, which realize a second-order

filtering function.

The current conveyors are configured so as to be able to be switched off, electrically

disconnecting their inputs and outputs. The architecture of the FPAA is to have locally

interconnected CABS, as depicted in figure 3.12. A significant waste of silicon area can occur

with the two current conveyor CAB since quite often only one of the two current conveyors is

used and the other one must be turned off.

The variable resistor used is depicted in figure 3.13. The result is a programmable grounded

resistor with response given by equation 3.4.

Figure 3.1 1: Prémont et al ConJgurable Analog Block

v CAB -

Figure 3.12: Architecture of Prémont et al Locally-lnterconnected FPAA

The problem with this transconductor is that a voltage Vi,+Vc, which tracks Vin, must be

generated. The problem is solved by using a level shifter which would shift the voltage Vin up

by a value Vc. A level-shifter can be designed using two matched PMOS transistors, as

depicted in figure 3.14. A voItage VDflc is applied to the gate of transistor M l , and Vin is

applied to the gate of M2. This generates a current flowing through Ml and into M2. To get

the same current flowing through M2, VgsZ must be equal to Vgsl. Thus, the output must be

equal to Vin+VC. A problem with this solution is that the bandwidth of the level shifter is too

low. An HSPICE simulation of the level shifter shows a bandwidth of 2MHz, which is

Vin

P

Figure 3.13: Transconductor Implernenting Grounded Resistor

Figure 3.14: k v e l Shzfier that Shifts y, U p by Voltage VC

insufficient for video applications.

3.4 Commercial Current Conveyors

At least two commercial current conveyors have been described in the literature. The first,

called the PA630 [WadgO], has a 3dB bandwidth of SOMHz, operates with rtlSV power

supplies, and has a power dissipation of 90rnW. It is used within SentedAntemi's DiAna

audio DIA converter [Wad96].

The AD844 [AD97], is a current feedback op-amp with a 3dB bandwidth of 60MHz, operates

with power supplies ranging from 15V to 118V, and has a power dissipation of 1.1W. It is

shown in [Sv09 11 that the AD844 can be configured as a second-generation current conveyor.

Both the PA630 and the AD844 are bipolar.

As well, current conveyors have been used for the analog circuitry and switches in the VISTA

family of telephone sets, available from Norte1 [Wad96].

Two 0.5pm CMOS research designs by Oliaei et al [Oli96, Oli971 operate at 12.1MHz and

6MHz 3dB points, respectively, with a single 3.3V power supply. A 1.2pm CMOS design

[Cha96] operates beyond 100MHz, but uses power supplies of +5V.

power consumption.

Technology Power Supplies

Bipolar + 1 SV

Bipolar S V - k18V

Table 3.2: Pe~orrnance of Existing Current Conveyor Architectures

0.5pm CMOS +3.3V

0.5pm CMOS +3.3V

3dB Bandwidth

5OMHz

6OMHz

Power Consumption

90mW

1.1W

12.1MHz

6MHz

NIA

N/A

cnapter 4: A LIVIVB Lurrent Lonveyor- Based Configurable Analog Block

This chapter describes the design and implementation of a current conveyor-based prototype

chip in a 0.8p.m CMOS process. The test chip includes four configurable analog blocks and

an interconnection network, but contains no programming memories. The following section

describes the CAB, followed by a section on the interconnection network. Then the chip

design is presented, and the chapter closes with test resufts.

4.1 Configurable Analog Block

The CAB is the principal functional block in an FPAA. Some desirable functions for a CAB

include amplification, integration, and differentiation, multiplication, addition, subtraction,

log, anti-log and cornparison. Figure 4.1 shows a potential current conveyor-based

implementation of a CAB capable of implementing first-order filtering functions as well as

amplification; the log and anti-log functions could potentially be added by having switchable

diodes on the X and Z nodes. The CAB includes a current conveyor, two transconductors, two

programmable capacitors, and a buffer. The transconductors realize programmable resistors.

The response of the CAB is described by equation 4.1.

By disconnecting Cx and CZ, we obtain the response of an amplifier. Similarly, by

disconnecting Cx and RZ, we obtain the response of an integrator. As well, a lossy integrator

function is obtained by disconnecting Cy.

In the prototype implementation, the current conveyor is based on the Oliaei-Loumeau CMOS

design [Oli96]. This implementation of the CC11 has been chosen for its low impedance on

the X node, crucial in order to eventually implement a fast comparator. The variable resistors

configurable as a grounded, programmable resistor. The variable capacitors are implemented

using programmable capacitor arrays (PCA), which produce discrete capacitor values. The

unity gain buffer is based on an operational amplifier in a unity-gain feedback configuration.

ccn z 1-0

Figure 4.1: Current Conveyor-Based Conjîgurable Analog BLock

The following subsections describe, individually, the circuit blocks used to implement the

CAB.

4.1.1 Current Conveyor

The current conveyor used in the test chip is a CMOS design [01i96]. A schematic is shown

in figure 4.2. The design was chosen because of the low impedance of the X node and its

CMOS implementation. Voltages Vni and Vpl are generated using a temperature-stable bias

circuit [Joh97] described in section 4.1 S.

Transistors M l 0 to Ml3 instantiate current sources, biased by Vnl and Vpl. The source-to-

source current mirrors MllM2 and M3/M4 ensure that the voltage at node Y is replicated at

node X; in order to get equal currents through both branches of the current mirrors (a

condition forced by the current sources), each current mirrors' two Vg,s must be equal. The

two class-AB output stages M6M7 and M8/M9 ensure that equal currents flow out of the X

and Z nodes; the currents flowing through M2 and M4 are equal. M2 and M4 instantiate

Figure 4.2: The Oliaei-Loumeau CMOS Current Conveyor

grounded-gate amplifiers which lower voltage variations on the X node, resulting in lower X

impedance.

In this design M l 0 instantiates a 52pA current source, Ml 1 a 62pA current source, and

400mA fiows through each of Md and M8. The input impedance on the Y node is Ry=56.5kt2

and Cy=0.33pF; the input impedance on the X node is Rx=90.3i2 and Cx=10.7pF; the

impedance on the Z node is RZ=35.4kR and CZ=0.75pF.

4.1.2 Transconductor

The transconductor chosen for this design is based on a CMOS double pair [Par86], and is

shown in figure 4.3. Advantages of the CMOS double pair transconductor include its ability

to be used to implement a grounded resistor, and the absence of mismatch problems between

NMOS and PMOS transistors. Problems do exist, however, in tenns of Iinearity and

mismatch between the NMOS threshold voltages due to the body effect.

Each of the transistor pairs Ml and M2, and M3 and M4, implements a CMOS double pair,

with the equivalent Vg, given by the voltage difference between its two gates. Al1 transistors

operate in the saturation region. This is accomplished by guaranteeing that

Figure 4.3: CMOS Double Pair Transconductor

M2 and M3 are diode-connected and thus always operate in the saturation region. The CMOS

double pair MlIM2 has response

2 ' A = Keq( VG 1 - Vin - V T ~ ~ A ) (4.31,

where

and

Similarly

Thus, assuming that Vol = -VG4, and an NWELL process with VTpA = VTpB, we get

Figure 4.4 shows the DC response of the transconductor with WnLn = 1515 and Wfip = 45/5.

Power supplied are VDD - Vss = SV. The bias voltages were varied from 4 . 5 V to 0.5V,

resulting in AC resistance values ranging from 10.35kR to 46.70kQ (as measured on the full -

IV to IV range). This transconductor is the one on the Z node. Note the offset voltage of

200mV due to the mismatch in VTns, as indicated in equation 4.7. Resistances and linearities

are summarized in table 4.1. In the table Iinearity is calculated by taking the maximum

difference in current from a least squares line and dividing by the range of current; the result

is expressed as a percentage. Linearities are calculated on a 2Vpp range, a IVpp range, and a

O.SVpp range.

Similarly, figure 4.5 shows the DC response with W&, = 15A.2 and WdLp = 4511.2. Here

AC resistances ranged frorn 2.10kQ to 6.64kil (a resistance of 10.44kQ can be obtained by

limiting the input voltage to 1Vpp). This transconductor is the one on the

Resistances and linearities are summarized in table 4.2

X node.

Table 4.1: Equivalent Resistances and Linearities of Large Resistance Transconductor for

Bias Voltages Ranging from VDD-o. Sv to VDD+0.5V

Bias Voltage

(w.r.t. VDD)

+0.50V

2V Range

1.96%

1V Range

1.19%

0 . W Range

0.54%

Req (2V)

10.35kQ

Fige 1 Zv Range 1 Range 1 0.w Range / Reg (2V) 1

Table 4.2: Equivalent Resistances and Linearities of Small Resistance Transconductor for

Bias Voltages Ranging from VDD-O.5V to VDD+O.SV

The temperature dependence of the large resistance transconductor is simulated for

temperatures of -50°C, 3O0C, and 1 1O0C, and results are depicted in figure 4.6. In the -0.6V to

0.4V linear voltage range, the dependence is of 67 1 pprn/"C over the temperature range; in the

-0.35V to 0.15V range the dependence is of 336ppd0C. The dependence is calculated by

taking the percentage difference in resistance value over the temperature range, and dividing

by the difference in temperature (160°C). A technique for reducing temperature dependence

of the four MOSFET transconductor to 220ppmIoC is described in [LeegSa].

Figure 4.4: Large Resistance Transconductor I vs. V Response for 5 Control Voltages

/ ................... i ......................... ; ....................... i ....................... i i i i l r I I J I I I J I I

- 5 0 0 . OU O . 5 0 0 . ~ 0 ~ ' I I

1 .O VOLTS CL IN1 1 . 0

Figure 4.5: Small Resistance Transconductor I vs. V Response for 5 Control Voltages

Figure

/ - ............ "" ................................................................................... / l l i 1 l l l l i l l l l l l I

- 5 0 0 . OH O . 5 0 0 . ~ 0 ~ ' - 1 . 0 VOLTS [ L I N I 1 . 0

4.6: Temperature Dependence of Transconductor with I vs. V characteristics shown for T = -SO°C, 30°C and 110°C

4.1.3 Programmable Capacitor Array

A programmable capacitor array (PCA) controlled by NMOS switches, as shown in figure 4.7,

was used to implement programmable grounded capacitors. For the test chip, capacitor values

tied to the CCII's X node and the other has its Vin node tied to the CCII's Z node. In the

layout the two capacitors are placed side-to-side in order to ensure good matching between

capacitance values. In a complete FPAA, a PCA would normally inchde a greater number of

capacitors so as to adjust Q-factors and centre frequencies more precisely; Q-factor and

centre frequency adjustments can also be done using the transconductors.

Figure 4.7: Programmable Capacitor Array with Two Capacitors

The Lee-Gulak FPAA also used PCAs in order to realize capacitor programmability, with

switchable feedback capacitors on each CAB'S op-amp.

Advantages of a PCA include programmability using a digital configuration bit string, and

relatively close matching of capacitor values. Also, the programmed capacitance value is not

affected by noise. However, the range of capacitor values is not continuous. Also, modifying

the capacitance value during operation can result in glitches.

Figure 4.8: Continuously Programmable Capacitor

triode region to realize a linear capacitor, as depicted in figure 4.8 [Fos96j[Gra84].

Capacitance values are deterrnined by the control voltages VB and Vc. Advantages of this

approach include continuous programmability, and a lower die area. However, an advantage

of the PCA over this method is that a PCA is more easily and precisely programmable. In

addition, noise on the programming signals VB and VC can substantialIy Vary the capacitance

value. For these reasons a PCA has been chosen over the continuously programmable

capaci tor.

4.1.4 Buffer

The Y node in the Oliaei-Loumeau current conveyor has a finite impedance which must be

considered in calculating circuit responses. When the Y node is tied to the Z output of another

current conveyor, there is degradation in gain due to the parallel loading of impedance with

(b)

Figure 4.9: Impedance Mode1 for Connection Between Two CCZIs

Figure 4.10: Temperature-Stable Bias Circuit

the impedance tied to the Z node, as shown in the impedance mode1 in figure 4.9, where two

current conveyors, CC11 1 and CC11 2 are connected in this fashion. Figure 4.9(a) shows the

parallel impedances & and Ry, with Ry reducing the gain produced by CC11 1. For this

purpose, a unity-gain buffer with infinite input impedance is used. Here, an op-amp is used in

a unity gain feedback configuration, as shown in figure 4.9(b). Note that here the op-arnp does

not limit the bandwidth of the CAB since the bandwidth of the unity gain buffer is equal to the

unity gain frequency of the op-arnp, which is higher than the desired lOMHz bandwidth. The

op-amp was designed for a power dissipation of 4mW and unity-gain bandwidth of 43MHz;

the design was done using the PowerDesign tool [Rez95].

4.1.5 Bias Circuit

The bias circuit used to generate the Vnl and Vpl voltages for the current conveyor is a

temperature-stable circuit [Joh97]. Its schematic is shown in figure 4.10. The bias circuit

gives transistor transconductances which do not Vary with temperature.

Figure 4.1 1: Transmission Gate

4.2 Interconnection Network

4.2.1 Transmission Gate Response

Unlike switches in a digital FF'GA, switches in an FPAA must be carefully chosen so as to

maximize linearity and minimize parasitics such as ON-resistance and capacitance, and

minimize signal coupling when turned OFF. A pass transistor in the signal path introduces

non-linearities. For this implementation, a transmission gate, illustrated in figure 4.1 1, was

chosen as a switch for the interconnection network rather than a pass transistor.

Due to the non-polarity of MOSFET transistors, the analysis of the transmission gate can be

done either for Vin > Vaut or vice versa. We will assume Vin > Vaut. As long as

and

then both transistors operate in the triode region. The current through the NMOS transistor is

equal to

Similarly the current through the PMOS transistor is equal to

Assuming matched transistors, where

then

'TOT = In + I P = K ( 5 - 1 VTnI - 1 VTpl) ( Vin - Vour)

and the transmission gate is equivalent to a linear resistor with resistance

In order to obtain an ON resistance of less than 2008 we need K greater than 1 .5rnAN2. In a

typical0.8pm process this is achievable by using W&,=160.0/0.8.

Two models will now be presented to demonstrate the effect of transmission gate resistance on

circuit performance.

4.2.2 'Ikansmission Gate Into X Node

Figure 4.12 shows the small signal mode1 for an output current IZ flowing through a

transmission gate and into the X node of another current conveyor. Here RZ and CZ are the

output resistance and capacitance, respectively, of the first current conveyor; Rx and Cx are

the input resistance and capacitance, respectively, of the X terminal of the second current

Figure 4.12: Small Signal Mode1 of Transmission Gate Connection to X Node

n

.......... ............ . . . . . . . . . .

........ .:. .......... .:. . . . . . . . . . . . . . . . . . . . . . . ........... -9.60mL..I.. .................... .. . . . . . . . . " v .........................

t 1 1 1 1 1 1 1 ~ 1 1 1 1 1 1 1 1 ~ 1 1 1 1 1 1 1 1 ~ 1 1 1 1 1 1 1 1 ~ 1 8 1 1 1 1 1 1

10.0k 100.0k 1 . O x 10. O x 1 . O k hertz 1 0 0 . 0 ~

Figure 4.13: Efect of RT (Magnitude, top; Phase, bottom) on IX, for RT ranging from 0Q (top curve), 100Q 200Q and 1 ka

conveyor; RT is the equivalent resistance of the transmission gate. When used in this

configuration, we desire to have Ix approximately equal to IZ. Equation 4.16 gives the ratio of

Ix to IZ, taking into account al1 parasitic impedances and the equivalent resistance of the

transmission gate.

Simulation results shown in figure 4.13 shows the effect of RT for values of RT of OQ 100Q

20021, and 1 kQ and values of Rz, Cz, Rx, and Cx as determined in section 4.1.1. The effect

of RT is negligible when RT « RZ; for RT=200Q there is a 2% reduction in magnitude and

less than 0.01 " phase difference, as compared to the RT=OQ case.

4.2.3 Transmission Gate Into Y Node

Figure 4.14 shows the smalI signal mode1 for an output voltage VZ, passing through a

transmission gate, and driving the Y node of another current conveyor. In this case the Vy to

Figure 4.14: Small Signal Mode1 of Transmission Gate Connection tu Y Node

VZ ratio is given by equation 4.17, where we desire to get Vy equal to Vz.

In this case, since we assume that ROA is very large (1 Mn), RT will have a negligible effect

on circuit performance; for RT=îOOQ we get a reduction in Vy of 0.02%.

4.3 Test Chip

A CMOS test chip, designed in the 0.8pm BiCMOS process available from Norte1 [Hadgl],

was fabricated. The chip contains four current conveyor-based CABS and a transmission gate-

based interconnection network. Figure 4.15 shows a block diagram of the chip. Each circle

represents a transmission gate connecting the two crossing wires. The X input on each CAB

Figure 4.15: Test Chip Schematic

adders and subtractors. The current conveyors are organized in a bipartite architecture, with

connection between CCns of different groups.

The layout was generated using the BALLISTIC EOwen95, Owen961 layout language.

BALLISTIC circuit descriptions are parameterizable thus making it easier to migrate to new

technologies. An approach to designing a FPAA using BALLISTIC was presented in

[DMe96].

Figure 4.16 shows a die photograph of the chip. Table 4.3 gives the area requirements for the

CABS, interconnect, core, and total chip. The chip operates with a single 5V power supply.

On each of the four outputs is an output buffer which drives the pads and which has a 5 0 0

output impedance. HSPICE simulation of the buffer shows that for a 5pF load, the bandwidth

is in excess of lOOMHz, and thus does not affect bandwidth measurements presented in the

next section. At lOMHz, the phase difference is 3.91" and magnitude loss compared to DC is

0.02dB. Its linearity is approximately 30dB, with an output signal swing of 300mV. The

power dissipation of the buffer is 28mW.

1 Unit 1 Area(pmxprn) 1

1 chip 1 3413.8 x 1483.8 1 core

Table 4.3: Area Requirements for Test Chip

1551.8 x 741.2

Figure 4.16: Die Photograph of Test Chip

48

The following subsections describe the test results obtained from the prototype chip.

4.4.1 Amplifier

An amplifier is configured by tuming on the transconductors on the X and output nodes.

Figures 4.17 and 4.18 show the steady state response of an input sine wave at SOOkHz, at high

and low amplifications, respectively. Figure 4.19 shows the frequency response of the

amplifier at four different gains. The 3dB points were measured at 1 1 to 13MHz and are in

agreement with current conveyor theory which states that bandwidth should be constant.

Gains Vary from 2 to 14dB. In al1 four cases, there is a small bend at approximately 20MHz,

possibly indicating a zero in the frequency response.

The total harmonic distortion was measured at 2.89% (30.8dB) for a 10kHz 0.5Vpp input sine

wave (the input wave had a THD of 0.92%). Spectral output is shown in figure 4.20. The

third-order distortion component is high; a possible solution to this problem is to use a

transconductor more immune to odd-order distortion.

Output noise of the amplifier for a bandwidth of 12MHz was measured as 1 1.52mVm,,

resulting in a signal-to-noise ratio of 38.8dB for a IV output.

Power dissipation for the test chip in the amplifier configuration is 162mW for SV operation.

This compares well with simulation results of 165.3mW; simulations also show that the

power dissipation of each current conveyor is 4.9mW. Most of the power dissipation is Iost in

the chip's output buffers, which each consume 28mW (included in the 162mW).

4.4.2 Integrator

An integrator is configured by turning on a CAB'S output capacitor and the transconductor on

the X node. The steady state response of the integrator is shown in figure 4.21, and the

frequency response is shown in figure 4.22. As expected the output signal lags the input

signal by 90".

Figure 4.1 7: Steady State Response of High-Gain Amplifer - V, Top, Vo,, Bottorn

Figure 4.18: Sfeady State Response of Low-Gain Arnplijier - KI, Top, Va,, Bottom

4.4.3 Differentiator

A differentiator is configured by turning on a CAB'S output transconductor and the capacitor

on the output node. The steady state response of a differentiator is shown in figure 4.23, and

the frequency response is shown in figure 4.24. As expected the output signal precedes the

input signal by 90".

Ranget -20 d B m Rae BWi 1 7 000 Hz VBWI O f f

l e - A u g - 1995 1 4 1 28 Swp f i m a r 174.4 mSoc

Range* -20 d E m ROO BWS 17 ooo HZ vew. occ

1 8 - A u g - 1 Q Q S 14a 2 4 S w p T i m o i 174.4 m S o c

E. C o n C o r i 1 2 500 000 Hz S p a n i 25 000 000 Hz

3

9. C o n t a r i 12 ÇOO 000 Hz Spani 25 000 000 H z -

C r n t r r r 25 000 H r

A V E R A G I NG AVG8 20 Sponi

Figure 4.20: Harmonic Distortion of the Amplijîer at 1 OkHz

Figure 4.21: Steady State Response of Zntegrator - b, Top, Vo,, Bottom

Swp 1 3 mm8 139.2 m S r c

Figure 4.22: Frequency Response of Integrator

Figure 4.23: Steady State Response of Diflerentiatur - V,, Top, V,,, Bottom

R-O ewa 1 7 OUP wx VBWI OFF s w p ~ l r n m r i'aa. z msœc

S t a r t r O HZ

A V E R A G f N t AVGi 10

Figure 4.24: Frequency Response of Diigerentiator

4.4.4 Adder

An adder is instantiated on the FPAA as depicted in figure 4.25 Weighted input currents are

generated by CABS 1 and 2. The two currents are then fed into the X terminal of CAB 3. Due

to Kirchhoff's current law, the currents add up at that node, with the total current being

replicated at the output node of CAB 3. To convert to a voltage signal the currents are fed into

a transconductor at the output node of CAB 3.

The steady state response of an adder with 200kHz and lMHz input waves is depicted in

figure 4.26. The response shows that the two signals are added together.

Figure 4.25: Instantiation of Adder on Test Chip

Figure 4.26: Steady State Response of Adder to 200kHz and IMHz Inputs

4.4.5 Low Voltage Testing

As digital ICs go to lower linewidths and lower power supplies, analog design for low power

supplies will become increasingly important. Thus far tests for the prototype chip have been

done with a 5V power supply. In this section successful test results are presented for a power

supply of 4V.

Figure 4.27 shows the response of an amplifier at high gain, to a lOOkHz input sine wave,

shown on top. Figure 4.28 shows the same amplifier and same input sine wave, but with a

Tests were also conducted for a 3V power supply, but were unsuccessful.

Figure 4.27: AmpliJier Opera?@ a? 4V with High Gain - b,, Top, Vaut Bottom

Figure 4.28: Amplijîer Operating at 4V with Low Gain - y,, Top, Vaut Bottom

4.4.6 Summary of Test Results

Test results confirmed functionality of the CAB configured as amplifier, differentiator, and

integrator. Amplification was demonstrated for various gains, and in accordance to theory, the

bandwidth of the amplifier is constant with gain. A bandwidth of 12MHz was obtained for the

amplifier, and a total harmonic distortion of 2.89%.

Results have shown that significantly improved bandwidths have been achieved relative to

existing PAAS. However, the increase in bandwidth has resulted in circuits with lower

signal-to-noise ratio and linearity than existing commercial FPAA architectures (see

Appendix B for a summary of commercial FPAA performance results). Circuit techniques

achieving better noise and linearity performance at high bandwidth should be examined more

closely in future research.

Maximum GT 1 14dB

Parameter

Power Supply

Power

f -3d~

THD 1 2.89%

Resul t

5V

162mW

1 lMHz

functionality

SNR (IV Output, 12MHz BW)

amplifier, integrator,

differentiator, adder

38.8dB

Table 4.4: Summary of Test Chip Results

Based FPAAs

This chapter presents a current conveyor-based FPAA architecture, as well as a fully-

differential CAB. The FPAA, described in section 5.1, is modeled after the Zetex TRAC.

Section 5.2 describes a fully differential current conveyor block; then a potential fully-

differential CAB which uses the four MOSFET transconductor and which can also realize a

four-quadrant multiplier is introduced.

5.1 Current Conveyor Implementation of the Zetex TRAC

5.1.1 Architecture

The Zetex TRAC was introduced in chapter 2. It is a bipolar design achieving 4 MHz

bandwidths. Its noteworthy feature is the absence of switches in the signal paths, resulting

from the hardwired interconnection network. This can boost performance by fimiting the

Transconductor, programmable capacitor, and switchable

UO I/O I/O VO Figure 5.1 : TRQC-Like CMOS CUI-Based FPAA with 6 CABS

To Bias Circuitry To CC11

Vni O j T O V n i out

Figure 5.2: Switchable CCII Mechanism

parasitics in the routing and can result in greater linearity. The challenge we face in this

section is whether by using current conveyors, the performance of the TRAC can be upgraded

to beyong lOMHz, in a CMOS process rather than a bipolar one.

A CMOS CCU-based TRAC design includes CABs, similar to those used in chapter 4, which

are arranged in a manner as depicted in figure 5.1. Hardwired connections are used to route

voltage signals between subsequent CABs. The leftmost pins act as inputs and the rightmost

pins act as outputs. The intermediate pins can be configured both as inputs and outputs. To

configure a pin as an input, the previous CAB whose output is connected to the pin, must be

turned off. This is accomplished by turning off the CCII's bias currents, as shown in figure

5.2. This approach is similar to that proposed for the Prémont et al architecture, but could

result in a significant waste of silicon area if too many CABs must be turned off.

Notice that in this architecture, each current conveyor has two 2 terrninals. Terminal Z1 acts

like the Z terminal described previously. Terminal 22 is switchable; that is, the current

flowing out of 2 2 can be turned on or off using a programming bit. This allows the

prograrnming of an adder different from the one in section 4.4.4, as shown in figure 5.3.

Inputs Vini and Vin* are converted to currents through the respective resistors Rini and Rinl

Vin i

Vin2

Figure 5.3: Adder on the CCII-Based TRAC-Like Circuit

The currents are then summed ont0 resistor ROUI, producing output voltage V,,,.

vaut ' i n 1 ' i n 2 - = - +- Rout ' i n ~ ' i n 2

The 22 output is realized by adding four transistors in the output stage of the current

conveyor, as depicted in figure 5.4.

Figure 5.4: Switchable Z Output Mechanisrn

5.1.2 Layout

A layout for the FPAA in the 0.8pm CMOS process is shown in figure 5.5. Programming

memories have been included. The TRAC array occupies 5000 x 1500 pm2, including

Memory and control logic Analog array -

Figure 5.5: Layout of TMC-Like FPAA

memories and pad frarne. The chip is currently under fabrication in the Norte1 process.

5.1.3 Simulation Results

Figure 5.6 shows a biquadratic filter (biquad) embedded ont0 the FPAA. Four CABS are used,

and two are turned OFF. One is used as an amplifier, two are used as differentiators, and one

is used as an adder. The solid, bold lines indicate connections within the FPAA, which are

used to configure the biquad. The dotted, bold lines indicate connections which are externa1

to the FPAA. The response of the filter is given by equation 5.2.

VOL', - - - -4 Vin R,(l+sR,C,+sRlR2C,C2) (5.2)

By choosing RICl = 4R2C2, we get a low-pass transfer function with poles at mp=1/2R2CZ A

band-pass transfer function is obtained at the output of one of the differentiators.

Simulation results of the biquad are shown in figure 5.7 for three centre frequencies, varying

from 3.7MHz to 7.3MHz. Centre frequencies are changed by modifying the values of the on-

chip resistances and capacitances RI, R2, Cl, and CL. LOW-pass and bass-pas outputs are

shown. A potential problem with the low-pass response is that in the high frequency band,

attenuation is limited to approximately 27dB. This may be due to a possible zero at 20MHz,

as evidenced by the test results in the previous chapter.

Figure 5.6: Biquad Embedding onto TRAC-Like FPM

In figure56 the thick solid lines indicate active wires on the FPAA IC, while dotted lines

indicate wires external to the FPAA. A high-pass output could be added by using the 22

output of the second differentiator and feeding it ont0 a resistor. Given test chip performance

Figure 5.7: Low-Pass and Band-pass Biquad Responses

5.2 Fully-Differential Implementation

Al1 current conveyor blocks presented thus far have employed single-ended signalling.

However, fully-differential signalling has advantages in terms immunity to common-mode

noise. A potential fully-differential current conveyor amplifier block is depicted in figure 5.8,

and includes two CCII, and two resistors. Here the current Ix is equaI to (Vin+-Vin-)&.

That current then flows across RZ, producing an output (Vmt+-Vout-)=(RZ/RX)(Vin+-Vin-).

Figure 5.8: Fully-Dgerential CCII Amplifier

Another way to realize a fully-differential amplifier is through the use of the four MOSFET

transconductor, introduced in chapter 2. The four MOSFET transconductor has the advantage

of having the capacity to realize a four quadrant multiplier, and can be used to change the

polarity of a signal. A potential CAB utilizing this transconductor is shown in figure 5.9. The

input voltages cannot be put on the Y nodes since that would result in a nonlinear response

from the transconductor. Instead, inputs are put on the transconductor directly. Note that this

results in a low-impedance input to the CAB.

The CAB, when used in conjunction with the comparator introduced in chapter 3, can be used

to realize a precision rectifier. In such a realization, the output of the comparator controls the

transconductance of the input transconductor, and either lets a signal through, blocks it, or

Figure 5.9: Fully-Dwerential CAB Utilizing the Four MOSFET Transconductor

5.3 Summary

This chapter has presented a design for a field-programmable analog array, with an

architecture similar to that of a commercially available FPAA. The advantage of the new

method is that potentially greater bandwidths are achieved, while using CMOS technology

instead of bipolar technology. AIso, a fully-differential configurable analog block, which uses

the four MOSFET transconductor has been presented.

cnapter O:

6.1 Summary and Conclusions

Current field-programmable analog array designs operate at 1 OOkHz frequencies. However,

video bandwidths are in the order of 10MHz. In this thesis the circuitry necessary for the

development of field-programmable analog arrays operating at video frequencies, has been

presented. Current conveyors were seen as being a viable option in achieving a video

frequency FPAA.

A field-programmable analog array consists of configurable analog blocks, interconnect, as

well as memories capable of configuring the array into useful analog circuits. Chapter 2

reviewed the FPAA circuits in the literature, and discussed obstacles in the development of a

high-frequency FPAA. Among these was the low bandwidth of the simple operational

amplifier.

Chapter 3 introduced the second-generation current conveyor, an analog building block with

properties similar to those of an operational amplifier, and which has the potential for high

frequency operation. A current conveyor can be implemented in an area similar to that of a

simple operational amplifier. Current conveyor building blocks were described, including a

novel voltage comparator. Also, reasons were stated as to why a current conveyor is

preferable over a simple operational amplifier.

Chapter 4 presented the design and implementation of a configurable analog block and

interconnect for a field-programmable analog array designed to operate at video bandwidths,

using current conveyors. A test chip was fabricated in a O.8pm CMOS process. Test results

demonstrated bandwidths of over lOMHz for a current conveyor-based amplifier, as well as

functionality of an integrator, differentiator, and adder. This was seen as a first step towards

the development of a complete current conveyor-based FPAA.

CAB. The CMOS single-ended FPAA architecture is similar to that of the bipolar Zetex

TRAC, a commercial FPAA. Functionality in simulation of the TRAC-like WAA was

demonstrated using a biquad filter embedded ont0 the FPAA. Given the IC results of the

initia1 test chip, and the simulations of the TRAC-like FPAA, bandwidth of the CMOS TRAC-

Iike FPAA should be well in excess of the 4MHz bandwidth of the commercially available

bipolar TRAC. A new test chip including the TRAC-like FPAA is currently being fabricated.

The following section suggests research topics for future FPAA-related research.

6.2 Suggestions for Future Research

As their bandwidths surpass video frequencies, FPAAs will find increasing application in a

number of areas. The following subsections describe research topics that will be of interest

now that current conveyor-based CABS and interconnect have been developed. Among these

will be field-programmable mixed-signal arrays, CAD tools, memories, low power-supply

FPAAs, and well as FPAAs with even higher bandwidths.

6.2.1 Field-Programmable Mixed-Signal Arrays

Mixed-signal ICs are the fastest-growing segment of the integrated circuits market, growing

from a 26% share of a $4.OB market in f 994 to an estimated 31% share of $9.8B in 1999

[ICE94]. This is due in large part to decreasing IC linewidths, leading to more and more

analog functionality finding its way ont0 digital circuits.

Field-programmable mixed-signal arrays (FPMAs) along with associated CAD tools, will

offer a medium on which to prototype mixed-signal circuits. A field-programmable mixed-

signal array is an integrated circuit containing both an FPAA block and an FPGA block,

connected via signal conversion circuitry such as configurable converter blocks [Chow94,

Chow95, Lee961, comparators, level shifters, as well as direct wires. A conceptual FPMA is

shown in figure 6.1. The configuration bit string contains configuration data for both the

FPAA and FPGA, as well as converter configuration. Converters may be of fixed width,

Analog in Digital out

Analog out Digital in

l l l l l l l l l 1 l l l l l l l 1 l 1 1 1 1 1 1 1 1 1

shift in interconnection network I FPA A I FPGA configuration I shift Out

Figure 6.1: Conceptual Field-Programmable Mixed-Signal Array Diagram

An early FPMA design, called MADAR [Chow95], was developed at the University of

Toronto. The FPAA section is based on the Lee-Gulak Transconductor FPAA, and the FPGA

section on a University of Toronto FPGA tile [Chow93]. The FPMA uses a 2741-bit

configuration string. Circuit applications of MADAR included a dual slope AD converter

and a pulse-width modulation DIA converter.

Other FPMA proposals were described in chapter 2 and include the Faura et al FPMA

[Fau97], as well as the future plans by Motorola Pra96J. Also, some versions of IMPYs EPAC

include on-chip signal converters [IMP].

6.2.2 CAD Tools

As discussed in chapter 2, computer-aided design (CAD) methodologies are used to map

designers' circuits ont0 FPAA architectures, and to download the rnappings ont0 the FPAA

ICs. Al1 existing commercial FPAAs, as well as the Lee-Gulak transconductor FPAA, are

programmed using a PC-based CAD tool.

Thus far features included on FPAA CAD tools have included schematic capture and entry,

possibility to specify interna1 and external connectivity, and simulators to simulate the

synthesizing capability as well in order to map the circuit ont0 the FPAA. One CAD tool

includes a library of macro cells that can be placed on the array. Table 6.1 summarizes

features available on existing FPAA CAD tools.

Tool Schernatic

& Entry

Motorola [Mot971 1 I J 1 J 1 1

Lee-Gulak [Roi951

Zetex [~e t97 ] I

Macro

Table 6.1: Sumrnary of FPAA CAD Tool Capabilities

J

Once a complete current conveyor-based FPAA will have been fabricated, there will be a need

for an associated CAD tool. For the purpose of synthesis and resimulation, there will be a

need for an electrical mode1 of the CAB. This should include input and output impedances of

the current conveyor, as well as equivalent impedances of the transconductors, capacitors, and

switches.

Interna1 Connectivity

Entry

Of future interest will be the development of CAD tools for FPMAs. Such a CAD tool should

have the capability to synthesize a high-level description in terms of both analog and digital

components, and should include appropriate mixed-signal simulation capabilities.

J

6.2.3 FPAA On-Chip Mernories

On-chip memories were not included in the design of the FPAA circuitry in this thesis.

However, a complete FPAA must include on-chip programming memories. These mernories

include digital SRAM shift registers, as well as multi-values memories. Now that the CAB

and interconnect have been successfully designed, mernories must also be designed.

External Connectivity

Entry I

1

Digital SRAM bits are used to program CAB functionality, and interconnection switches. As

Simulation

continuously-variable quantities such as transconductance.

6.2.4 Low Power Supply Voltage

In this thesis, al1 circuits were designed to be used with a single 5V power supply in a 0.8pm

CMOS technology. However, with the increase in the use of mixed-signal techniques, there

will be pressure to design analog circuits with lower power supply voltages. This is already

evident in many deep subrnicron designs which use a single 3.3V power supply or lower

[Fer96, Bas97, Ded971. A current conveyor providing rail to rail swings at low power

supplies must be developed.

6.2.5 Performance Limitations

In chapter 2, performance limitations of FPAAs were described. Some performance

limitations included the speeds of op-amps, transconductors, and comparators. By using

current conveyors rather than simple op-amps, the performance of FPAAs has been increased

from audio bandwidths to video bandwidths. However, current conveyors as they stand, as

well as existing transconductors, will not allow an extension of CMOS FPAAs to RF

bandwidths. For that purpose, new architectures will need to be studied.

As well, FPAA performance parameters other than bandwidth must be examined and

improved upon. Such parameters should include versatility and linearity.

Appendix A: Empirical Cornparison ok- Area Requirements for Digital and Analog Filters

-- -

A.l Introduction

Studies have attempted to compare analog and digital circuit performances, in terms of speed

and power consumption, for various applications. Variations in analog circuit performance as

transistor sizes decrease have been studied in [Vitgo]. Another study by [DeH96] looks at

comparing area requirements for various digital circuits and techniques.

This appendix gives an empirical area comparison between circuits implemented in the digital

domain and their counterparts implemented in the analog domain; the comparison studies

specifically digital and analog filtering techniques. In both domains, results are derived for

both parametrically-programmable and non-programmable circuits. In the digital domain, the

mode1 is valid for different bit precisions.

The area models include the areas of building blocks such as registers and operational

amplifiers, and also include area for routing. A treatment of both has been included, with

emphasis on the area required by building blocks.

Sections A.2 and A.3 develop the area models for digital and analog filters, respectively.

Section A.4 compares the area requirements for both types of filters.

A.2 Digital Filters

A.2.1 Definitions

A digital filter is a filter operating in discrete time, with discrete, binary signal values.

' b o approaches are possible when implementing digital filters: finite impulse response (FIR)

Figure A. I : Structure of Znjinite Impulse Response (IZR) Filter

filters and infinite impulse response ( I I . ) filters. Both types are realized using registers,

multipliers, and adders. F R filters are non-recursive and IIR filters use recursion. I I . filters

have the general structure shown in figure A. 1, and their transfer function is given by equation

A.1.

N- 1

Only IIR filters will be considered in this chapter, though the mode1 could easily be extended

to FIR filters.

A.2.2 Area Requirements for Digital Filters

Table A.l lists dimensions for standard cells in the Mississippi State University's CMOS

standard ce11 library [MSU97]. The first column gives the type of circuit block and the last

column gives the areas in h2 units, not including the power rails, which occupy 1Oh each. The

standard cells are used to build larger-grained blocks such as adders, multipliers, and registers.

The MSU cells are designed for 2.0pm (kl .Opm), 1.2pm ( k O A p r n ) , and 0.8pm (k0.4pm)

technologies. Transistor sizes for the inverter are 8h2 for the NMOS transistor and 26h2 for

the PMOS transistor. Contact sizes, including metal overlap, are 16h2. Average active area

Area (h2) J

Inverter 1160

1 D Flip-Flop 1 16066 I

1 Full Adder 1 15474 1

Table A. 1 : Areas of Standard Cells in Mississippi State University Library

For the calculations presented in this section, we will assume that a k-bit full adder uses k

1-bit full adders. Sirnilarly, a k-bit register is implemented using k D-flip-flops. Routing area,

which will include power rails, will be considered later.

There are many ways of implementing digital multipliers [Wes93][Man9 l][Lew95]. One

technique adds shifted instances of the input signal, as illustrated in figure A.2. A constant M

can be represented by a summation of powers of 2. In figure A.2, we multiply the input signal

A by the constant M = 53/64. The constant 53/64 is equal to the summation of 112, 1/4, 1/16,

and 1/64. It is easy to multiply a binary signal by a power of 2 since the result is sirnply a

shifted version of the input. Thus, to multiply the input signal A by the constant M, we add

together shifted versions of A to produce the product. This method uses less area than an

equivalent multiplier with the same precision.

Figure A.2: Multiplication of Signal A by Constant 43 Using Only Adders

For each multiplier in an N-tap, k-bit IIR filter, up to (k - 1) k-bit adders could be required.

For a programmable filter, al1 (k - 1) adders are necessary, as well as programming circuitry.

(53/64) A "l Adder 'FI Adder »6

b »2 -

Adder

required for each tap, as well as k2 AND gates to control the inputs to the adders. AND gates

are built using the NAND and NOT cells, and a typical SRAM bit uses approxirnately 650h2.

For a non-programmable filter, some of the bits in the coefficients might be zero, thus

eliminating the requirement for an adder; this is illustrated in figure A.2, where there is no

need to add results of multiplying the input signal by 1/8 or by 1/32. Since there is equal

probability, for a k-bit coefficient, that each bit could be a O or a 1, we will assume that k/2 of

the bits in the coefficient are 1, and thus for a non-programmable filter, on average (kl2 - 1)

adders are required for each tap.

For both programmable and non-programmable IIR filters, we require (2N - 1) multipliers,

(2N - 2) adders to add the results of the multiplications, and (N - 1) registers.

The height of the standard cells in the Mississippi State University's library is 58h. In

addition, each of the two power rails uses 10h, and about 10h are left between the cells for

routing area. Thus, for the area estimates presented in this section, the area requirements are

multiplied by 1.5 in order to take into account routing area.

Equation A.2a gives an estimate of the area required for an N-tap, k-bit precision

non-programmable FIR filter; equation A.2b gives the estimate for a programmable IIR filter.

In equations A.2a and A.2b, ARk and AAk represent the area required for a k-bit register and

adder, respectively. In equation A.2b, As is the area of one SRAM bit and AAND is the area of

one AND gate. We see that the following relationships hold true.

Now, areas of IIR filters can be tabulated. The areas are calculated for 3-tap, 5-tap, 9-tap, and

17-tap filters. Precisions of 4 and 8 bits are used. Table A.2 summarizes the areas.

- - - - - --

Table A.2: Areas in h2 of Programmable and Non-Programmable IIR Filters

Precision and programmability

4-bit non-programmable

4-bit programmable

8-bit non-programmable

8-bit

Two programmable, 6-bit F R filters are described in [Pea95]. The 10-tap filter has an area of

6 4 ~ h ~ , and the 8-tap filter has an area of 2 8 . 8 ~ ~ ~ ; both are designed in a 0.5pm CMOS

process. An 8-tap, 6 bit programmable FIR filter is described in [Tho95]; its area is 18. M h 2

in a 0.8pm tecl-inology. Even though these filters include the area of input and output

conversion circuitry, the areas are significantly higher than the areas given in table A.2, and

thus shows that the above mode1 is a lower bound for digital filter areas.

Many filtering applications require fewer than 10 bits of precision; some of these include

high-speed data communications and video circuits [Joh97]. Modern Nyquist-rate A/D

converters can provide up to 15 bits of precision [Kwa97].

3-tap

1028388

2338248

3913656

A.3 Analog Filters

l l140g6 I

A.3.1 Definitions

Analog filters can be divided into two categories: continuous-time and discrete-time filters.

16631040

5- tap

1963932

4321680

7270248

programmable 1 1 31664928

9- tap

3835020

7678272

13983432

61732704

17-tap

7577 196

16222272

27409800

The transfer function of an analog, continuous-time filter is given by equation A.4. The filter

is characterized by its poles, pi, and its zeros, zj. We can obtain the frequency response of the

filter by replacing s by jo in equation A.4.

There are many different physical realizations of analog filters. One type, called "passive

filter" [Sed89], uses resistors, capacitors, and inductors. Another type, called

"switched-capacitor filter" [Joh97], uses operational amplifiers, capacitors, and replaces

resistors by a transistor-capacitor structure; switched-capacitor filters operate in discrete time.

The type studied in this section, called "active RC filter" [Sed89], uses resistors, capacitors

and operational ampli fiers.

Active RC and switched-capacitor circuits can be further categorized into single-ended and

fully-differential circuits. In this section, fully-differential filters are used. Note though that

fully-differential circuits use approximately twice the area of single-ended circuits, but result

in lower common-mode noise.

A.3.2 Area Requirements for Analog Filters

There does not exist a "general" analog active RC filter structure, as there exists for FIR

filters. However, active filters are built using operational amplifiers, capacitors, and resistors

or transconductors; high order filters can be achieved by cascading iow order filters.

The areas, including power rails, of typical fully-differential analog building blocks in a

1.2pm CMOS process are given in table A.3 [Lee95a]; for a 1.2pm process, h = 0.6pm. It is

important to note that here, devices cannot be scaled as easily with decreasing transistor size,

since scaling down affects impedances and noise levels. Capacitors and resistors are used in

non-programmable filters; in programmable filters, programmable capacitor arrays replace

capacitors, and transconductors replace pairs of resistors.

Building Block

Capacitor (20 pF)

Capacitor Array

Transconductor with Programming Circuitry

2 Resistors (10 ka each)

Table A.3: Areas of Fully-D~gerential Analog Building Blocks in 1.2 pz CMOS Process

Area @m2)

60000

126000

130200

540

Operationa1 Amplifier

For the area analysis, we will look at the filter structures presented in table A.4; references for

the filters are given in the table.

50000

We now consider routing area. The areas for the building blocks given in table A.3 include

138900

power rails. Furthemore, given the datapath architecture of analog circuits, and the low

number of blocks to be stacked, al1 blocks can be stacked in a row, and no extra area is

required to route signals outside the area required by the power bars.

Order n

Capacitors N~~~

Fil ter

(A) Integrator [Papo80 p.2901

(B) Differentiator [Papo80 p.2901

(C) Low Pass [Sed89 p.7793

(D) High Pass [Sed89 p.7791

(E) General Filter [Sed89 p.7791

(F) Biquad ELee95a p. 1011 l

(G) Tow-Thomas [Sed89 p.8041

Table A.4: Building Block Requirements for Various Analog Filters

equation A.5b gives the estimate for a programmable active filter.

NO and Ag represent the number and area of operational amplifiers. NREs and ARES represent

the number and area of resistors. NCAp and ACAP represent the number and area of capacitors.

Nxc and Axc represent the number and area of transconductors. NPCA and APCA represent

the number and area of programmable capacitor arrays. It is more difficult in the analog case

to obtain order bounds paralleling those in equations A.3a and A.3b since the architectures of

analog filters are Iess rigorously structured than the regular ones of FIR filters.

Areas for the seven filters described in table A.4 are tabulated in table AS.

Fil ter Area -Programmable (h2)

1 (B) Differentiator 1 1 204 O00 1 473 800 I

Area - Non-ProgrammabIe (h2,

(A) Integrator

1 (D) High Pass 1 1 565 700 1 475 300 1 1 (E) General Filter 1 2 269 100 1 808 700 I

1 204 O00

1 (F) Biquad 1 3 131 400

473 800

Table A S : Areas of Programmable and Non-Programmable Active Filters from Table A.#

(G) Tow-Thomas

A.4 Area Comparisons

A.4.1 Cornparison

In order to compare digital and anaIog filters in a fair way, we must compare same-order

3 993 700 II

1 092 500

z-domain filter is the bilinear transformation [Opp89]. The bilinear transformation replaces s

with a function of z according to equation A.6.

This has the effect of repIacing an Mth order continuous-time filter by a discrete-tirne filter

with M delays, or M+l taps.

Table A.6: Area Comparison Between Same-Order Non-Programmable Filters

Order

Table A.7: Area Comparison Between Same-Order Programmable Filters

Digital -

Bits (h2)

Order

Cascading lower-ordered filters is an often used method of achieving an Mth order analog

filter; the resulting order is the sum of the orders. Table A.6 gives area cornparisons for

Area (h )

Digital Ares - 8 Bits (h2)

ADig : A*,,

Analog ( ~ 2 )

A ~ i g : A ~ n

precisions. The areas for analog filters are derived by using the largest area 2nd order filter, the

Tow-Thomas filter, and cascading as many as are required to obtain the desired order.

Comparison between the results for the digital and analog cases shows that analog filters

generalIy consume about one half to one third less area than their digital counterparts.

A.4.2 Study Conclusions

Area comparisons showed that analog filters consume approximately twice to three times less

area than their digital counterparts.

No mention was made as to the usage of N D and D/A convertors, as well as anti-aliasing and

reconstruction filters. In an actual signal-processing system, the inputs and outputs would

normally be analog signals, and thus there would be a requirement for signal convertors in the

digital filter. Such convertors were not considered in the area analysis, but would add more

area to the digital filters.

For the digital filters, precision of the filters was an easily definable criterion. In the analog

case, precision is defined in terms of quantifiers such dynamic range. These numbers are very

implementation-dependent, with 8-bit precisions being common and 12 to 16 bit precisions

being more difficult to obtain in CMOS technology. The ZSSCC97 Proceedings describe

CMOS analog filtering circuits with dynarnic ranges of 54dB (9 bits) up to 6OdB (10 bits)

[Nag97] [B as971.

Appendix B: Characteristics of Existing Commercial FPAAs

Characteristic 1 IMP EPAC5OE1 O Motorola 1 MPAAO2O Zetex TRAC020

Tec hnology

System clock 1 50OkHz 1 lMHz 1 not applicable

Power supply voltage

CABS

Bandwidth 1 125lcHz 1 200kHz 1 4MHz

CMOS switched-capacitor

SV

datapath architecture

Gain error 1 2.0% 1 not available 1 1.0%

CMOS switched-capacitor

Input signal range

Gain drift 1 30ppm/'C 1 not available 1 not available

bipolar continuous-time

SV

20

Noise 1 O . ~ ~ V M Z ~ . ~ (input) 1 3 8 n ~ / H z ~ . ~ 1 60dB SNR

SV

20

Vss-0.2V to vDD+o.2v

Total harmonic 1 -68dB 1 -46dB 1 6 2 d B

Vss+O.SV to V D d . 5 v

Dynarnic range 1 not available 1 not available 1 80dB

Vss+ 1 .SV to VDD- 1 .ov

distortion

Temperature range 1 O to 70°C 1 -40 to 85'C 1 O to 70°C

I

Table B. I : Characteristics of Existing Commercial FPAAs

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