DESIGN GUIDE Carrier Board - VIA Technologies,...
Transcript of DESIGN GUIDE Carrier Board - VIA Technologies,...
DESIGN GUIDE
Carrier Board for VIA SOM-6X80 Module
1.01-04242020-145700
Copyright
Copyright © 2018-2020 VIA Technologies Incorporated. All rights reserved.
No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies, Incorporated.
Trademarks
All trademarks are the property of their respective holders.
Disclaimer
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided in this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Technologies assumes no responsibility for the use or misuse of the information (including use or connection of extra device/equipment/add-on card) in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.
VIA Technologies, Inc. reserves the right the make changes to the products described in this manual at any time without prior notice.
Carrier Board Design Guide for VIA SOM-6X80 Module
Revision History
Revision Date Description1.00 08/22/2018 Initial release1.01 04/24/2020 Updated the reference schematics
iii
Carrier Board Design Guide for VIA SOM-6X80 Module
Table of Contents
1. Introduction ....................................................................................................................... 11.1 Document Overview ............................................................................................................................. 11.2 Acronyms Used ..................................................................................................................................... 21.3 SchematicConventions ........................................................................................................................ 3
2. GeneralCarrierBoardRecommendations ......................................................................... 42.1 PCB Stackup .......................................................................................................................................... 4
2.1.1 4-Layer PCB Stackup Example ........................................................................................................ 52.1.2 4-Layer PCB Impedance Control .................................................................................................... 5
2.2 GeneralLayoutandRoutingGuidelines ............................................................................................... 62.2.1 RoutingStylesandTopology .......................................................................................................... 62.2.2 GeneralTraceAttributeRecommendation .................................................................................... 72.2.3 GeneralClockRoutingConsiderations ........................................................................................... 8
3. VIASOM-6X80ModuleandSOMDDR3SODIMMSlotSpecificationOverview ................ 93.1 VIA SOM-6X80 Module Placement ...................................................................................................... 93.2 VIASOM-6X80ModuleMechanicalCharacteristics ............................................................................. 93.3 VIA SOM-6X80 Module and Carrier Board Dimensions ...................................................................... 103.4 SOM DDR3 SODIMM Slot ................................................................................................................... 11
3.4.1 SOM DDR3 SODIMM Slot Dimensions ........................................................................................ 113.4.2 SOM DDR3 SODIMM Slot Footprint ............................................................................................. 12
3.5 SOMDDR3SODIMMSlotPinAssignments ........................................................................................ 13
4. LayoutandRoutingRecommendation............................................................................. 164.1 HDMI Interface ................................................................................................................................... 16
4.1.1 HDMISignalDefinition ................................................................................................................. 164.1.2 HDMILayoutandRoutingRecommendations ............................................................................. 174.1.3 HDMIReferenceSchematics ........................................................................................................ 19
4.2 Ethernet Interface .............................................................................................................................. 204.2.1 EthernetSignalDefinition ............................................................................................................ 204.2.2 EthernetLayoutandRoutingRecommendations ........................................................................ 214.2.3 EthernetReferenceSchematics ................................................................................................... 22
4.3 USB Interface ...................................................................................................................................... 234.3.1 USBSignalDefinition ................................................................................................................... 234.3.2 USBLayoutandRoutingRecommendations ................................................................................ 244.3.3 USBReferenceSchematics ........................................................................................................... 26
4.4 COM and UART Interface .................................................................................................................... 274.4.1 COMandUARTSignalDefinition ................................................................................................. 274.4.2 COMandUARTLayoutandRoutingRecommendations ............................................................. 284.4.3 COMandUARTReferenceSchematics ........................................................................................ 29
4.5 LCD Interface ...................................................................................................................................... 304.5.1 LCDSignalDefinition .................................................................................................................... 304.5.2 LCDLayoutandRoutingRecommendations ................................................................................ 314.5.3 LCDReferenceSchematics ........................................................................................................... 32
4.6 Touch Panel Interface ......................................................................................................................... 334.6.1 TouchPanelSignalDefinition ....................................................................................................... 334.6.2 TouchPanelLayoutandRoutingRecommendations ................................................................... 334.6.3 TouchPanelReferenceSchematics .............................................................................................. 34
4.7 GPIO Interface .................................................................................................................................... 354.7.1 GPIOSignalDefinition .................................................................................................................. 354.7.2 GPIOLayoutandRoutingRecommendation ................................................................................ 35
4.8 I²C Interface ........................................................................................................................................ 364.8.1 I²CSignalDefinition ..................................................................................................................... 364.8.2 I²CLayoutandRoutingRecommendation ................................................................................... 36
4.9 SPI Interface ....................................................................................................................................... 37
iv
Carrier Board Design Guide for VIA SOM-6X80 Module
v
4.9.1 SPISignalDefinition ..................................................................................................................... 374.9.2 SPILayoutandRoutingRecommendation ................................................................................... 37
4.10 Audio Interface ................................................................................................................................... 384.10.1 AudioSignalDefinition ................................................................................................................ 384.10.2 AudioLayoutandRoutingRecommendations ............................................................................. 384.10.3 AudioInterfaceReferenceSchematics ........................................................................................ 39
4.11 SD Interface ........................................................................................................................................ 414.11.1 SDSignalDefinition ...................................................................................................................... 414.11.2 SDLayoutandRoutingRecommendations .................................................................................. 414.11.3 SDInterfaceReferenceSchematics .............................................................................................. 42
Carrier Board Design Guide for VIA SOM-6X80 Module
ListofFiguresFigure1: Schematicconventions......................................................................................................................... 3Figure2: MicrostripPCBstackupexample .......................................................................................................... 4Figure3: StriplinePCBstackupexample ............................................................................................................. 4Figure4: 4-LayerPCBboardstackupdetail ......................................................................................................... 5Figure5: Point-to-pointandmulti-dropexamples .............................................................................................. 6Figure6: Daisy-chainexample ............................................................................................................................. 6Figure7: Alternatemulti-dropexample .............................................................................................................. 6Figure8: Signaltracewidthandspacingexample .............................................................................................. 7Figure9: Differentialsignaltracewidthandspacingexample ............................................................................ 7Figure10: Suggestedclocktracespacing .............................................................................................................. 8Figure11: Clocktracelayoutinrelationtothegroundplane ............................................................................... 8Figure12: Seriesterminationformultipleclockloads .......................................................................................... 8Figure13: VIASOM-6X80moduleplacementexampleonthecarrierboard ....................................................... 9Figure14: CarrierboardwithVIASOM-6X80module(sideview) ........................................................................ 9Figure15: CarrierboardandVIASOM-6X80moduleheightdistribution(sideview) .......................................... 9Figure16: DimensionsoftheVIASOM-6X80module ........................................................................................ 10Figure17: Dimensionsofthereferencecarrierboard ........................................................................................ 10Figure18: DimensionsoftheSOMDDR3SODIMMslot(topview) .................................................................... 11Figure19: DimensionsoftheSOMDDR3SODIMMslot(sideview) ................................................................... 11Figure20: PCBfootprintoftheSOMDDR3SODIMMslot .................................................................................. 12Figure21: PCBfootprintoftheSOMDDR3SODIMMslotwithVIASOM-6X80module ..................................... 12Figure22: SOMDDR3SODIMMslotschematics ................................................................................................. 15Figure23: HDMIroutingtopology ...................................................................................................................... 16Figure24: HDMIdifferentialtracewidthandspacingexample .......................................................................... 17Figure25: HDMIsingle-endedtracewidthandspacingexample ....................................................................... 17Figure26: HDMIreferencecircuitry .................................................................................................................... 19Figure27: Ethernetroutingtopology .................................................................................................................. 20Figure28: Ethernetsingle-endedtracewidthandspacingexample .................................................................. 21Figure29: Ethernetdifferentialtracewidthandspacingexample ..................................................................... 21Figure30: Ethernetreferencecircuitry ............................................................................................................... 22Figure31: USBroutingtopology ......................................................................................................................... 23Figure32: USBdifferentialsignalroutingexample ............................................................................................. 24Figure33: USBdifferentialtracewidthandspacingexample ............................................................................. 24Figure34: USBhostreferencecircuitry ............................................................................................................... 26Figure35: USBclientreferencecircuitry ............................................................................................................. 26Figure36: COMandUARTroutingtopology ....................................................................................................... 28Figure37: COMandUARTreferencecircuitry .................................................................................................... 29Figure38: LCDroutingtopology.......................................................................................................................... 30Figure39: LCDreferencecircuitry ....................................................................................................................... 32Figure40: Touchpanelroutingtopology ............................................................................................................ 33Figure41: Touchpanelreferencecircuitry .......................................................................................................... 34Figure42: Line-in1&2referencecircuitry ......................................................................................................... 39Figure43: Headphonereferencecircuitry .......................................................................................................... 39Figure44: Monospeakeroutreferencecircuitry ................................................................................................ 39Figure45: Rightchannelspeakeroutreferencecircuitry ................................................................................... 40Figure46: Leftchannelspeakeroutreferencecircuitry ...................................................................................... 40Figure47: Onboardmicrophonereferencecircuitry........................................................................................... 40Figure48: SDroutingtopology ........................................................................................................................... 41Figure49: SDreferencecircuitry ......................................................................................................................... 42
vi
Carrier Board Design Guide for VIA SOM-6X80 Module
List of TablesTable1: Acronymsused ..................................................................................................................................... 2Table2: 4-LayerPCBimpedancecontrol ........................................................................................................... 5Table3: Recommendedtracewidthandspacing .............................................................................................. 7Table4: SOMDDR3SODIMMslotsample ....................................................................................................... 11Table5: SOMDDR3SODIMMslotpinouts ...................................................................................................... 14Table6: HDMIsignaldefinition ........................................................................................................................ 16Table7: HDMItraceproperties ....................................................................................................................... 17Table8: HDMIlayoutguidelines ...................................................................................................................... 18Table9: HDMIroutingtopologyandsignaltype ............................................................................................. 18Table10: Ethernetsignaldefinition ................................................................................................................... 20Table11: Ethernettraceproperties ................................................................................................................... 22Table12: Ethernetlayoutguidelines ................................................................................................................. 22Table13: Ethernetreferenceplane,signaltypeandroutingtopology ............................................................. 22Table14: USBsignaldefinition .......................................................................................................................... 23Table15: USBtraceproperties .......................................................................................................................... 25Table16: USBterminationoption,signaltypeandroutingtopology ................................................................ 25Table17: USBlayoutguidelines ......................................................................................................................... 25Table18: COMandUARTsignaldefinition ........................................................................................................ 27Table19: COMandUARTtraceproperties ........................................................................................................ 28Table20: COMandUARTtopology,signaltypeandlayoutguidelines .............................................................. 29Table21: LCDsignaldefinition ........................................................................................................................... 30Table22: LCDtraceproperties........................................................................................................................... 31Table23: LCDsignaltype,topologyandreferenceplane .................................................................................. 31Table24: LCDlayoutguidelines ......................................................................................................................... 32Table25: Touchpanelsignaldefinition ............................................................................................................. 33Table26: Touchpaneltraceproperties ............................................................................................................. 33Table27: Touchpanelsignaltype,routingtopologyandreferenceplane ........................................................ 33Table28: Touchpanellayoutguidelines ............................................................................................................ 34Table29: GPIOsignaldefinition ......................................................................................................................... 35Table30: GPIOtraceproperties ......................................................................................................................... 35Table31: GPIOsignaltype,topologyandlayoutguidelines .............................................................................. 35Table32: I²Csignaldefinition ............................................................................................................................ 36Table33: I²Ctraceproperties ............................................................................................................................ 36Table34: I²Csignaltype,topologyandlayoutguidelines .................................................................................. 36Table35: SPIsignaldefinition ............................................................................................................................ 37Table36: SPItraceproperties ............................................................................................................................ 37Table37: SPIsignaltype,topologyandlayoutguidelines ................................................................................. 37Table38: Audiosignaldefinition ....................................................................................................................... 38Table39: Audiotraceproperties ....................................................................................................................... 38Table40: Audiosignaltype,topologyandlayoutguidelines ............................................................................. 39Table41: SDsignaldefinition ............................................................................................................................. 41Table42: SDtraceproperties ............................................................................................................................ 42Table43: SDsignaltype,topologyandlayoutguidelines .................................................................................. 42
vii
Carrier Board Design Guide for VIA SOM-6X80 Module
1
1. IntroductionThisdocumentprovidesdesignguidelinesandrulerecommendationsforthedevelopersofacarrierboardthatsupportsthefeaturesoftheVIASOM-6X80module.Thisdocumentincludesthelayoutandroutingguidelinesforgeneralboarddesignsandmajorunderlyinginterfaces(e.g.HDMI,Ethernet,USB).Inaddition,thedocumentincludestheplacementandmechanicalinformationontheSOMDDR3SODIMMslotwhichisusedtoprovidehigh-speedinterfacesbetweenthecarrierboardandthemodule.
Pleasenotethatthisdocumentisconsideredtobeareferenceguideonly.Thisdocumentisnotintendedtobeaspecification.Allinformationandexampleslistedbelowareconsideredtobeaccurateasofthepublicationdate.However,developersmustbeawarethatthisdocumentisonlyareferenceguide.
1.1 Document OverviewAbriefdescriptionofeachchapterisgivenbelow.
Chapter 1: IntroductionThischapterbrieflyintroducesthestructureofthedesignguidedocument.
Chapter 2: General Carrier Board RecommendationsThegeneraldesignschemesandrecommendedlayoutrulesareshowninthischapter.
Chapter 3: VIA SOM-6X80 Module and SOM DDR3 SODIMM Slot Specification OverviewDetailedinformationabouttheVIASOM-6X80moduleandSOMDDR3SODIMMslotplacementanddimensions are described in this chapter.
Chapter 4: Layout and Routing RecommendationsDetailedlayoutandroutingguidelinesforeachmajorinterfacearedescribedinthischapter.
Carrier Board Design Guide for VIA SOM-6X80 Module
2
1.2 Acronyms Used
Table1:Acronyms used
Term DescriptionASIC Application-specificIntegratedCircuitDDR Double Data RateEMI ElectromagneticInterferenceESD Electrostatic-discharge
GPIO General Purpose Input/OutputHDMI High-DefinitionMultimediaInterface
I²C Inter-ICIC IntegratedCircuit
LCD Liquid-Crystal DisplayLVDS Low-VoltageDifferentialSignalingP2P Point-to-PointPCB Printed Circuit BoardRGB Red,GreenandBlue
RJ-45 RegisteredJack45RS-232 Recommend Standard number 232
SD SecureDigitalSODIMM Small Outline Dual In-line Memory Module
SMT SurfaceMountTechnology
SOM System-On-ModuleSPI Serial Peripheral Interface
UART UniversalAsynchronousReceiver-TransmitterUSB Universal Serial Bus
USB OTG USB On-The-Go
Carrier Board Design Guide for VIA SOM-6X80 Module
3
1.3 SchematicConventionsThereferenceschematicsdepictedinthisdocumentshowthedirectionalflowofthesignals.Directionalflowisindicated by the pointed ends of the arrow shapes.
Figure1:Schematicconventions
Bidireconal signal flow
IC/Connector
Input signal flow
Output signal flow
Carrier Board Design Guide for VIA SOM-6X80 Module
4
2. General Carrier Board RecommendationsThissectioncontainsgeneralguidelinesforthePCBstackupandthelayoutoftraces.Thegeneralguidelinesforroutingstyle,topology,andtraceattributerecommendationsarealsodiscussed.
2.1 PCB StackupThePCBstackupconsistsofsignallayersandreferencelayers(powerandground).Thesignallayersarereferredtoasthecomponentlayer(top),innerlayerandsolderlayer(bottom).
ThecarrierboarddesignerscanchoosebetweentwobasiccategoriesofPCBstackupdesign:microstripandstripline.Themicrostripdesignshavetheoutersignallayersexposed.Thestriplinedesignshavetheoutermostsignallayersshieldedbyreferencelayers.
Thefollowingfiguresshowanexampleofmicrostripandstriplinedesigns.
.
Figure2:Microstrip PCB stackup example
Figure3:Stripline PCB stackup example
Thechoiceofmicrostriporstriplinedesigndependsontheapplicationforwhichthecarrierboardisbeingdesigned.IfthecarrierboardisbeingdesignedforlocationswheresensitivitytoEMIisanissue,astriplinedesignisrecommendedforreducingEMIandnoisecoupling.ForapplicationswherethetoleranceforEMIlevelsisgreater,amicrostripdesignisrecommendedtoreducecosts.DuetotheinherentnatureofstriplinePCBstacks,broad-sidecouplingispossible.
Microstrip stackup design
Signal layers
Reference layers
Component layer
Ground layer
Inner layer
Power layer
Ground layer
Solder layer
Stripline stackup design
Signal layers
Reference layers
Component layer
Ground layer
Inner layer
Power layer
Ground layer
Solder layer
Carrier Board Design Guide for VIA SOM-6X80 Module
5
2.1.1 4-Layer PCB Stackup ExampleThefollowingfigureshowstherecommended4-layerPCBstackupdesignforthecarrierboardoftheVIASOM-6X80 module.
Figure4:4-Layer PCB board stackup detail
2.1.2 4-Layer PCB Impedance Control
Table2:4-Layer PCB impedance control
± 10%40Ω
Single-end50Ω
Single-end55Ω
Single-end85Ω
Differential90Ω
Differential90Ω
Differential
Layer 1 12mil 8mil 7mil7.8:9:7.8
mil7.6:8:7.6
mil7:7.5:7
mil
Layer 4 12mil 8mil 7mil7.8:9:7.8
mil7.6:8:7.6
mil7:7.5:7
mil
TOP = 1.0oz (1.46mil)
GROUND = 1.0oz (1.18mil)
POWER =1.0oz (1.18mil)
BOTTOM = 1.0 oz (1.46mil)
PP (Er) = 4.76 mil
Core (Er) = 44.88mil
PP (Er) = 4.76 mil
Soldermask = 0.79mil
Pla ng = 0.8mil
Soldermask = 0.79mil
Pla ng = 0.8mil
LAYER 1
LAYER 2
LAYER 3
LAYER 4
61.68mil
Copper foil + Plang
Copper foil
Copper foil
Copper foil + Plang
Carrier Board Design Guide for VIA SOM-6X80 Module
6
2.2 GeneralLayoutandRoutingGuidelinesThissectionprovidesgenerallayoutrulesandroutingguidelinesfordesigningcarrierboardsfortheVIASOM-6X80 module.
2.2.1 RoutingStylesandTopologyTopologyisthephysicalconnectivityofanetoragroupofnets.Therearetwotypesoftopologiesforacarrierboardlayout:point-to-point(P2P)andmulti-drop.AnexampleofthesetopologiesisshowninFigure5.
Figure5:Point-to-pointandmulti-dropexamples
High-speedbussignalsaresensitivetotransmissionlinestubs,whichcanresultinringingontherisingedgecausedbythehighimpedanceoftheoutputbufferinthehighstate.Inordertomaintainbettersignalquality,transmissionstubsshouldbekeptasshortaspossible(lessthan1.5”).Therefore,daisychainstyleroutingisstronglyrecommendedforthesesignals.Figure6belowshowsanexampleofdaisychainrouting.
Figure6:Daisy-chain example
Ifdaisychainroutingisnotallowedinsomecircumstances,differentroutingsmaybeconsidered.AnalternativetopologyisshowninFigure7.Inthiscase,thebranchpointissomewherebetweenbothends.Itmaybenearthesourceorneartheloads,butbeingclosetotheloadsideisbest.Theseparatedtracesshouldbeequalinlength.
Figure7:Alternatemulti-dropexample
Carrier Board Design Guide for VIA SOM-6X80 Module
7
2.2.2 GeneralTraceAttributeRecommendationA5miltracewidthand10milspacingaregenerallyadvisedformostsignaltracesonacarrierboardlayout.Toreduce trace inductance the minimum power trace width is recommended to be 30mil.
Asaquickreference,theoverallrecommendedtracewidthandspacingfordifferenttracetypesarelistedinTable3,andtherecommendedtracewidthandspacingforeachsignalgroupisshowninChapter4.
Table3:Recommendedtracewidthandspacing
Generalrulesforminimizingcrosstalkinhigh-speedbusdesignsarelistedbelow:
• Maximize the distance between traces. Maintain 10mil minimum spaces between traces wherever possible.
•Maximizethedistance(30milminimum)betweentwoadjacentroutingareasofdifferentsignalgroups wherever possible.
•Avoidparallelismbetweentracesonadjacentlayers.
•Providestablereferenceplanesforallhigh-speedsignals.
•Neverroutehigh-speedsignalsoversplitsintheirperspectivereferenceplanes.
•Selectaboardstack-upthatminimizescouplingbetweenadjacenttraces.
Figure8:Signaltracewidthandspacingexample
Figure9:Differentialsignaltracewidthandspacingexample
Notes:1.W:Tracewidth2.S:Thespacingtoothertraces3.S1:Differentialpairspacing
Trace Type Trace Width (mil) Spacing (mil)RegularSignal 5 or wider 10 or widerInterfaceorBusReferenceVoltageSignal 20 or wider 20 or widerPower 30 or wider 20 or wider
S1S S
Reference Plane
W W
Signal Signal
S
Reference Plane
WS
Signal
Carrier Board Design Guide for VIA SOM-6X80 Module
8
2.2.3 GeneralClockRoutingConsiderationsTheclockroutingguidelinesarelistedbelow:
• The recommended clock trace width is 5mil.
•Theminimumspacebetweenoneclocktraceandadjacentclocktracesis20mil.Theminimumspace fromonesegmentofaclocktracetoothersegmentsofthesameclocktraceisatleasttwotimesof theclockwidth.Thatis,morespaceisneededfromoneclocktracetoothersoritsowntracetoavoid signalcoupling(seeFigure10).
•Theclocktracesshouldbeparalleltotheirreferencegroundplanes.Thatis,aclocktraceshouldberight beneathorontopofitsreferencegroundplane(seeFigure11).
•Theseriesterminations(dampingresistors)areneededforallclocksignals(typically0Ωto47Ω).When twoloadsaredrivenbyoneclocksignal,theseriesterminationlayoutisshowninFigure12.When multipleloads(morethantwo)areapplied,aclockbuffersolutionispreferred.
•Isolatingclocksynthesizerpowerandgroundplanesthroughferritebeadsornarrowchannels(typically 20milto50milwide)ispreferred.
• No clock traces on the internal layer if a six-layer board is used.
Figure10:Suggestedclocktracespacing
Figure11:Clocktracelayoutinrelationtothegroundplane
Figure12:Seriesterminationformultipleclockloads
Carrier Board Design Guide for VIA SOM-6X80 Module
9
3. VIA SOM-6X80 Module and SOM DDR3 SODIMM Slot Specification Overview3.1 VIA SOM-6X80 Module Placement ThefollowingfigureshowsthedepictionofthetopviewofthecarrierboardPCB(SOMDB3)withtheappropriate amount of space reserved for the VIA SOM-6X80 module.
Figure13:VIA SOM-6X80 module placement example on the carrier board
3.2 VIASOM-6X80ModuleMechanicalCharacteristics
Figure14:CarrierboardwithVIASOM-6X80module(sideview)
Figure15:CarrierboardandVIASOM-6X80moduleheightdistribution(sideview)
SOMDB3
63mm
O 2mm 60mm
67.6mm
Carrier board
Carrier board
SOM DDR3 SODIMM slotVIA SOM-6X80 module
Standoff spacer
Screw
5.2mm1.8mm
66.5mm
3mm
1.3mm
Carrier Board Design Guide for VIA SOM-6X80 Module
10
3.3 VIA SOM-6X80 Module and Carrier Board DimensionsThefollowingfiguresshowthemechanicaldimensionsoftheVIASOM-6X80moduleandthereferencecarrierboard(SOMDB3).
Figure16:Dimensions of the VIA SOM-6X80 module
Figure17:Dimensions of the reference carrier board
SOMDB3
146mm
102mm
95.4mm44.7mmO 3.5mm
95.2mm
48.5mm 91.5mm 3mm3mm
3mm6.9mm
3.7mm
67.6mm
60mm
63mm
O 2mm
20mm
Carrier Board Design Guide for VIA SOM-6X80 Module
11
3.4 SOM DDR3 SODIMM SlotTheSOMDDR3SODIMMslotcanhandlehigh-speedsignalsandcomprises204pinstoconnecttheVIASOM-6X80module.Table4showsthespecificationsampleoftheSOMDDR3SODIMMslot.
Table4:SOM DDR3 SODIMM slot sample
3.4.1 SOM DDR3 SODIMM Slot Dimensions
Figure18:DimensionsoftheSOMDDR3SODIMMslot(topview)
Figure19:DimensionsoftheSOMDDR3SODIMMslot(sideview)
Part Number Description Height Vendor
AS0A626-H2R6-7HDDR3 SODIMM 10u"
GoldPlating5.2mmHConnector5.2mm Foxconn
63.7±0.5mm
71.30mm
25.8mm
6.2mm
1.3mm
69.60mm
68±0.15mm (Slot width)
1.65mm1.35mm
39mm 21mmPin # 1Pin # 203
1.35mm1.65mm
39mmPin # 204
21mmPin # 2
5.2mm
12mmmm0.50+0.10
-0.05
6mm (Max.)Between VIA SOM-6X80 module top surface and SMT surface
30°
VIA SOM-6X80 module
1.4mm (Min.)Between VIA SOM-6X80 module boom surface and SMT surface
Carrier Board Design Guide for VIA SOM-6X80 Module
12
3.4.2 SOM DDR3 SODIMM Slot Footprint
Figure20:PCB footprint of the SOM DDR3 SODIMM slot
Figure21:PCB footprint of the SOM DDR3 SODIMM slot with VIA SOM-6X80 module
Pin # 204
39mm
3mm
21mm
Pin # 2
0.60mm (Pitch)
4.10mm
4.10mm
Ø1.10±0.10mm (Hole)
Pin # 1
39mm
Pin # 203 3mm
21mm
0.35±0.03mm
Ø1.60±0.05mm (Hole)
2±0.03mm
4.60±0.10mm (2X)
3.50±0.10mm (2X)65.6mm
66.8mm1.75mm
0.60mm
12mm
Carrier board
Carrier Board Design Guide for VIA SOM-6X80 Module
13
3.5 SOMDDR3SODIMMSlotPinAssignmentsThe SOM DDR3 SODIMM slot consists of 204 pins. The pinouts of the SOM DDR3 SODIMM slot are shown below.
Pin Signal Pin Signal1 GND 2 GND3 SPK_OUT_R- 4 MICBIAS5 SPK_OUT_R+ 6 GND7 SPK_OUT_L- 8 LINPUT29 SPK_OUT_L+ 10 LINPUT3
11 HPOUTR 12 LINPUT113 OUT3 14 RINPUT215 HPOUTL 16 RINPUT117 GND 18 GND19 GND 20 GND21 GND 22 GND23 I2C0SCL 24 nUSBHB+25 I2C0SDA 26 nUSBHB-27 USBSW0 28 GND29 USBATTA0 30 nUSBHA+31 USBID0 32 nUSBHA-33 GND 34 GND35 GPIO2 36 nUSBHD0-37 M0_LINK 38 nUSBHD0+39 M0_SPEED 40 GND41 GPIO1 42 nUSB2+43 GPIO5 44 nUSB2-45 GPIO3 46 GND47 GND 48 VCC-BAT49 NET_RX+ 50 GND51 NET_RX- 52 SPI0MOSI53 GND 54 SPI0CLK55 NET_TX+ 56 SPI0MISO57 NET_TX- 58 SPI0SS0-59 GND 60 GND61 SUS_GPIO0 62 UART1RTS63 WAKEUP0 64 UART1CTS65 SUS_GPIO1 66 NC67 NC 68 NC69 GPIO4 70 NC71 WAKEUP3 72 GND73 WAKEUP2 74 GND75 GPIO0 76 LCD1CLK-77 GPIO6 78 LCD1CLK+
Pin Signal Pin Signal79 GND 80 GND81 UART1RXD 82 LCD1DO0-83 UART1TXD 84 LCD1DO0+85 GND 86 GND87 SPI1CLK 88 LCD1DO1-89 SPI1SS0- 90 LCD1DO1+91 SPI1MISO 92 GND93 SPI1MOSI 94 LCD1DO3+95 GND 96 LCD1DO3-97 NC 98 GND99 NC 100 LCD1DO2+
101 PWRENVCC 102 LCD1DO2-103 PWREN_MAIN 104 GND105 NC 106 PWMOUT1107 GPIO14 108 PWMOUT2109 GPIO10 110 PWMOUT3111 GPIO8 112 PWMOUT0113 RSMRST- 114 GPIO9115 PWRBTN- 116 GPIO7117 GND 118 GND119 UART0TXD 120 UARTB_485121 UART0RXD 122 UARTA_485123 GND 124 GND125 NC 126 UARTC_485127 SD0CD 128 UARTD_485129 SD0PWRSW 130 GND131 SD0DATA2 132 I2C1SDA133 GND 134 I2C1SCL135 SD0CLK 136 GPIO13137 SD0DATA3 138 GPIO12139 SD0DATA1 140 I2C2SDA141 SD0DATA0 142 I2C2SCL143 SD0CMD 144 GND145 SD0WP 146 C24MOUT147 GND 148 VCLK149 nHDMIDDCSDA 150 VVSYNC151 GND 152 VHSYNC153 nHDMIDDCSCL 154 VDIN7155 nHDMIHPD 156 VDIN5
Carrier Board Design Guide for VIA SOM-6X80 Module
14
Table5:SOM DDR3 SODIMM slot pinouts
Pin Signal Pin Signal157 nHDMICEC 158 VDIN6159 GND 160 VDIN4161 UARTD_RX 162 VDIN0163 UARTD_TX 164 VDIN2165 UARTD_CTS 166 VDIN3167 UARTD_RTS 168 VDIN1169 UARTC_CTS 170 GND171 UARTC_RTS 172 nHDMID2+173 UARTC_RX 174 nHDMID2-175 UARTC_TX 176 GND177 UARTB_CTS 178 nHDMID1+179 UARTB_RTS 180 nHDMID1-181 UARTB_RX 182 GND183 UARTB_TX 184 nHDMID0+185 UARTA_CTS 186 nHDMID0-187 UARTA_RTS 188 GND189 UARTA_RX 190 nHDMICLK-191 UARTA_TX 192 nHDMICLK+193 GND 194 GND195 GND 196 GND197 GND 198 GND199 5VIN 200 5VIN201 5VIN 202 5VIN203 5VIN 204 5VIN
Carrier Board Design Guide for VIA SOM-6X80 Module
15
Figure22:SOMDDR3SODIMMslotschematics
Carrier Board Design Guide for VIA SOM-6X80 Module
16
4. Layout and Routing RecommendationTheinformationpresentedinthischapterincludesthesignaldefinition,topology,layoutandroutingguidelinesforeachbusinterface,andreferenceschematicsexample.Theinformationprovidedisintendedfordesigningcarrier boards that are compliant with the VIA SOM-6X80 module.
4.1 HDMI InterfaceTheVIASOM-6X80modulefeaturesoneHDMIinterface.TheHDMIinterfaceusesfourcontrolsignals,onedifferentialclock,andthreedifferentialdatapairsignalsthatcarryvideoandaudiosignals.
4.1.1 HDMISignalDefinitionThefollowingtableprovidesthedefinitionoftheHDMIsignalsthatareimplementedintheSOMDDR3SODIMM slot.
Table6:HDMIsignaldefinition
Figure23:HDMIroutingtopology
Note:TheEMIfiltersandESDcomponentsmustbeplacedneartheHDMIport.
Signal Name Pin # I/O DescriptionnHDMID0+ 184
O HDMIdifferentialpairlineslane0nHDMID0- 186nHDMID1+ 178
O HDMIdifferentialpairlineslane1nHDMID1- 180
nHDMID2+ 172O HDMIdifferentialpairlineslane2
nHDMID2- 174nHDMICLK+ 192
O HDMIdifferentialpairclocklinesnHDMICLK- 190nHDMIDDCSCL 153 IO HDMI DDC SCLnHDMIDDCSDA 149 IO HDMI DDC SDAnHDMICEC 157 O HDMI consumer electronics connectornHDMIHPD 155 O HDMIhotplugdetect
L1L1
L1L1
L1
L1
L2
L2
SOM DDR3SODIMM Slot
HDMI port
EMI filter1 4
2 3
ESD
1 4
2 3
ESD
1 4
2 3
ESD
1 4
2 3
ESD
VIA SOM-6X80
Edge
fing
er
L2
L2
L2
L2
L2
L2
L2
L2
nHDMID0+
nHDMID0-
nHDMID2+
nHDMIDDCSCL
nHDMIDDCSDA
nHDMICLK-
nHDMICLK+
nHDMID2-
nHDMID1-
nHDMID1+
ESD
ESD
L2
L2nHDMIHPD
nHDMICEC
N-ChannelDigital FET
L1
L1Route Differenally
L1
L1Route Differenally
L1
L1Route Differenally
L1
L1Route Differenally
Carrier Board Design Guide for VIA SOM-6X80 Module
17
4.1.2 HDMILayoutandRoutingRecommendations•Tracelengthsshouldbekepttoaminimum.
•Eachtraceofdifferentialpairsshouldnothavemorethantwoviaholes.
•Eachdifferentialpairssignalshouldroutetoparalleltoeachotherwiththesametracelength.
•Differentialpairshouldbeallreferencedtoground.
•Routethedifferentialpairsonasinglelayeradjacenttoagroundplane.
•Thespacingbetweenthedifferentialpairsignalandothersignalsshouldbeatleastthreetimesthetrace width.
Figure24:HDMIdifferentialtracewidthandspacingexample
Figure25:HDMIsingle-endedtracewidthandspacingexample
Table7:HDMItraceproperties
HDMI SignalDifferenal Pair
S1S S
Reference Plane
W W
S
Reference Plane
WS
HDMI SignalSingle-ended
Signal Group Signal Name Trace Impedance
Trace & Spacing (mil)(S : W : S1 : W : S)
Pair to Pair Trace Mismatch
Spacing to Other Signal
Data
nHDMID0+
100Ω±15%(Differential)
15:5:7:5:15<5mil
(Differential)15mil
nHDMID0-nHDMID1+nHDMID1-nHDMID2+nHDMID2-
ClocknHDMICLK+ 100Ω±15%
(Differential)15:5:7:5:15 <5mil
(Differential) 15milnHDMICLK-
Control
nHDMIDDCSCL
50Ω±15%5:10(W:S)
6mil 10milnHDMIDDCSDAnHDMICECnHDMIHPD
Carrier Board Design Guide for VIA SOM-6X80 Module
18
Table8:HDMIlayoutguidelines
Table9:HDMIroutingtopologyandsignaltype
Signal Group Signal Name Routing LayerAccumulated Trace Length (L1+ L2 = LT)
Length Difference (mil)
To Clock In Group
Data
nHDMID0+
Top/Bottom LT < 3" <500 <1000
nHDMID0-nHDMID1+nHDMID1-nHDMID2+nHDMID2-
ClocknHDMICLK+
Top/Bottom LT < 3" <500 <1000nHDMICLK-
Control
nHDMIDDCSCL
Top/Bottom LT < 3" <500 <1000nHDMIDDCSDAnHDMICECnHDMIHPD
Signal Group Signal Name Reference Plane Routing Topology Signal Type
Data
nHDMID0+
Ground Point-to-Point DifferentialPairs
nHDMID0-nHDMID1+nHDMID1-nHDMID2+nHDMID2-
ClocknHDMICLK+
Ground Point-to-Point DifferentialPairsnHDMICLK-
Control
nHDMIDDCSCL
Ground Point-to-Point Single-endednHDMIDDCSDAnHDMICECnHDMIHPD
Carrier Board Design Guide for VIA SOM-6X80 Module
19
4.1.3 HDMIReferenceSchematics
Figure26:HDMI reference circuitry
Carrier Board Design Guide for VIA SOM-6X80 Module
20
4.2 Ethernet InterfaceTheVIASOM-6X80modulefeaturesoneEthernet(10/100Mbps)interface.TheEthernetinterfaceconsistsoftwodifferentialdatasignalsandtwocontrolsignalsforactivitylinkandspeedindicators.
4.2.1 EthernetSignalDefinitionThefollowingtableprovidesthedefinitionoftheEthernetsignalsthatareimplementedintheSOMDDR3SODIMM slot.
Table10: Ethernetsignaldefinition
Figure27:Ethernetroutingtopology
Note:ThemagneticmodulehastobeplacedascloseaspossibletotheRJ-45port.Thedistancemustbelessthan1".
Signal Name Pin # I/O DescriptionNET_TX+ 55
O EthernetdifferentialpairlinesTransmitNET_TX- 57NET_RX+ 49
O EthernetdifferentialpairlinesReceiveNET_RX- 51
M0_SPEED 39 O Ethernet controller 0 100Mbps speed indicatorM0_LINK 37 O Ethernet controller 0 100Mbps link indicator
SOM DDR3SODIMM Slot
RJ-45 port VIA SOM-6X80
Edge
fing
er
L1
L1
L1
L1
LT
LT
L2
L2
L2
L2
NET_TX+
NET_TX-
M0_SPEED
M0_LINK
NET_RX-
NET_RX+
Magnec module (Transformer)
Route Differenally
Route Differenally
Carrier Board Design Guide for VIA SOM-6X80 Module
21
4.2.2 EthernetLayoutandRoutingRecommendations•Routedifferentialpairsclosetogetherandawayfromothersignals.
•Routeanyothertraceparalleltooneofthedifferentialtrace.
•Keeptracelengthwithineachdifferentialpairequal.
•Keepproperimpedancebetweentwotraceswithinadifferentialpair.
•Eachtraceofdifferentialpairsshouldnothavemorethantwoviaholes.
•Thespacingbetweenthedifferentialpairsignalandothersignalsshouldbeatleastthreetimesthetrace width.
•Eachdifferentialpairofsignalsisrequiredtobeparalleltoeachotherwiththesametracelength (Tolerance±50mil)onthecomponent(top)layerandtobeparalleltoarespectivegroundplane. Thelengthdifferencebetweentheshortestandlongestpairsshouldbelessthan200mil.
•TheaccumulatedtracelengthofthedifferentialsignalspairbetweentheSOMDDR3SODIMMslotand magneticmoduleshouldbelessthan1".
•TheaccumulatedtracelengthofthedifferentialsignalspairbetweenthemagneticmoduleandRJ-45 connectorshouldbelessthan1".Isolategroundplaneandconnecttochassis.
•Keepeachdifferentialpaironthesameplane.
•Topreventanynoisefrominjectingintothedifferentialpairs,besuretokeepdigitalsignalsorother signalsawayfromthedifferentialsignals.
•TheexternalmagneticmoduleshouldbeplacedclosetotheRJ-45connectortolimitEMIemissions.
Figure28:Ethernetsingle-endedtracewidthandspacingexample
Figure29:Ethernetdifferentialtracewidthandspacingexample
.
S
Reference Plane
WS
Ethernet Signal Single-ended
Ethernet SignalDifferenal Pair
S1S S
Reference Plane
W W
Carrier Board Design Guide for VIA SOM-6X80 Module
22
Table11: Ethernettraceproperties
Table12: Ethernetlayoutguidelines
Table13: Ethernetreferenceplane,signaltypeandroutingtopology
4.2.3 EthernetReferenceSchematics
Figure30:Ethernet reference circuitry
Signal Group Signal Name Trace Impedance
Trace & Spacing (mil)(S : W : S1 : W : S)
Pair to Pair Trace Mismatch
Spacing to Other Signal
Data
NET_TX+
100Ω±15%(Differential)
10:10:5:10:10 50mil 10milNET_TX-NET_RX+NET_RX-
ControlM0_SPEED
55Ω±15% 5:10 - 10milM0_LINK
Signal Group Signal Name Routing LayerAccumulated Trace Length(L1+ L2 = LT)
Length Difference (mil)
To Clock
Data
NET_TX+
Top/Bottom LT < 3" <1500NET_TX-NET_RX+NET_RX-
ControlM0_SPEED
Top/Bottom LT < 3" <1500M0_LINK
Signal Group Signal Name Reference Plane Signal Type Routing Topology
Data
NET_TX+
Ground/Power DifferentialPairs Point-to-PointNET_TX-NET_RX+NET_RX-
ControlM0_SPEED
Ground/Power Single-ended Point-to-PointM0_LINK
Carrier Board Design Guide for VIA SOM-6X80 Module
23
4.3 USB InterfaceThe VIA SOM-6X80 module features three USB 2.0 interfaces. Two of the three USB interfaces can only be usedasahost.Theotherinterfacecanbeconfiguredtobeusedaseitherthehostorclient.TheUSBinterfacesignalsusethreebi-directionaldifferentialdatapairs.
4.3.1 USBSignalDefinitionThefollowingtableprovidesthedefinitionoftheUSBsignalsthatareimplementedintheSOMDDR3SODIMMslot.
Table14: USBsignaldefinition
Figure31:USBroutingtopology
Signal Name Pin # I/O DescriptionnUSBHD0+ 38
IOOTGUniversalSerialBusport0,data+
nUSBHD0- 36 OTGUniversalSerialBusport0,data-nUSBHA+ 30
IOUniversalSerialBusport1,data+
nUSBHA- 32 UniversalSerialBusport1,data-
nUSBHB+ 24IO
UniversalSerialBusport2,data+nUSBHB- 26 UniversalSerialBusport2,data-USBATTA0 29 I UniversalSerialBusdeviceattachdetectUSBID0 31 I Port ID pinUSBSW0 27 I Universal Serial Bus power control pin
L2
L2
L2
L2
L2
L2
L1L1
L1L1
L1L1
L1L1
L1L1
L1L1
SOM DDR3SODIMM Slot
USB port 1
EMI filter1 4
2 3
ESD
2 3
1 4
ESD
1 4
2 3
ESD
VIA SOM-6X80
Edge
fing
er
nUSBHA-
nUSBHA+
nUSBHD0-
USBID0
USBSW0
USBATTA0
nUSBHD0+
nUSBHB+
nUSBHB-USB port 2
USB port 3 (Micro USB)
USB Overcurrent Protector IC
R
R
VSUS
R
VCC
R
R
Carrier Board Design Guide for VIA SOM-6X80 Module
24
4.3.2 USBLayoutandRoutingRecommendations•Thedifferentialpairsignalsshouldbeallreferencedtoground.
•Eachtraceofdifferentialpairsshouldnothavemorethantwoviaholes.
•Differentialpairrouteinparallelandinequallength.
•TheamountofviasandcornersusedfortheUSBsignallayoutshouldbeminimized;thisistopreventtheoccurrenceofreflectionandimpedancechanges.
•EachpairofUSBdatalinesisrequiredtobeparalleltoeachotherwiththesametracelength,andnot parallelwithothersignalstominimizecrosstalk.
•Separatethesignaltracesintosimilargroupsandroutesimilarsignaltracestogether.Inaddition,itisrecommendedtohavedifferentialpairsroutedtogetheronthecarrierboard.
•Controltracesignalsimpedanceshouldmaintain55Ω±10%.
•FortheUSBtraces,donotroutethemunderoscillators,crystals,clocksynthesizers,magneticdevicesorIC’swhichcouldbeusingduplicateclocks.
TheroutingexamplefortwopairsofUSBdatabusesisshowninFigure32.
Figure32:USBdifferentialsignalroutingexample
Figure33:USBdifferentialtracewidthandspacingexample
SOM DDR3SODIMM Slot
nUSBHA+
nUSBHA-
nUSBHA-
nUSBHA+
Recommended
USB port
USB port
Not recommended
S1W W
USB Signal Differenal Pair
S S
Reference Plane
S1W W
S
Carrier Board Design Guide for VIA SOM-6X80 Module
25
Table15: USBtraceproperties
Table16: USBterminationoption,signaltypeandroutingtopology
Table17: USBlayoutguidelines
Signal Group Signal Name Trace Impedance
Trace & Spacing (mil)(S : W : S1 : W : S)
Pair to Pair Trace Mismatch
Spacing to Other Signal
Data
nUSBHA+
90Ω±15% 20:7:7.5:7:20 100mil 20mil
nUSBHA-nUSBHB+nUSBHB-nUSBHD0+nUSBHD0-
ControlUSBATTA0
55Ω±10% 5:10 - 10milUSBID0USBSW0
Signal Group Signal Name Termination Option Signal Type Topology
Data
Port 1nUSBHA+
90Ω DifferentialDataPairs Point-to-Point
nUSBHA-
Port 2nUSBHB+nUSBHB-
Port 3nUSBHD0+nUSBHD0-
ControlUSBATTA0
60Ω - Point-to-PointUSBID0USBSW0
Signal Group Signal Name Routing LayerLength Difference
(In Pair)
Accumulated Trace Length(L1+ L2 = LT)
Data
Port 1nUSBHA+
Top/Bottom <100mil LT < 12"
nUSBHA-
Port 2nUSBHB+nUSBHB-
Port 3nUSBHD0+nUSBHD0-
ControlUSBATTA0
Top/Bottom - LT < 12"USBID0USBSW0
Carrier Board Design Guide for VIA SOM-6X80 Module
26
4.3.3 USBReferenceSchematics
Figure34:USB host reference circuitry
TheUSBportmodecanbecontrolledbythesignalUSBID0.Inthereferencecircuitryexamplebelow,theUSBID0signalisreferencedtogroundthatmakestheUSBportmodeasclientUSB(orUSBOTGport).
Figure35:USB client reference circuitry
Carrier Board Design Guide for VIA SOM-6X80 Module
27
4.4 COM and UART InterfaceTheVIASOM-6X80modulefeaturesCOMandUARTinterfacesthatenabletheinterfacingoffourCOMortwoUARTonthecarrierboard.ThefourCOMinterfacesareusedforRS-232serialcommunicationsandthetwoUARTcanbeusedforTX/RX,RTS,CTSanddebuggingTX/RX.
4.4.1 COMandUARTSignalDefinitionThefollowingtableprovidesthedefinitionoftheCOMandUARTsignalsthatareimplementedintheSOMDDR3 SODIMM slot.
Table18: COMandUARTsignaldefinition
Signal Name Pin # I/O DescriptionUARTA_TX 191 O UART Port-A transmit dataUARTA_RX 189 I UART Port-A receive dataUARTA_RTS 187 O UART Port-A request to sendUARTA_CTS 185 I UART Port-A clear to send
UARTB_TX 183 O UART Port-B transmit dataUARTB_RX 181 I UART Port-B receive dataUARTB_RTS 179 O UART Port-B request to sendUARTB_CTS 177 I UART Port-B clear to sendUARTC_TX 175 O UART Port-C transmit dataUARTC_RX 173 I UART Port-C receive dataUARTC_RTS 171 O UART Port-C request to sendUARTC_CTS 169 I UART Port-C clear to sendUARTD_TX 163 O UART Port-D transmit dataUARTD_RX 161 I UART Port-D receive dataUARTD_RTS 167 O UART Port-D request to sendUARTD_CTS 165 I UART Port-D clear to sendUART1TXD 83 O UART Port-1 transmit dataUART1RXD 81 I UART Port-1 receive dataUART0TXD 119 O UART Port-0 transmit dataUART0RXD 121 I UART Port-0 receive data
Carrier Board Design Guide for VIA SOM-6X80 Module
28
Figure36:COMandUARTroutingtopology
4.4.2 COMandUARTLayoutandRoutingRecommendations•Thetransmitandreceivedatatracesignalsshouldberoutedinparallelandinequallength.
•TheamountofviasandcornersusedfortheCOMandUARTsignallayoutshouldbeminimized;thisisto preventtheoccurrenceofreflectionandimpedancechanges.
•Controltracesignalsimpedanceshouldmaintain55Ω±10%.
Table19: COMandUARTtraceproperties
L4L3L2L1
L4L3L2L1
L4L3L2L1
L4L3L2L1
ESD
L2
L2COM port 1
L4
L4
L3
L3
L1
L1
L4L3L2L1
L2
L2COM port 2
L4
L4
L3
L3
L1
L1
ESD UARTpin header 1
ESD
L2
L2COM port 3
L4
L4
L3
L3
L1
L1
L2
L2COM port 4
L4
L4
L3
L3
L1
L1
ESD UARTpin header 2
SOM DDR3SODIMM Slot
VIA SOM-6X80
Edge
fing
er
UARTA_TX
UARTA_RTS
UARTA_RX
UARTA_CTS
UARTB_TX
UARTB_RTS
UARTB_RX
UARTB_CTS
UARTD_TX
UARTD_RTS
UARTD_RX
UARTD_CTS
UARTC_TX
UARTC_RTS
UARTC_RX
UARTC_CTS
L4L3L2L1
L4L3L2L1
L4L3L2L1
Tranceiver IC
Tranceiver IC
Tranceiver IC
Tranceiver IC
Signal Group Signal NameTrace (mil)
(Width:Spacing)Trace Impedance Spacing in Other Group
Data
UART[D:A]_TX
5:5 55Ω±10% 5milUART[D:A]_RXUART[1:0]TXDUART[1:0]RXD
ControlUART[D:A]_CTS
5:5 55Ω±10% 5milUART[D:A]_RTS
Carrier Board Design Guide for VIA SOM-6X80 Module
29
Table20: COMandUARTtopology,signaltypeandlayoutguidelines
4.4.3 COMandUARTReferenceSchematics
Figure37:COM and UART reference circuitry
Signal Group Signal Name Signal Type Topology Reference Plane
Accumulated Trace Length
(L1 + L2 + L3 + L4 = LT)
Data
UART[D:A]_TX
Single-ended Point-to-Point Ground/Power <10"UART[D:A]_RXUART[1:0]TXDUART[1:0]RXD
ControlUART[D:A]_CTS
Single-ended Point-to-Point Ground/Power <10"UART[D:A]_RTS
Carrier Board Design Guide for VIA SOM-6X80 Module
30
4.5 LCD InterfaceTheVIASOM-6X80modulefeaturesoneLCDinterface.TheLCDinterfaceisaparallelbussignalprovidedforinterfacingtheLCDconnectorforLVDSLCDdisplayasthemaindisplayinterface.TheLCDinterfaceisasingle-channel that supports 18-bit and 24-bit interfaces.
4.5.1 LCDSignalDefinitionThefollowingtableprovidesthedefinitionoftheLCDsignalsthatareimplementedintheSOMDDR3SODIMMslot.
Table21: LCDsignaldefinition
Figure38:LCDroutingtopology
Signal Name Pin # I/O DescriptionLCD1DO0- 82
O LCDdifferentialpairdata0signalsLCD1DO0+ 84
LCD1DO1- 88O LCDdifferentialpairdata1signals
LCD1DO1+ 90
LCD1DO2- 102O LCDdifferentialpairdata2signals
LCD1DO2+ 100LCD1DO3- 96
O LCDdifferentialpairdata3signalsLCD1DO3+ 94LCD1CLK- 76
O LCDdifferentialpairclocklinesLCD1CLK+ 78
SOM DDR3SODIMM Slot EMI filter
VIA SOM-6X80
Edge
fing
er
L2
L2L1L1
L1L12 3
1 4
LCD1DO0-
LCD1DO0+
L2
L2L1L1
L1L12 3
1 4
LCD1DO1-
LCD1DO1+
L2
L2L1L1
L1L12 3
1 4
LCD1DO2-
LCD1DO2+
L2
L2L1L1
L1L12 3
1 4
LCD1DO3-
LCD1DO3+
L2
L2L1L1
L1L12 3
1 4
LCD1CLK-
LCD1CLK+
LCD panelconnector LCD panel
Carrier Board Design Guide for VIA SOM-6X80 Module
31
4.5.2 LCDLayoutandRoutingRecommendations•LCDdatasignaltracesshouldbedesignedtobeasshortaspossible.
•InordertomaximizethenoiserejectioncharacteristicsoftheLCDvideooutputs,itisthen recommendedtoroutetheLCDvideooutputsonthetoplayeroverasolidgroundplane.
•TheroutingfortheLCDsignalsshouldbeassimilaraspossible(i.e.,sameroutinglayer,samenumber ofvias,sameroutinglengthandsamebends).
•RoutetheLCDdatatracesignalsasadifferentialsignalwithatraceimpedanceof100Ω.
Table22: LCDtraceproperties
Table23: LCDsignaltype,topologyandreferenceplane
Signal Group Signal Name Trace Impedance
Trace & Spacing (mil) (S : W : S1 : W : S)
Pair to Pair Trace Mismatch
Spacing to Other Signal
Data
LCD1DO0-
100Ω±15%(Differential)
15:5:7:5:15<5mil
(Differential)15mil
LCD1DO0+LCD1DO1-LCD1DO1+LCD1DO2-
LCD1DO2+LCD1DO3-LCD1DO3+
ClockLCD1CLK- 100Ω±15%
(Differential)15:5:7:5:15 <5mil
(Differential) 15milLCD1CLK+
Signal Group Signal Name Signal Type Topology Reference Plane
Data
LCD1DO0-
Differentialpairs Point-to-Point Ground
LCD1DO0+LCD1DO1-LCD1DO1+LCD1DO2-
LCD1DO2+LCD1DO3-LCD1DO3+
ClockLCD1CLK-
Differentialpairs Point-to-Point GroundLCD1CLK+
Carrier Board Design Guide for VIA SOM-6X80 Module
32
Table24: LCDlayoutguidelines
4.5.3 LCDReferenceSchematics
Figure39:LCD reference circuitry
Signal Group Signal Name Routing LayerLength Difference (mil) Accumulated
Trace Length (LT)To Clock In Group
Data
LCD1DO0-
Top/Bottom <500 <1000Route to Minimum
(or<6")
LCD1DO0+LCD1DO1-LCD1DO1+LCD1DO2-LCD1DO2+LCD1DO3-LCD1DO3+
ClockLCD1CLK-
Top/Bottom - - -LCD1CLK+
Carrier Board Design Guide for VIA SOM-6X80 Module
33
4.6 Touch Panel InterfaceTheVIASOM-6X80modulefeaturesatouchpanelinterfaceforcapacitivetouchscreens.Itallowstheintegrationofthetouchscreensolutiononthecarrierboard.ThetouchpanelinterfaceisaninterfaceconnectionbetweentheSOMDDR3SODIMMslotandtouchpanelconnector.Thetouchpanelinterfacesupports4-wireand5-wirecapacitivetouchscreens.
4.6.1 TouchPanelSignalDefinitionThefollowingtableprovidesthedefinitionofthetouchpanelsignals.
Table25: Touchpanelsignaldefinition
Figure40:Touchpanelroutingtopology
4.6.2 TouchPanelLayoutandRoutingRecommendations•Keeptracelengthsasshortaspossible.
• It is recommended to route the traces on the top layer.
•Theamountofviasandcornersusedforthetouchpanelsignallayoutshouldbeminimized.
Table26: Touchpaneltraceproperties
Table27: Touchpanelsignaltype,routingtopologyandreferenceplane
From SOM DDR3 SODIMM Slot to Capacitive Touch Sensor ControllerSignal Name Pin # I/O Description
GPIO4 69 O TPresetsignalGPIO5 43 O TPinterruptsignal
I2C0SDA 25 O TP I²C DataI2C0SCL 23 O TP I²C Clock
RRS
SOM DDR3SODIMM Slot
VIA SOM-6X80
Edge
fing
er
GPIO4
GPIO5
I2C0SCL
I2C0SDA
TP_RESET
TP_INT
TP_SCL
TP_SDA
L1
L1
L1
L1
Touch Panel Connector
CapaciveTouch screen
Interface Signal Name Trace Impedance
Trace (mil)(Width : Spacing)
Trace Mismatch
Spacing to Other Signal
SOM DDR3 SODIMM slot to Touch panel connector
GPIO4
55Ω±10% 5:5 20mil 5milGPIO5I2C0SCLI2C0SDA
Interface Signal Name Signal Type Topology Reference Plane
SOM DDR3 SODIMM slot to Touch panel connector
GPIO4
Single-ended Point-to-Point Ground/PowerGPIO5I2C0SCLI2C0SDA
Carrier Board Design Guide for VIA SOM-6X80 Module
34
Table28: Touchpanellayoutguidelines
4.6.3 TouchPanelReferenceSchematics
Figure41:Touch panel reference circuitry
Interface Signal Name Routing Layer Length Difference (mil)
Accumulated Trace Length (L1 + L2 = LT)
SOM DDR3 SODIMM slot to Touch panel connector
GPIO4
Top/Bottom - 2"GPIO5I2C0SCLI2C0SDA
Carrier Board Design Guide for VIA SOM-6X80 Module
35
4.7 GPIO InterfaceTheVIASOM-6X80modulefeaturesaGeneralPurposeInputandOutput(GPIO)interface.
4.7.1 GPIOSignalDefinitionThefollowingtableprovidesthedefinitionoftheGPIOsignalsthatareimplementedintheSOMDDR3SODIMM slot.
Table29: GPIOsignaldefinition
4.7.2 GPIOLayoutandRoutingRecommendation
Table30: GPIOtraceproperties
Table31: GPIOsignaltype,topologyandlayoutguidelines
Signal Name Pin # I/O DescriptionGPIO0 75 IO
General Purpose GPIO
GPIO1 41 IOGPIO2 35 IOGPIO3 45 IOGPIO4 69 IOGPIO5 43 IOGPIO6 77 IOGPIO7 116 IOGPIO8 111 IOSUS_GPIO0 61 IO
General Purpose GPIO for Suspend Power DomainSUS_GPIO1 65 IO
Signal Group Signal Name Trace ImpedanceTrace (mil)
(Width : Spacing)Spacing to
Other Signal
Data
GPIO[7:0]55Ω 5:5 5mil
GPIO8SUS_GPIO0
55Ω 5:5 5milSUS_GPIO1
Signal Group Signal Name Signal Type Topology Reference Plane Accumulated Trace Length
Data
GPIO[7:0]Single-ended Point-to-Point Ground/Power 12"
GPIO8SUS_GPIO0
Single-ended Point-to-Point Ground/Power 12"SUS_GPIO1
Carrier Board Design Guide for VIA SOM-6X80 Module
36
4.8 I²C InterfaceThe VIA SOM-6X80 module features an I²C interface that can support up to three I²C devices.
4.8.1 I²CSignalDefinitionThefollowingtableprovidesthedefinitionoftheI²CsignalsthatareimplementedintheSOMDDR3SODIMMslot.
Table32: I²Csignaldefinition
4.8.2 I²CLayoutandRoutingRecommendation
Table33: I²Ctraceproperties
Table34: I²Csignaltype,topologyandlayoutguidelines
Signal Name Pin # I/O DescriptionI2C0SDA 25 IO I²C0 serial dataI2C0SCL 23 IO I²C0 serial clockI2C1SDA 132 IO I²C1 serial data
I2C1SCL 134 IO I²C1 serial clockI2C2SDA 140 IO I²C2 serial dataI2C2SCL 142 IO I²C2 serial clock
Signal Group Signal Name Trace ImpedanceTrace (mil)
(Width : Spacing)Spacing to
Other SignalData I2C[2:0]SDA 55Ω 5:5 5milClock I2C[2:0]SCL 55Ω 5:5 5mil
Signal Group Signal Name Signal Type Topology Reference Plane Accumulated Trace Length
Data I2C[2:0]SDA Single-ended Daisy chain Ground/Power <12"Clock I2C[2:0]SCL Single-ended Daisy chain Ground/Power <12"
Carrier Board Design Guide for VIA SOM-6X80 Module
37
4.9 SPI InterfaceThe VIA SOM-6X80 module features two SPI interfaces. Each SPI interface can support one master and one slave.
4.9.1 SPISignalDefinitionThefollowingtableprovidesthedefinitionoftheSPIsignalsthatareimplementedintheSOMDDR3SODIMMslot.
Table35: SPIsignaldefinition
4.9.2 SPILayoutandRoutingRecommendation
Table36: SPItraceproperties
Table37: SPIsignaltype,topologyandlayoutguidelines
Signal Name Pin # I/O DescriptionSPI0MISO 56 I MasterInput0,SlaveOutput0SPI0MOSI 52 O MasterOutput0,SlaveInput0SPI0CLK 54 O Serial Clock 0
SPI0SS0- 58 O Slave Select 0SPI1MOSI 93 O MasterOutput1,SlaveInput1SPI1MISO 91 I MasterInput1,SlaveOutput1SPI1CLK 87 O Serial Clock 1SPI1SS0- 89 O Slave Select 1
Signal Group Signal Name Trace ImpedanceTrace (mil)
(Width : Spacing)Spacing to
Other Signal
DataSPI[1:0]MISO
55Ω 5:5 5milSPI[1:0]MOSISPI[1:0]SS0-
Clock SPI[1:0]CLK 55Ω 5:10 5mil
Signal Group Signal Name Signal Type Topology Reference Plane Accumulated Trace Length
DataSPI[1:0]MISO
Single-ended Daisy chain Ground/Power <10"SPI[1:0]MOSISPI[1:0]SS0-
Clock SPI[1:0]CLK Single-ended Rs=22Ω Ground/Power <10"
Carrier Board Design Guide for VIA SOM-6X80 Module
38
4.10 Audio InterfaceTheVIASOM-6X80modulefeaturesanaudiointerfaceforaudioconnectorssuchastwoline-in,headphone,monospeakerout,rightandleftchannelspeakerout,andmicrophone.
4.10.1 AudioSignalDefinitionThefollowingtableprovidesthedefinitionoftheaudiosignalsthatareimplementedintheSOMDDR3SODIMM slot.
Table38: Audiosignaldefinition
4.10.2 AudioLayoutandRoutingRecommendations•Routetheanaloganddigitaltracesignalsasfaraspossiblefromeachothertopreventnoise.
•Routetheclocktraceawayfromanyanaloginputandvoltagereferencepins.
•Isolatethecodecorputawayfromanymajorcurrentpathorgroundbounce.
•Fillwithcoppertheregionsbetweentheanalogtracesandattachedittotheanalogground.
•Fillwithcoppertheregionsbetweenthedigitaltracesandattachedittothedigitalground.
•Keeptracelengthsasshortaspossible.
Table39: Audiotraceproperties
Signal Name Pin # I/O DescriptionHPOUTR 11 O HeadphonerightchanneloutputHPOUTL 15 O HeadphoneleftchanneloutputOUT3 13 O Audio mono output
LINPUT1 12 I Leftchannelsingle-endedMicinput/LeftchannelnegativedifferentialMicinput
LINPUT2 8 I Leftchannellineinput/LeftchannelpositivedifferentialMicinput
LINPUT3 10 I Leftchannellineinput/LeftchannelpositivedifferentialMicinput/Jack detect input pin
RINPUT1 16 I Rightchannelsingle-endedMicinput/RightchannelnegativedifferentialMicinput
RINPUT2 14 I Rightchannellineinput/RightchannelpositivedifferentialMic input
SPK_OUT_R+ 5 O RightspeakerpositiveoutputSPK_OUT_R- 3 O RightspeakernegativeoutputSPK_OUT_L+ 9 O LeftspeakerpositiveoutputSPK_OUT_L- 7 O Leftspeakernegativeoutput
Signal Name Trace ImpedanceTrace (mil)
(Width : Spacing)Spacing to
Other SignalHPOUTR
55Ω±10% 8:5 5milHPOUTLOUT3 55Ω±10% 8:5 5milLINPUT[3:1]
55Ω±10% 8:5 5milRINPUT[2:1]SPK_OUT_R[+/-]
55Ω±10% 8:5 5milSPK_OUT_L[+/-]
Carrier Board Design Guide for VIA SOM-6X80 Module
39
Table40: Audiosignaltype,topologyandlayoutguidelines
4.10.3 AudioInterfaceReferenceSchematics
Figure42:Line-in1&2referencecircuitry
Figure43:Headphone reference circuitry
Figure44:Mono speaker out reference circuitry
Signal Name Signal Type Topology Reference Plane Accumulated Trace Length
HPOUTRSingle-ended Point-to-Point Ground <10"
HPOUTLOUT3 Single-ended Point-to-Point Ground <10"LINPUT[3:1]
Single-ended Point-to-Point Ground <10"RINPUT[2:1]SPK_OUT_R[+/-]
Single-ended Point-to-Point Ground <10"SPK_OUT_L[+/-]
Carrier Board Design Guide for VIA SOM-6X80 Module
40
Figure45:Rightchannelspeakeroutreferencecircuitry
Figure46:Leftchannelspeakeroutreferencecircuitry
Figure47:Onboard microphone reference circuitry
Carrier Board Design Guide for VIA SOM-6X80 Module
41
4.11 SD InterfaceTheVIASOM-6X80modulefeaturesanSDinterfaceforSDstorage.
4.11.1 SDSignalDefinitionThefollowingtableprovidesthedefinitionoftheSDsignalsthatareimplementedintheSOMDDR3SODIMMslot.
Table41: SDsignaldefinition
Figure48:SDroutingtopology
4.11.2 SDLayoutandRoutingRecommendations•SignaltracesshouldbeaboveasolidandcontinuousgroundplanealongthepathfromSOMDDR3 SODIMM slot to SD slot.
•SD0CMDtracesignalmusthavepull-upresistorof4.7KΩ.
•SD0WPtracesignalmusthavepull-downresistorof1KΩtotheground.
•TheESDprotectionoftracesignalSD0PWRSWmustbeplacedneartheSDslot.
Signal Name Pin # I/O DescriptionSD0DATA0 141 IO Datasignal0,usedforSDinterfaceSD0DATA1 139 IO Datasignal1,usedforSDinterfaceSD0DATA2 131 IO Datasignal2,usedforSDinterfaceSD0DATA3 137 IO Datasignal3,usedforSDinterfaceSD0CMD 143 IO Commandsignal,addexternalpull-upresistorSD0CLK 135 O SD0 bus clockSD0CD 127 I SD0 CommandSD0PWRSW 129 O SD0 Power switchSD0WP 145 I SD0 write protect
L2L1
L2L1
L2L1
L1 L2
L1 L2
ESD
R
VCC33_SD0
R
SD slot
ESD SOM DDR3SODIMM Slot
SD0DATA[3:0]
SD0CMD
SD0CD
SD0PWRSW
SD0WP
SD0CLK VIA SOM-6X80
Edge
fing
er
Carrier Board Design Guide for VIA SOM-6X80 Module
42
Table42: SDtraceproperties
Table43: SDsignaltype,topologyandlayoutguidelines
4.11.3 SDInterfaceReferenceSchematics
Figure49:SD reference circuitry
Signal Group Signal Name Signal Type Topology Reference PlaneAccumulated Trace Length(L1 + L2 = LT)
Data SD0DATA[3:0] Single-ended Point-to-Point Ground/Power <8"
Control
SD0CMD
Single-ended Point-to-Point Ground/Power <8"SD0CDSD0WPSD0PWRSW
Clock SD0CLK Single-ended Point-to-Point Ground/Power <8"
Signal Group Signal Name Trace ImpedanceTrace (mil)
(Width : Spacing)Spacing to
Other SignalData SD0DATA[3:0] 55Ω±15% 5:5 5mil
Control
SD0CMD
55Ω±15% 5:5 5milSD0CDSD0WPSD0PWRSW
Clock SD0CLK 55Ω±15% 5:15 15mil
1F, 531 Zhong-zheng Road,Xindian Dist., New Taipei City 231Taiwan
Tel: 886-2-2218-5452Fax: 886-2-2218-9860Email: [email protected]
940 Mission CourtFremont, CA 94539,USA
Tel: 1-510-687-4688Fax: 1-510-687-4654Email: [email protected]
Email: [email protected]
Taiwan Headquarters USA
Europe
Tsinghua Science Park Bldg. 7No. 1 Zongguancun East Road,Haidian Dist., Beijing, 100084China
Tel: 86-10-59852288Fax: 86-10-59852299Email: [email protected]
3-15-7 Ebisu MT Bldg. 6F,Higashi, Shibuya-kuTokyo 150-0011Japan
Tel: 81-3-5466-1637Fax: 81-3-5466-1638Email: [email protected]
ChinaJapan