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NI sbRIO-9651System on ModuleCarrier Board Design Guide

NI sbRIO-9651 System on Module Carrier Board Design Guide

March 2017376960C-01

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© National Instruments | v

Contents

About This DocumentTerminology ..................................................................................................................... ixSchematic Conventions .................................................................................................... xAdditional Documentation Resources .............................................................................. xi

Chapter 1Fixed Behavior SignalsPrimary Ethernet (GBE0) ................................................................................................. 1-1

GBE0 Signal Definitions .......................................................................................... 1-2GBE0 Implementation on the Reference Carrier Board........................................... 1-3Gigabit Ethernet Magnetic Requirements ................................................................ 1-4GBE0 Routing Considerations ................................................................................. 1-4

USB (USB0, USB1) ......................................................................................................... 1-5USB0 Host/Device Signal Definitions ..................................................................... 1-5USB0 Device Implementation on the Reference Carrier Board............................... 1-6USB1 Host Signal Definitions.................................................................................. 1-7USB1 Host Implementation on the Reference Carrier Board .................................. 1-8Supporting Onboard USB Devices........................................................................... 1-10USB Routing Considerations.................................................................................... 1-10

UART/Console Out (Serial1) ........................................................................................... 1-10Serial1 Signal Definitions......................................................................................... 1-10Serial1 Implementation on the Reference Carrier Board ......................................... 1-11Adding Flow Control and Modem Control Signals.................................................. 1-12

SD Card ............................................................................................................................ 1-12SD Signal Definitions............................................................................................... 1-13SD Implementation on the Reference Carrier Board................................................ 1-14SD Routing Considerations ...................................................................................... 1-16

RTC Battery (VBAT) ....................................................................................................... 1-16VBAT Signal Definitions ......................................................................................... 1-17VBAT Implementation on the Reference Carrier Board.......................................... 1-17Eliminating the Effects of Contact Bounce .............................................................. 1-17

Resets................................................................................................................................ 1-18Reset Signal Definitions ........................................................................................... 1-18Reset Implementation on the Reference Carrier Board............................................ 1-19

Status LED........................................................................................................................ 1-20Status LED Signal Definitions ................................................................................. 1-20Status LED Implementation on the Reference Carrier Board .................................. 1-20

FPGA Config.................................................................................................................... 1-21FPGA Config Signal Definitions.............................................................................. 1-21FPGA Config Implementation on the Reference Carrier Board .............................. 1-21

Temp Alert........................................................................................................................ 1-22Temp Alert Signal Definitions ................................................................................. 1-22Temp Alert Implementation on the Reference Carrier Board .................................. 1-22

Contents

vi | ni.com

Chapter 2User-Defined FPGA SignalsSecondary Ethernet (GBE1) .............................................................................................2-1

GBE1 Signal Definitions on the Reference Carrier Board .......................................2-2GBE1 Reference Schematic......................................................................................2-4GBE1 Routing Considerations..................................................................................2-8

Additional RS-232 (Serial2, Serial3, Serial4) ..................................................................2-9Serial2 Signal Definitions on the Reference Carrier Board......................................2-9Serial2 Reference Schematic ....................................................................................2-10

RS-485 (Serial5, Serial6) ..................................................................................................2-11Serial5 Definitions on the Reference Carrier Board .................................................2-12Serial5 Reference Schematic ....................................................................................2-13RS-485 Layout Considerations .................................................................................2-14

CAN (CAN0, CAN1) .......................................................................................................2-14CAN0 Signal Definitions on the Reference Carrier Board.......................................2-15CAN0 Reference Schematic .....................................................................................2-16Termination Resistors for CAN Cables ....................................................................2-18

Chapter 3Carrier Board PCB Layout GuidelinesImpedance-Controlled Signaling ......................................................................................3-1Single-Ended Signal Best Practices ..................................................................................3-2Differential Signal Best Practices .....................................................................................3-2Ground and Power Plane Recommendations....................................................................3-3Fanout and Layout Options...............................................................................................3-3

Chapter 4Mechanical ConsiderationsMounting...........................................................................................................................4-1

Selecting an Appropriate Mating Connector ............................................................4-1Selecting Appropriate Standoffs ...............................................................................4-2Mounting Direction Options.....................................................................................4-4

Managing Thermal Conditions .........................................................................................4-6Designing a Suitable Enclosure ................................................................................4-6Understanding Thermal Specifications.....................................................................4-7

Validating the System.......................................................................................................4-8Validating Temperature Measurements....................................................................4-8Managing Power and Feature Utilization .................................................................4-10Mounting Recommendations for Maximizing Thermal Performance......................4-11Additional Resources for Managing Thermal Conditions ........................................4-12

Shock and Vibration .........................................................................................................4-12


© National Instruments | vii

Appendix AReference Carrier Board Specifications and User GuideParts Locator Diagram and Block Diagram ..................................................................... A-1Specifications.................................................................................................................... A-1

Ethernet..................................................................................................................... A-2Serial ......................................................................................................................... A-2CAN.......................................................................................................................... A-2SD Card .................................................................................................................... A-2USB .......................................................................................................................... A-2Pmod......................................................................................................................... A-2RTC Battery.............................................................................................................. A-4Support Signals......................................................................................................... A-4

Connector Pinouts............................................................................................................. A-4RS-232, RS-485, and CAN Connector Pinouts ........................................................ A-4Pmod 12-Pin Connector Pinout ................................................................................ A-5Pmod I2C Connector Pinout ..................................................................................... A-6

Environmental Management............................................................................................. A-6

Appendix BRevision History

Appendix CNI Services

© National Instruments | ix

About This Document

The NI sbRIO-9651 System on Module (SOM) provides an embedded real-time processor and reconfigurable FPGA. The sbRIO-9651 SOM requires a user-designed carrier board to provide power and I/O interfaces. You can optimize the carrier board to implement the exact functions your application requires. You can design the carrier board size and connector locations to fit the packaging or enclosure of your specific system.

This document provides detailed information about carrier board design techniques, guidelines, and requirements.

Note Refer to the documents listed in the Additional Documentation Resources section of this chapter for more information as you design, prototype, and implement your sbRIO-9651 SOM application. In particular, refer to the NI sbRIO-9651 System on Module OEM Device Specifications for dimensions, pinout information, functional specifications, and electrical specifications for the sbRIO-9651 SOM.

TerminologyTable 1 defines terms used in this document to describe sbRIO-9651 SOM concepts and technology.

Table 1. sbRIO-9651 SOM Terminology in This Document

Term Definition

System Components

J1 Molex 45971-4185 320-pin, 8 × 40 position, SEARAY open-pin-field-array connector on the sbRIO-9651 SOM.

SEARAY Connector family used for the J1 connector on the sbRIO-9651 SOM. Manufactured by Samtec and Molex.

SOM System on Module.

SoC System on Chip.

USB Device Physical, electrical, addressable, and logical entity that is attached to USB and performs a function.

USB Device port Port on a carrier board that provides a USB Device interface to the SOM.

USB Host USB interface that controls the bus and communicates with connected USB devices.

USB Host port Port on a carrier board that provides a USB Host interface from the SOM.

About This Document

x | ni.com

Schematic ConventionsTable 2 describes symbol conventions used in the I/O interface schematic diagrams in this document.

Reference Schematic and Signal Naming

LVTTL In compliance with the Low-Voltage Transistor-Transistor Logic (LVTTL) specification.

LVCMOS In compliance with the Low-Voltage Complementary Metal Oxide Semiconductor (LVCMOS) specification.

PUDC Pull-up During Configuration

Mechanical

CPU/FPGA temperature

The temperature reported digitally by a sensor that measures the die junction temperature of the Xilinx Zynq SoC.

Primary System temperature

The temperature reported digitally by a sensor on the Xilinx Zynq SoC side of the circuit card assembly underneath the integrated heat spreader. This value is an approximation of the local ambient temperature inside the heat spreader.

Secondary System temperature

The temperature reported digitally by a sensor on the SEARAY side of the circuit card assembly. This value is a conservative approximation of the local ambient temperature on that side of the circuit card assembly.

Table 2. Schematic Conventions in This Document

Symbol Description

Off-page symbol that represents communication to and from the mating connector.

Off-page symbol that represents communication from the mating connector.

Off-page symbol that represents communication to the mating connector.

On-page symbol that represents the signal being driven.

Table 1. sbRIO-9651 SOM Terminology in This Document (Continued)

Term Definition


© National Instruments | xi

Additional Documentation ResourcesRefer to the following additional resources as you design, prototype, and implement your sbRIO-9651 SOM application.

On-page symbol that represents the signal being received.

Power supply rail.

Analog ground.

Digital ground.

Chassis ground.

SPARE Refers to an unpopulated reference designator.

Table 2. Schematic Conventions in This Document (Continued)

Symbol Description

I

About This Document

xii | ni.com

What Would You Like toLearn More About?

Resources Availability

NI sbRIO-9651System on Module OEM Device

NI sbRIO-9651 System on ModuleOEM Device Specifications

NI sbRIO-9651System on Module Development Kit

NI sbRIO-9651 System on ModuleDevelopment Kit Quick Start Guide

Designing a carrier boardfor your application

NI sbRIO-9651 System on ModuleCarrier Board Design Guide

LabVIEW Help (NI-RIO) Adding an sbRIO-9651

System on Module target in LabVIEW

Creating a socketed CLIP that defines theI/O configuration to use in your application

NI Single-Board RIO CLIPGenerator Help

NI Training and Supportni.com/singleboard/setup

ni.com/trainingni.com/support

PDF available online at ni.com/manuals Included in the shipping kitHelp file available locally Available online at ni.com

© National Instruments | 1-1

1Fixed Behavior Signals

A subset of pins on the J1 connector on the sbRIO-9651 SOM are dedicated to implementing the following specific I/O functionality:

• Primary Ethernet (GBE0)

• USB Host/Device (USB0)

• USB Host (USB1)

• UART/Console Out (Serial1)

• SD Card

Other pins on the J1 connector are dedicated to implementing the following support signals:

• RTC Battery (VBAT)

• Resets

• Status LED

• FPGA Config

• Temp Alert

Note Refer to the NI sbRIO-9651 System on Module OEM Device Specifications for a complete list of all pins and signals on the J1 connector.

The reference carrier board included with the sbRIO-9651 SOM development kit demonstrates how to implement each of these signals. Refer to the specific sections in this chapter for more information about how the reference carrier board implements each signal.

Primary Ethernet (GBE0)The sbRIO-9651 SOM provides a primary Gigabit Ethernet port (GBE0) for use on a carrier board. Refer to the Secondary Ethernet (GBE1) section of Chapter 2, User-Defined FPGA Signals, for information about implementing a secondary Gigabit Ethernet port.

1-2 | ni.com

Chapter 1 Fixed Behavior Signals

GBE0 Signal DefinitionsTable 1-1 describes the GBE0 port pins and signals on the J1 connector on the sbRIO-9651 SOM.

Table 1-1. GBE0 Signal Definitions

Signal NameDedicated SOM Pin # Direction*

I/O Standard Description

GBE0_MDI0_PGBE0_MDI0_NGBE0_MDI1_PGBE0_MDI1_NGBE0_MDI2_PGBE0_MDI2_NGBE0_MDI3_PGBE0_MDI3_N

19

18263112028

I/O Defined by Ethernet PHY specification.

Pre-magnetic Gigabit Ethernet data pairs.

GBE0_SPEED_LEDgGBE0_SPEED_LEDy

513

O LVTTL Speed LED signals.

GBE0_ACT_LEDg 6 O LVTTL Activity/link LED signal.

* I/O direction is with respect to the sbRIO-9651 SOM.



GBE0 Implementation on the Reference Carrier BoardFigure 1-1 shows a schematic design for the GBE0 implementation on the reference carrier board.

Figure 1-1. GBE0 Reference Schematic

Reference Schematic Design ConsiderationsTable 1-2 lists design considerations for the schematic shown in Figure 1-1.

Table 1-2. GBE0 Reference Schematic Design Considerations

Consideration Notes

MDI data pairs • The MDI data pairs are routed differentially and connected directly to the Ethernet connector.

• The Ethernet connector has the required Ethernet magnetics built into it. You may use discrete magnetics instead.

LED signals • The LED signals can be used to directly drive connector LEDs.

• The current-limiting resistors must be sized so that the drive current of the LED signals is not exceeded.

• Refer to the Ethernet Speed LED Behavior section of the NI sbRIO-9651 System on Module OEM Device Specifications for information about Ethernet LED signal behavior and rated drive current.

GBE0_MDIO_PGBE0_MDIO_NGBE0_MDI1_PGBE0_MDI1_NGBE0_MDI2_PGBE0_MDI2_NGBE0_MDI3_PGBE0_MDI3_N

GBE0_SPEED_LEDg

GBE0_ACT_LEDg

GBE0_SPEED_LEDy

1413

1615

12617

1011

54

23

98

1718

J3

LED2(GRN-AN/YEL-CATH)

08261K1T-43-F

LED2(GRN-CATH/YEL-AN)LED1(GRN-AN)LED1(GRN-CATH)

SHIELD1SHIELD2

MDIA_PMDIA_N~MDIB_PMDIB_N~MDIC_PMDIC_N~MDID_PMDID_N~

MCTAMCTBMCTCMCTD

22222222

2

1 C70.1UF10%16V 2

1 C80.1UF10%16V 2

1 C20.1UF10%16V 2

1 C40.1UF10%16V

2

2

2

R5

475 1%1/16 W

475 1%1/16 W

R62 1

2 1

1-4 | ni.com


Gigabit Ethernet Magnetic RequirementsThe Ethernet PHY on the sbRIO-9651 SOM uses voltage-mode drivers for the MDI pairs, which greatly reduces the power that the magnetics consume and eliminates the need for a sensitive center tap power supply.

You must consider the following requirements for connecting center taps:

• Do not connect the center taps of the isolation transformer on the MDI pair side to any power source. Keep the center taps separate from each other.

• Connect each center tap through separate 0.1 μF capacitors to ground. The separation is required because the common-mode voltage on each MDI pair might be different.

Table 1-3 lists recommended magnetic characteristics.

The sbRIO-9651 SOM development kit uses the Gigabit Ethernet connector parts described in Table 1-4.

Refer to the datasheet for the Micrel Ethernet PHY for more information about magnetic requirements.

GBE0 Routing ConsiderationsNI recommends the following design practices for properly routing GBE0 signals on your carrier board:

• Route MDI pairs differentially with 100 Ω differential trace impedance.

• Length-match the positive and negative signal for each MDI data pair to within 10 mils.

Table 1-3. Recommended Magnetic Characteristics

Parameter Value Test Condition

Turns ratio 1 CT : 1 CT —

Open-circuit inductance (min) 350 μH 100 mV, 100kHz, 8 mA

Insertion loss (max) 1.0 dB 0 MHz to 100 MHz

HIPOT (min) 1500 Vrms —

Table 1-4. Gigabit Ethernet Connector Parts

Part Manufacturer Part Number

sbRIO-9651 SOM PHY Micrel KSZ9031MNXIA

Reference carrier board Gigabit Ethernet connector

Bel Stewart Magjack 0826-1K1T-43-F



• Limit the MDI trace lengths on the carrier board to 6.0 in. or less, which is the length at which Ethernet compliance was tested.

USB (USB0, USB1)The sbRIO-9651 SOM provides two USB 2.0-compliant ports for use on a carrier board: USB Host/Device port (USB0) and USB Host port (USB1).

Note Your carrier board design must provide the 5 V USB_VBUS power to USB Host ports and must limit the current supplied to each host port according to USB specifications.

USB0 Host/Device Signal DefinitionsTable 1-5 describes the USB0 Host/Device port pins and signals on the sbRIO-9651 SOM connector.

Table 1-5. USB0 Host/Device Signal Definitions

Signal NameDedicated SOM Pin # Direction* I/O Standard Description

USB0_DP 33 I/O Defined by USB specification.

USB0 data pair.

USB0_DN 41

USB0_MODE 65 I LVTTL Controls whether the USB0 port provides a Host or Device connection. Refer to the Configuring the USB0 Mode section of this chapter for more information.

USB0_CPEN 73 O LVTTL USB0 over-current protection enable.

USB0_VBUS 81 I 5 V tolerant voltage sense

USB0 VBUS input. Allows USB PHY to sense if VBUS is present on the connector.


1-6 | ni.com


Configuring the USB0 ModeYou can configure the USB0 interface to be a USB Host port or a USB Device port, as shown in Table 1-6. This mode is set when the system boots and does not change dynamically. The reference carrier board uses the USB0 interface for a USB Device port.

Note USB On-The-Go (OTG) is not supported.

USB0 Device Implementation on the Reference Carrier BoardFigure 1-2 shows a schematic design for the USB0 Device implementation on the reference carrier board.

Figure 1-2. USB0 Device Reference Schematic

Table 1-6. Configuring the USB0 Mode

Mode How to Enable

USB Host Connect the USB0_MODE signal to digital ground on your carrier board. You can implement USB0 Host functionality in the same way that the USB1 Host signal is implemented on the reference carrier board, as described in the USB1 Host Implementation on the Reference Carrier Board section of this chapter.

USB Device Connect the USB0_MODE signal to the VCC_3V3 rail on your carrier board. Refer to the USB0 Device Implementation on the Reference Carrier Board section of this chapter for more information about the USB0 Device implementation on the reference carrier board.

USB0_DP

USB0_DN

USB0_VBUS

USB0_MODE

34

L2

DLW21S_90012

3 GND

U17TPD2EUSB30

2

1 C330.1 UF10%16 V

1

2

C321.0 UF10%16 V

4

6

1

5

23

J8

CONN-USB,B,HIGH_RETENTION

SHLD1SHLD2

GND

D–D+

VBUS2

2

2

+3.3V

2

21 R78

0 5%1/16W

21 R76

0, 5%1/16 W

R6621

1 K0.5% 0.1 UF 10%

50 V

1 2C204

R61

SpareR0603

21

Population OptionsFor EMC/EMI

Pulled Up To Select Usb Device Port

Not Populated

These lines can swapif layout is easier

D+D–




USB1 Host Signal DefinitionsTable 1-8 describes the USB1 Host port pins and signals on the sbRIO-9651 SOM connector.

Table 1-7. USB0 Device Reference Schematic Design Considerations

Consideration Notes

USB data pair • The USB0_DP and USB0_DN data pair is routed differentially to the USB connector.

• On the reference carrier board, the L2 common-mode choke is not populated, but you can populate it in your design to help with conducted immunity or emissions.

• If you choose to populate L2, remove R76 and R78 from your design.

• If your design does not include a common-mode choke, you can route the USB pair directly from the USB connector to the sbRIO-9651 SOM connector.

• U17 provides ESD protection to the USB data pair and should be placed close to the USB connector.

USB0_MODE The USB0_MODE signal is pulled up to 3.3 V to select USB Device functionality.

USB0_CPEN Leave the USB0_CPEN signal disconnected for a USB Device port.

USB0_VBUS • For the USB Device port to function properly, the USB0_VBUS signal must be connected to the VBUS pin on the USB connector.

• This is a low-current, voltage-sense connection.

• In layout, you can treat this connection as a data signal.

• R66 helps provide some overvoltage protection on USB0_VBUS and should be placed close to the USB connector. NI recommends that you use a 1 kΩ resistor.

Table 1-8. USB1 Host Signal Definitions



USB1_DP 35 I/O Defined by USB specification.

USB1 data pair.

USB1_DN 43

1-8 | ni.com


USB1 Host Implementation on the Reference Carrier BoardFigure 1-3 shows a schematic design for the USB1 Host implementation on the reference carrier board.

Figure 1-3. USB1 Host Reference Schematic

USB1_CPEN 50 O LVTTL USB1 over-current protection enable.

USB1_VBUS 58 I 5 V tolerant voltage sense

USB1 VBUS input. Allows USB PHY to sense if VBUS is present on the connector.


Table 1-8. USB1 Host Signal Definitions (Continued)



USB1_DN

USB1_DP

USB1_CPEN

USB1_VBUS

4

2

3

1L3

DLW21S_900

3

2

1 D+

D–

U18TPD2EUSB30

GND1

2

R864.7 K0.5%1/16 W

R921 k0.5%

2

1–

C67100 UF6.3 V20%

1

2

C570.1 UF10%16 V

43

52

1

7

6U20

IN

EN

ILIM

OUT

FAULT~

GNDPAD

TPS25531

2 2

1R8923.2 K0.5%1/16 W

R854.7 K0.5%1/16 W

4

56

123

J10

VCC–DAT1+DAT1

SHLD1SHLD2

GND

USB_A

2

2

2

2

+5 V +5 V

21R82

0 5%1/16 W

21R79

0 5%1/16 W

1

2

R931 K.5%

1

2

2

1 C610.01 UF100 V10%

1

2

C6222 UF25 V10%

0.1 UF 10%50 V

C2031 2

POPULATION OPTIONSFOR EMC/EMI

NOT POPULATED

These lines can swapif layout is easier




Table 1-9. USB1 Host Reference Schematic Design Considerations

Consideration Notes

USB data pair • The USB1_DP and USB1_DN data pair is routed differentially to the USB connector.

• On the reference carrier board, the L3 common-mode choke is not populated, but you can populate it in your design to help with conducted immunity or emissions.

• If you choose to populate L3, remove R79 and R82 from your design.

• If your design does not include a common-mode choke, you can route the USB pair directly from the USB connector to the sbRIO-9651 SOM connector.

• U18 provides ESD protection to the USB data pair and should be placed close to the USB connector.

USB1_CPEN The USB1_CPEN signal must be connected to the enable of the VBUS current limit switch (U20). This allows the sbRIO-9651 SOM to power-cycle USB devices when the processor is reset.

USB1_VBUS • For the USB Host port to function properly, the USB1_VBUS signal must be connected to VBUS on the USB connector.

• This is a low-current, voltage-sense connection.

• In layout, you can treat the trace after R92 going to the sbRIO-9651 SOM connector as a data signal.

• R92 helps provide some overvoltage protection on USB1_VBUS and should be placed close to the USB connector. NI recommends that you use a 1 kΩ resistor.

• The carrier board must provide 5 V VBUS power for the USB Host port.

• A current limit switch is required between the 5 V rail and the USB connector.

• U20 is the current limiter.

• NI recommends that you provide 100 μF of capacitance on the VBUS rail.

1-10 | ni.com


Supporting Onboard USB DevicesWhen you implement a USB device directly on your carrier board, you can connect the device to a USB Host port from the sbRIO-9651 SOM. For this case, use the following design guidelines:

• You can connect the USB data pair directly to a USB device on your carrier board.

• A current limiter is not required.

• Use the CARRIER_RST# signal to reset the USB device when the sbRIO-9651 SOM is in reset.

• Tie the USBx_VBUS signal to 3.3 V or 5 V.

USB Routing ConsiderationsNI recommends the following design practices for properly routing USB signals on your carrier board:

• Route the USBx_DP and USBx_DN signals as differential pairs with 90 Ω differential impedance.

• Length-match the positive and negative signal for each USB data pair to within 10 mils.

• Limit the USBx_DP and USBx_DN trace lengths on the carrier board to 8.0 in. or less, which is the length at which USB compliance was tested.

UART/Console Out (Serial1)The sbRIO-9651 SOM provides a dedicated UART (Serial1) interface for use on a carrier board. This interface also functions as an operating system console when Console Out is enabled. Refer to the Additional RS-232 (Serial2, Serial3, Serial4) and RS-485 (Serial5, Serial6) sections of Chapter 2, User-Defined FPGA Signals, for information about implementing additional serial ports.

Serial1 Signal DefinitionsTable 1-10 describes the Serial1 port pins and signals on the sbRIO-9651 SOM connector.

Note The NI-Serial driver has been developed for and tested with the Texas Instruments TRS3253EIRSMR RS-232 transceiver. Other transceivers may be compatible.



Serial1 Implementation on the Reference Carrier BoardFigure 1-4 shows a schematic design for the Serial1 implementation on the reference carrier board.

Figure 1-4. Serial1 Reference Schematic


Table 1-10. Serial1 Signal Definitions



SERIAL1_TX 52 O LVTTL Two-wire serial and console out signals for the sbRIO-9651 SOM.SERIAL1_RX 60 I


Table 1-11. Serial1 Reference Schematic Design Considerations

Consideration Notes

Interface The reference carrier board demonstrates how to use the Serial1 interface to implement a two-wire RS-232 serial port.

Serial transceiver

U24 is the RS-232 serial transceiver that converts between RS-232 and LVTTL signal levels. To minimize the impact of higher voltage signals on your carrier board, place the serial transceiver near the RS-232 connector.

FPGA_CFG

SERIAL1_TX

SERIAL1_RXSERIAL1_RX_CONN#SERIAL1_RX_F#

SERIAL1_TX_F#SERIAL1_TX_CONN#

12 2

0.1 UF 10%50 V

0.1 UF 10%50 V

C111

C107

1

2 C1880.1 UF10%16 V

29

311

2

457

252322

289

6

816

24

32

2120191817

1413121110

15

27

3

30

33

26

U24

DIN1DIN2DIN3

ROUT1ROUT2ROUT3ROUT4ROUT5

C1+

C1-C2+

C2-

INVALID~

FORCEONFORCEOFF~

TRS3253EIRSMR

VL

NC1NC

NC3NC4

THERMALPAD

V–

V+

DOUT1

RIN3RIN2RIN1

VCC

GND

RIN4

DOUT2DOUT3

RIN5

2

11 2

1 2

C18710%0.1 UF16 V

1

2

C1890.1 UF10%16 V

C1900.1 UF10%16 V

1

2

2

1 R1244.7 K 0.5%1/16 W

2

1 R1214.7 K0.5%1/16 W

2, 4

1110

9

8

7

6

5

4

3

2

1

12

34

67

89

5

J15DSUB9-761918-A

2

+3.3 V

+3.3 V

+3.3 V +3.3 V

+3.3 V

R116

R115

2

1R125

1 K0.5%

39 0.5%1/16 W

R123

R122SPARER0402

1

2

C94

C1206, SPARE

C99

C1206, SPARE

C106

1 2

1 2

1 2

1 2

1 2

0 5%1/16 W

0 5%1/16 W

0.1 UF 10%50 V

1-12 | ni.com


Adding Flow Control and Modem Control SignalsYou can use the sbRIO CLIP Generator application included with the NI-RIO Device Drivers software to add optional flow control and modem control signals to the Serial1 interface.

Refer to the Additional RS-232 (Serial2, Serial3, Serial4) section of Chapter 2, User-Defined FPGA Signals, for an example of how to implement a full-modem RS-232 port. Refer to the NI Single-Board RIO CLIP Generator Help, described in the Additional Documentation Resources section of the About This Document preface, for more information about using the sbRIO CLIP Generator application.

SD CardThe sbRIO-9651 SOM provides a Secure Digital (SD) Card interface for use on a carrier board. This interface supports SD and SDHC cards. You can implement this interface with standard SD or microSD card connectors. The maximum supported SDHC card capacity is 32 GB.

Series termination

R123 is the series termination for SERIAL1_RX. Use series termination at the serial transceiver on all signals being driven to the sbRIO-9651 SOM. The sbRIO-9651 SOM provides onboard series termination for SERIAL1_TX near the Xilinx Zynq SoC.

FPGA All serial port signals pass through the FPGA on the sbRIO-9651 SOM. The FPGA_CFG signal is used to disable the serial transceiver when the FPGA is not configured. Disabling the transceiver in this way prevents any unwanted glitches on the RS-232 port.

Table 1-11. Serial1 Reference Schematic Design Considerations (Continued)

Consideration Notes



SD Signal DefinitionsTable 1-12 describes the SD pins and signals on the sbRIO-9651 SOM connector.

Table 1-12. SD Signal Definitions

Signal NameDedicated SOM Pin # Direction* I/O Standard Description

SD_CLK 15 O LVTTL SD clock.

SD_CMD 31 I/O LVTTL SD command.

SD_D0SD_D1SD_D2SD_D3

8222430

I/O LVTTL SD data bus.

SD_CD# 32 I LVTTL SD card detect. Assert low when card is present. Can connect to a mechanical switch in the SD card socket.

SD_WP 40 I LVTTL SD write protect. Assert high to enable protection. Can connect to a mechanical switch in the SD card socket.

SD_PWR_EN 38 O LVTTL Power enable for SD card socket.


1-14 | ni.com


SD Implementation on the Reference Carrier BoardFigure 1-5 shows a schematic design for the SD implementation on the reference carrier board.

Figure 1-5. SD Reference Schematic

SD_CLK

SD_PWR_EN

SD_OC#

SD_CD#

SD_WP

VOUT_SD

SD_D2

SD_D1

SD_D0

SD_D3

SD_CMD

3

4

12

6

13

987

11

25

1

10

J2

Shi

eld1

WP

SD SOCKET

CommonCardDetect

D1D0

Vss2

CLK

Vdd

Vss1

CMD

CD/D3D2

CONN9-764432-01-RA

2

1 C130.1 UF10%16 V

1

2

C14410%0.1 UF16 V

+3.3 V

2

1 C1210 UF10%10 V

4

32

5

6781

U9

EN

INS1INS2

GND

OC#

OUTD1OUTD2OUTD3

TPS2030D

2

1 R144.7 K0.5%1/16 W

+3.3V

2

2

2

2

2

2

2

2

2 1 2R38

0 5%1/16 W

1

2

R211 K0.5%

1

2

R1981 K0.5%

1 2

2

1

R1991 K0.5%

21

68.1 .5%1/16 W

68.1 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

R217

+3.3V

+3.3V

21

21

21

21

21

R216

R211

R212

R213

R214

R215

C205

0.1UF 10%50 V

1 2




Table 1-13. SD Reference Schematic Design Considerations

Consideration Notes

SD_CLK, SD_CMD, and SD_D0 through SD_D3

• You can route these signals directly from the sbRIO-9651 SOM to the SD connector.

• Each of these signals requires series termination near its driver. The sbRIO-9651 SOM provides series termination near the Xilinx Zynq SoC to prevent overshoot on the SD card when the sbRIO-9651 SOM drives these signals. The bi-directional signals also require series termination at the SD converter.

• Use series termination at the SD connector for the SD_CMD and SD_D0 through SD_D3 signals to prevent overshoot on the sbRIO-9651 SOM when the SD card drives these signals.

SD_CD# • The SD_CD# signal is connected to the mechanical card-detect switch in the SD connector.

• When a card is inserted, the card-detect pin on the SD connector is shorted to ground.

• Because this is a mechanical switch with low output impedance, you must place a series termination resistor (R216) at the SD connector.

• You must have a card-detect switch to properly support hot-swapping cards. If you do not need to support hot-swapping cards, you can use an SD connector without a card-detect switch. In this case, tie the SD_CD# signal to ground so that the sbRIO-9651 SOM attempts to initialize a card on boot.

1-16 | ni.com


SD Routing ConsiderationsNI recommends the following design practices for properly routing SD signals on your carrier board:

• Length-match the SD_CMD and SD_D0 through SD_D3 signals to within ±250 mils of SD_CLK.

• Limit the trace length of the SD_CLK, SD_CMD, and SD_D0 through SD_D3 signals on the carrier board to 8.0 in. or less.

RTC Battery (VBAT)The reference carrier board contains a lithium cell battery that maintains the real-time clock (RTC) on the sbRIO-9651 SOM when the sbRIO-9651 SOM is powered off. A slight drain on the battery occurs when power is not applied to the sbRIO-9651 SOM. For information about the VBAT current drain, refer to the VBAT Requirements section of the NI sbRIO-9651 System on Module OEM Device Specifications.

If the battery is dead, or if no voltage has been applied to the VBAT pins, the system still starts but the system clock resets to the UNIX epoch date and time.

SD_WP • When the SD_WP signal is asserted high, the sbRIO-9651 will not write to the SD card.

• Standard-size SD card connectors provide a mechanical write-protect switch that you can connect to the SD_WP signal. The switch detects the position of the lock slide on the SD card.

• Because this is a mechanical switch with low output impedance, you must place a series termination resistor (R217) at the SD connector.

• If you are using a microSD connector or do not have a write-protect switch, you can tie the SD_WP signal to ground in order to disable write protection and allow changes to the SD card.

SD_PWR_EN • Use the SD_PWR_EN signal to gate power to the SD connector.

• U9 acts as a power switch and current limiter for the SD interface. SDHC cards must not draw more than 200 mA.

• The SD_PWR_EN signal controls when power is going to the SD card.

• The SD_PWR_EN signal asserts high when a card is detected using the SD_CD# signal. The SD_PWR_EN signal deasserts when a card is not present.

Table 1-13. SD Reference Schematic Design Considerations (Continued)

Consideration Notes



VBAT Signal DefinitionsTable 1-14 describes the VBAT pins and signals on the sbRIO-9651 SOM connector.

VBAT Implementation on the Reference Carrier BoardFigure 1-6 shows a schematic design for the VBAT implementation on the reference carrier board.

Figure 1-6. VBAT Reference Schematic

Reference Schematic Design ConsiderationsYou can directly connect the battery to VBAT. The sbRIO-9651 SOM already provides a current-limiting resistor and reverse-voltage protection.

Eliminating the Effects of Contact BounceIf you are using the A revision of the sbRIO-9651 SOM, it is important to eliminate the effects of contact bounce when you initially attach the battery.

Note To determine the revision, check the bottom side of the sbRIO-9651 SOM for a sticker with the part number 157660x-01L, where x is the revision letter.

Contact bounce can cause a momentary power interruption to the RTC, which might result in drift greater than the RTC accuracy listed in the NI sbRIO-9651 System on Module OEM Device Specifications.

Table 1-14. VBAT Signal Definitions



VBAT 64 I Power rail RTC battery input that provides backup power to the RTC to keep track of absolute time.


VBAT2

BTH1

2

1

+–

BA

TH

LDR

-747

921-

01

Use Br1225Battery In

This Holder

1-18 | ni.com


To eliminate the effects of contact bounce, try one of the following methods:

• (Preferred) Use power sequencing by applying Vcc to the RTC before attaching the battery.

• Filter the signal using a small capacitor between VBAT and ground. The manufacturer recommends capacitor values between 0.1 nf and 1.0 nf.

ResetsThe sbRIO-9651 SOM provides signals for implementing a reset button on a carrier board and indicating that the sbRIO-9651 SOM is in reset.

Reset Signal DefinitionsTable 1-15 describes the Reset pins and signals on the sbRIO-9651 SOM connector.

Table 1-15. Reset Signal Definitions



CARRIER_RST# 37 O LVTTL Reset that indicates that main power is not adequate or that the sbRIO-9651 SOM is in reset. Asserted low.

SYS_RST# 47 I LVTTL System reset that puts the sbRIO-9651 SOM in reset. Asserted low.

Asserting this signal causes the CARRIER_RST# signal to also assert.

You can also assert this signal to put the sbRIO-9651 SOM into safe mode or reset IP address settings.




Reset Implementation on the Reference Carrier BoardFigure 1-7 shows a schematic design for the Reset implementation on the reference carrier board.

Figure 1-7. Reset Reference Schematic

Refer to the SYS_RST# and CARRIER_RST# sections of the NI sbRIO-9651 System on Module OEM Device Specifications for more information about the behavior of the Reset signals.


Table 1-16. Reset Reference Schematic Design Considerations

Consideration Notes

Series termination

When SYS_RST# is driven, you must place a series termination resistor at the driver. When the driver is a mechanical switch, placing series termination is especially important due to the low output impedance of the switch.

SYS_RST#RESET_SW#2

C3C0402SPARE

1

2SW3

720176-01

1

2

3

4

+3.3 V

R41K0.5%

1

2

21R2

68.1 0.5%1/16 W

1-20 | ni.com


Status LEDThe sbRIO-9651 SOM provides a Status LED signal for use on a carrier board. The Status LED indicates the status of the SOM boot process or Safe Mode and can be used to report software errors.

Status LED Signal DefinitionsTable 1-17 describes the Status LED pins and signals on the sbRIO-9651 SOM connector.

Status LED Implementation on the Reference Carrier BoardFigure 1-8 shows a schematic design for the Status LED implementation on the reference carrier board.

Figure 1-8. Status LED Reference Schematic

Refer to the STATUS_LED section of the NI sbRIO-9651 System on Module OEM Device Specifications for more information about the behavior of the Status LED signal.

Table 1-17. Status LED Signal Definitions



STATUS_LED 14 O LVTTL Status LED indicator.


STATUS_LED21

DS7

YEL2

R12721

357 0.5%1/16 W



FPGA ConfigThe sbRIO-9651 SOM provides an FPGA Config signal to indicate when the FPGA is configured.

FPGA Config Signal DefinitionsTable 1-18 describes the FPGA Config pins and signals on the sbRIO-9651 SOM connector.

FPGA Config Implementation on the Reference Carrier BoardFigure 1-9 shows a schematic design for the FPGA Config implementation on the reference carrier board.

Figure 1-9. FPGA Config Reference Schematic

Refer to the FPGA_CFG section of the NI sbRIO-9651 System on Module OEM Device Specifications for more information about the behavior of the FPGA Config signal.

Table 1-18. FPGA Config Signal Definitions

Signal Name

Dedicated SOM Pin # Direction* I/O Standard Description

FPGA_CFG 53 O Refer to the NI sbRIO-9651 System on Module OEM Device Specifications for more information about the behavior of this signal.

FPGA Config Asserts when the FPGA is configured. Asserted high when the FPGA has been programmed.


357 0.5%1/16 W

FPGA_CFG2, 3, 4 1 12

R1282

DS3

GRN

LED_GRN_735278-01

1-22 | ni.com


Temp AlertThe sbRIO-9651 SOM provides a Temp Alert signal to indicate that the onboard CPU/FPGA or Primary System temperature has exceeded the minimum or maximum temperature specifications of the sbRIO-9651 SOM. Refer to the Environmental section of the NI sbRIO-9651 System on Module OEM Device Specifications for the minimum and maximum temperature specifications.

Temp Alert Signal DefinitionsTable 1-19 describes the Temp Alert pins and signals on the sbRIO-9651 SOM connector.

Temp Alert Implementation on the Reference Carrier BoardFigure 1-10 shows a schematic design for the Temp Alert implementation on the reference carrier board.

Figure 1-10. Temp Alert Reference Schematic

Refer to the TEMP_ALERT section of the NI sbRIO-9651 System on Module OEM Device Specifications for more information about the behavior of the Temp Alert signal.

Refer to the Validating Temperature Measurements section of Chapter 4, Mechanical Considerations, for information about validating the system temperatures of your sbRIO-9651 SOM application.

Table 1-19. Temp Alert Signal Definitions



TEMP_ALERT 46 O LVTTL Temp Alert indicator. Asserted high.


TEMP_ALERT11 22

DS4

RED

LED-QTLP630

2

357 0.5%1/16 W

R129


2User-Defined FPGA Signals

The sbRIO-9651 SOM connector provides several banks of FPGA pins that you can configure for purposes specific to your application. In addition to FPGA Digital I/O (DIO), you can use these pins to implement the following run-time peripheral interfaces:

• Secondary Ethernet (GBE1)

• Additional RS-232 (Serial2, Serial3, Serial4)

• RS-485 (Serial5, Serial6)

• CAN (CAN0, CAN1)

The reference carrier board included with the sbRIO-9651 SOM development kit shows an example of how to implement these signals. Refer to the specific sections in this chapter for more information about how the reference carrier board implements each signal.

Note To read or write to this I/O from a LabVIEW project, you must use the sbRIO CLIP Generator application to create a socketed component-level IP (CLIP) that defines the I/O configuration of the sbRIO-9651 SOM to use in your application. Refer to the Getting Started with the NI sbRIO-9651 in LabVIEW topic in the LabVIEW Help for more information about creating a CLIP.

Tip When you create your own CLIP, you must compile your FPGA VI and download it to the flash of the sbRIO-9651 SOM. This ensures that the driver for each enabled peripheral can load properly at boot time. Refer to the Downloading an FPGA VI to the Flash Memory of an FPGA Target topic in the LabVIEW Help (FPGA Module) for more information.

Secondary Ethernet (GBE1)You must use specific FPGA pins to implement a secondary Ethernet port due to the strict timing requirements across semiconductor process and temperature variations.

The reference carrier board implements one secondary Ethernet port (GBE1) in addition to the primary Ethernet port. Refer to the Primary Ethernet (GBE0) section of Chapter 1, Fixed Behavior Signals, for more information about implementing a primary Ethernet port.

Note The sbRIO CLIP Generator enforces the selection of specific FPGA pins when you implement a secondary Ethernet port.

2-2 | ni.com

Chapter 2 User-Defined FPGA Signals

GBE1 Signal Definitions on the Reference Carrier BoardTable 2-1 describes the GBE1 pins and signals on the sbRIO-9651 SOM connector used to implement a secondary Ethernet port on the reference carrier board.

Table 2-1. GBE1 Signal Definitions

Signal Name Pin #*

DIO Signal on Reference

Carrier Board Direction† Description

TX Signals

GBE1_GMII_GTX_CLK 192 DIO_62_N O Gigabit transmit clock.

GBE1_MII_TX_CLK 207 DIO_60_SRCC I 10/100 transmit clock.

GBE1_GMII_TX_EN 215 DIO_60_N O Transmit enable.

GBE1_GMII_TX_ER 183 DIO_59 O Transmit error.

GBE1_GMII_TX_D0GBE1_GMII_TX_D1GBE1_GMII_TX_D2GBE1_GMII_TX_D3GBE1_GMII_TX_D4GBE1_GMII_TX_D5GBE1_GMII_TX_D6GBE1_GMII_TX_D7

235227211203187179234242

DIO_49_NDIO_49DIO_48_NDIO_48DIO_47_NDIO_47DIO_46_NDIO_46

O Transmit data bus.

RX Signals

GBE1_GMII_RX_CLK 231 DIO_61_MRCC I Receive clock.

GBE1_GMII_RX_DV 200 DIO_62_MRCC I Receive data valid.

GBE1_GMII_RX_ER 239 DIO_61_N I Receive error.



GBE1_GMII_RX_D0GBE1_GMII_RX_D1GBE1_GMII_RX_D2GBE1_GMII_RX_D3GBE1_GMII_RX_D4GBE1_GMII_RX_D5GBE1_GMII_RX_D6GBE1_GMII_RX_D7

210218194186170162225233

DIO_45_NDIO_45DIO_44DIO_44_NDIO_43DIO_43_NDIO_42DIO_42_N

I Receive data bus.

Support Signals

GBE1_GMII_COL 201 DIO_41 I Collision detect.

GBE1_GMII_CRS 209 DIO_41_N I Carrier sense.

GBE1_MDC 177 DIO_40 O MDIO clock, which needs to be pulled up on carrier board.

GBE1_MDIO 185 DIO_40_N I/O MDIO data, which needs to be pulled up on carrier board.

GBE1_IRQ# 191 DIO_59_N I PHY interrupt request, which should be pulled high on reference carrier board.

Table 2-1. GBE1 Signal Definitions (Continued)

Signal Name Pin #*



2-4 | ni.com


GBE1 Reference SchematicFigure 2-1 shows a schematic design for the GBE1 implementation on the reference carrier board.

GBE1_SPEED_LEDgGBE1_SPEED_LEDy

126‡

118‡DIO_33DIO_33_N

O Speed LED signals:Yellow = 1000Green = 100Off = 10

* When you use the sbRIO CLIP Generator to enable secondary Ethernet, you must use the pins listed in this table. If you do not enable secondary Ethernet, you can use these pins for other FPGA DIO.

† I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the sbRIO CLIP Generator.

‡ You can use any available FPGA DIO lines to implement these signals. In NI-RIO Device Drivers February 2015 or later, you can use the sbRIO CLIP Generator to assign FPGA DIO to these signals.

Table 2-1. GBE1 Signal Definitions (Continued)

Signal Name Pin #*



NI sbR

IO-9651 S

ystem on M

odule Carrier B

oard Design G

uide

© N

ational Instruments

|2-5

Figure 2-1. GBE1 Reference Schematic

AVDDL_PLL_1V2

GBE1_GMII_RX_CLK

GBE1_GMII_RX_DV

GBE1_GMII_RX_D[3]

GBE1_GMII_RX_D[2]

GBE1_GMII_RX_D[1]

GBE1_GMII_RX_D[0]

PERIPHERAL_RESET_1V8#

GBE1_IRQ#

GBE1_ISET

GBE1_LED[1]_1P8GBE1_LED[2]_1P8GBE1_LED_MODE

NC_GBE1_62NC_GBE1_6

AVDDL_PLL_1V2

GBE1_GMII_GTX_CLK

GBE1_MII_TX_CLK

GBE1_GMII_TX_EN

GBE1_GMII_TX_D[7]GBE1_GMII_TX_D[6]GBE1_GMII_TX_D[5]GBE1_GMII_TX_D[4]GBE1_GMII_TX_D[3]GBE1_GMII_TX_D[2]GBE1_GMII_TX_D[1]GBE1_GMII_TX_D[0]

GBE1_GMII_RX_D[5]

GBE1_GMII_RX_D[7]

GBE1_GMII_RX_D[6]

GBE1_GMII_RX_D[4]

GBE1_GMII_RX_ER

GBE1_GMII_CRS

GBE1_GMII_COL

GBE1_GMII_TX_ER

GBE1_MDIO_PGBE1_MDIO_N

GBE1_MDI1_PGBE1_MDI1_N



GBE1_MDC

GBE1_MDIO

CARRIER_RST#

GBE1_XTAL_OUT

GBE1_XTAL_IN

PERIPHERAL_RESET_1V8#

GBE1_SPEED_LEDy

GBE1_SPEED_LEDg

GBE1_ACT_LED

GBE1_ACT_LED

C1370.1 UF10%16 V2

1 C1430.1 UF10%16 V2

1 C1250.1 UF10%16 V

1

2

C13110 UF10%10 V2

1 C1240.1 UF10%16 V

1

2

C1260.1 UF10%16 V

1

2

C1400.1 UF10%16 V2

1

+3.3 V

C11810 UF10%10 V

1

2

C1410.1 UF10%16 V2

1 C1420.1UF10%16 V2

1 C1380.1 UF10%16 V

1

2

+1.2V

C1270.1 UF10%16 V

1

2

C1320.1 UF10%16 V

1

2

C1390.1 UF10%16 V2

1C14810 UF10%10 V2

1 C1340.1 UF10%16 V

1

2

C1360.1 UF10%16 V

1

2

C1330.1 UF10%16 V2

1

+1.2V

C1280.1 UF16 V10%2

1

C1610 UF10%10 V

1

2

C150.1 UF10%16 V2

1

+1.2 V

21L1F

BLM15AG121

+3.3 V

+1.2 V

+1.2 V

2

2

2

2

2

2

2

2

2

R1344.7 K0.5%1/16 W

2

1

1

3

42 Y1

25M

HZ

GND1GND2

2

1

R2710 K0.5%1/16 W

2

1

2

1

R2210 K0.5%1/16 W

2

1

R3510 K0.5%1/16 W

2

1

1R3910 K0.5%1/16 W

2

R2610 K0.5%1/16 W

1

2

2

2

2

22222222

2

2

2

2

2

2

2

U10

6061

313357

2928272624232221

4745

48

3435373839414344

56

626

5150

32

5442362520

46403018

4952

53

14

10

7

2

15

11

8

3

65

1917

58

63

55

59

131254

161

649

TX_ER

AVDDL[3]AVDDL[2]AVDDL[1]AVDDL[0]

AVDDH[1]AVDDH[0]

LDO_OAVDDL_PLL

TXRXM_ATXRXP_A

TXRXM_BTXRXP_B

TXRXM_CTXRXP_C

TXRXM_DTXRXP_D

LED1/PHYAD0/~P~M~E~_~1LED[2]/PHYAD1

CLK125_ND0/LED_MODE~I~N~T/~P~M~E~_~2

ISETP_GND

AGNDH[0]AGNDH[1]

NC[0]NC[1]

DVDDH[0]DVDDH[1]DVDDH[2]DVDDH[3]

DVDDL[0]DVDDL[1]DVDDL[2]DVDDL[3]DVDDL[4]

GTX_CLKTX_CLKTX_EN

TXD7TXD6TXD5TXD4TXD3TXD2TXD1TXD0

RXD0/MODE0RXD1/MODE1RXD2/MODE2RXD3/MODE3RXD4RXD5RXD6RXD7RX_DV/CLK125_ENRX_ERRX_CLK/PHYAD2

COLCRS

MDCMDIO

RESET~

XIXO

2

C180.1 UF10%16 V

1

2

C190.1 UF10%16 V

1

2

C100.1 UF10%16 V

1

2

C90.1 UF10%16 V

1

2

J6

1817

89

32

45

1110

716

12

1516

1314

LED2(GRN-AN/YEL-CATH)LED2(GRN-CATH/YEL-AN)LED1(GRN-AN)LED1(GRN-CATH)

SHIELD1SHIELD2

MDIA_PMDIA_N~MDIB_PMDIB_N~MDIC_PMDIC_N~MDID_PMDID_N~

MCTAMCTBMCTCMCTD

+3.3V

2

2

R30

475 1%1/16W

12

U8

3

5

4

1

2

NC

A

VCC

GND

Y

SN74LVC1G04DBVR

C1510.1 UF10%16 V2

1

U13

2

16

54 3

74LVC1T45

BADIR

VCCB

GND

VCCA

C200.1 UF10%16 V1

2

2

+3.3V

R1374.7 K 0.5%1/16 W

1

2

R1364.7 K0.5%1/16 W

2

1

R534751%1/16 W 2

1

C1470.1 UF10%16 V

2

1

C1220.1 UF10%16 V1

2

C12312

0.1 UF 10%16 V

U5

74LVCE1G08

AB

Y

3

21

5

4

C11521

0.1 UF 10%16 V

R4412

0 5%1/16 W

2

R1331 K0.5%

2

1

R54

2

1

1 K0.5%

R521 K0.5%

2

1

R55 21

R51 21

R40

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

24.9 0.5%1/16 W

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2R36

R37

R15

R16

R17

R18

R24

R25

R29

R28

R50

R47

R49 C171 2

1 2

33 pF 50 V

C14

33 pF 50 V

U7

74LVCE1G08

AB

Y

3

21

5

4

R45SPARER0402

1

2

+1.8V +1.8V +1.8V

+1.8 V

+1.8 V +1.8 V

+1.8 V

+1.8V

2

16

3 4

5

U11

GDN VCC

A2 Y2

A1 Y1

+1.8 V

+1.8 V

+1.8 V

C2070.1 UF10%16 V

1

2

U26

345

6 1

2

74LVC1T45

BADIR

VCCB

GND

VCCA

C2080.1 UF10%16 V

2

1

+3.3 V+1.8 V

C20621

0.1 UF 10%50 V

R222390.5%1/16 W

1

2

R223390.5%1/16 W

1

2

R224390.5%1/16 W

1

2

DVDDH Decoupling

AVDDH Decoupling

DVDDL Decoupling

AVDDL_PLL Decoupling

R191 K0.5%

1

+1.8V

R4112.1 K0.1%1/16 W

R201 K0.5%

2

1

R2310 K0.5%1/16 W

KSZ9031MNXIA

08261K1T-43-F

NC7WZ16

2-6 | ni.com


Figure 2-2 shows additional schematic details for the GBE1 TX signal series termination resistors at the SEARAY.

Figure 2-2. GBE1 TX Series Termination Reference Schematic

GBE1_MII_TX_CLK

GBE1_GMII_RX_CLKGBE1_GMII_RX_ER

GBE1_GMII_RX_DV

GBE1_MDC

GBE1_GMII_COLGBE1_GMII_CRS

GBE1_IRQ#

GBE1_GMII_RX_D[6]GBE1_GMII_RX_D[7]




GBE1_GMII_TX_D[6]

GBE1_GMII_TX_D[7]

GBE1_GMII_TX_ER

GBE1_GMII_GTX_CLK

GBE1_GMII_TX_ENGBE1_GMII_TX_D[3]

GBE1_GMII_TX_D[2]

GBE1_GMII_TX_D[5]

GBE1_GMII_TX_D[4]

GBE1_GMII_TX_D[1]

GBE1_GMII_TX_D[0]

GBE1_MDIO7

7

77

77

77

77

77

77

7

7

7

7

7

7

7

7

7

7

7

7

7

7

1

2 C1460.1 UF16 V10% 1

2 C1450.1 UF10%16 V

+1.8V+1.8V

21

49.9 0.5%1/16W

49.9 0.5%1/16W

49.9 0.5%1/16W

R200

21R201

21 R202

R203

R204

21

21

21

49.9 0.5%1/16 W

49.9 0.5%1/16 W

49.9 0.5%1/16 W

49.9 0.5%1/16 W

49.9 0.5%1/16 W

49.9 0.5%1/16 W

49.9 0.5%1/16 W

49.9 0.5%1/16 W

49.9 0.5%1/16 W

49.9 0.5%1/16 W

R205

21 R206

21R207

21

21

21

R208

R209

R210

177185

201209

225233

170162

194186

218210

242234

179187

203211

227235

196188

220212

244236

181189

205213

229237

198190

222214

246238

183191

215207

231239

200192

216224

168 176

J5

VIO_BANK2_1

DIO_40

DIO_41

DIO_42

DIO_43

DIO_44

DIO_45

DIO_46

DIO_47

DIO_48

DIO_49

DIO_50

DIO_51

DIO_40_N

DIO_41_N

DIO_42_N

DIO_43_N

DIO_44_N

DIO_45_N

DIO_46_N

DIO_47_N

DIO_48_N

DIO_49_N

DIO_50_N

DIO_51_N

SBRIO-9651 Mating ConnectorBank 2 - 4 of 6 Symbols

VIO_BANK2_2

DIO_52

DIO_53

DIO_54

DIO_55

DIO_56

DIO_57

DIO_58

DIO_59

DIO_60_SRCC

DIO_61_MRCC

DIO_62_MRCC

DIO_63_SRCC

DIO_52_N

DIO_53_N

DIO_54_N

DIO_55_N

DIO_56_N

DIO_57_N

DIO_58_N

DIO_59_N

DIO_60_N

DIO_61_N

DIO_62_N

DIO_63_N

R22621

R227 21



Reference Schematic Design ConsiderationsTable 2-2 lists design considerations for the schematics shown in Figures 2-1 and 2-2.

Table 2-2. GBE1 Reference Schematic Design Considerations

Consideration Notes

Ethernet PHY selection

• The only PHY supported for secondary Ethernet is the Micrel Ethernet PHY, part number KSZ9031MNXIA. Refer to Table 1-4, Gigabit Ethernet Connector Parts, of Chapter 1, Fixed Behavior Signals, for information about the Gigabit Ethernet connector parts used in the sbRIO-9651 SOM development kit.

• To meet GMII timing to the sbRIO-9651 SOM, the DIO bank for the PHY (DVDDH) and VIO_BANK2 on the sbRIO-9651 SOM must be powered at 1.8 V.

• All pull-up and pull-down resistors connected to the PHY must be implemented in your carrier board design as shown in Figure 2-1. These connections ensure that the PHY is set up properly for sbRIO-9651 SOM software support.

• Refer to the datasheet for the Micrel Ethernet PHY for more information about secondary Ethernet PHY requirements.

GMII TX signals • Route the GMII TX signals directly to the Ethernet PHY.

• To meet timing requirements, the TX signals must be 1.8 V logic.

• You must place series termination resistors at the sbRIO-9651 SOM connector on the TX signals driving to the Ethernet PHY, as shown in Figure 2-2.

GMII RX signals • Connect the GMII RX signals directly to the Ethernet PHY.

• The pull resistors on the RX signals set options in the PHY when coming out of reset.

• The pull resistors must be implemented in your carrier board design as shown in Figure 2-1 to ensure that secondary Ethernet works properly. The resistors must be the same values shown in Figure 2-1.

• You must place series termination resistors near the Ethernet PHY on all RX signals, as shown in Figure 2-1.

PHY crystal selection

• NI recommends that you use a crystal with the Ethernet PHY.

• The crystal must be 25 MHz with 50 ppm or better accuracy.

• Ensure that you use suitable load capacitors for your crystal.

2-8 | ni.com


GBE1 Routing ConsiderationsNI recommends the following design practices for properly routing GBE1 signals on your carrier board:

• Length-match GMII TX signals to within ±250 mils of the GBE1_GMII_GTX_CLK signal.

• Length-match GMII RX signals to within ±250 mils of the GBE1_GMII_RX_CLK signal.

• Limit the overall length of GMII TX and RX signals to 5.0 in. or less.

• Route MDI pairs differentially with 100 Ω differential trace impedance.

• Length-match the positive and negative signal for each MDI data pair to within 10 mils.

• Limit the MDI trace lengths to 6.0 in. or less, which is the length at which Ethernet compliance was tested.

MDI data pairs • The MDI data pairs are connected directly to the Ethernet connector.

• Route the MDI data pairs differentially from the PHY to the connector.

• The Ethernet connector has magnetics built into it. You may use discrete magnetics instead.

Magnetic selection

Refer to the Gigabit Ethernet Magnetic Requirements section of Chapter 1, Fixed Behavior Signals, for information about magnetic requirements.

Ethernet speed LEDs

Refer to the Ethernet Speed LED Behavior section of the NI sbRIO-9651 System on Module OEM Device Specifications for information about Ethernet LED signal behavior and rated drive current.

Ethernet link activity LEDs

Figure 2-1 shows the logic required to create the same link activity LED behavior that the primary Ethernet signal uses.

GBE1 support signals listed in Table 2-1

Connect these signals as shown in Figure 2-1.

CARRIER_RST# The CARRIER_RST# signal should control the Ethernet PHY reset. Because the PHY has 1.8 V I/O, including the reset input, and the CARRIER_RST# signal is a 3.3 V signal, level translation is required to connect the CARRIER_RST# signal to the PHY. U13 provides this translation in Figure 2-1.

Table 2-2. GBE1 Reference Schematic Design Considerations (Continued)

Consideration Notes



Additional RS-232 (Serial2, Serial3, Serial4)You can use any FPGA pins to implement additional RS-232 ports.

The reference carrier board implements one secondary RS-232 port (Serial2) in addition to the primary UART/Console Out port. You can implement additional RS-232 ports (Serial3 and Serial4) in the same way that the Serial1 signal is implemented on the reference carrier board. Refer to the UART/Console Out (Serial1) section of Chapter 1, Fixed Behavior Signals for more information about implementing the primary UART/Console Out port.

Serial2 Signal Definitions on the Reference Carrier BoardTable 2-3 describes the Serial2 pins and signals on the sbRIO-9651 SOM connector used to implement an additional RS-232 port on the reference carrier board.

Note The NI-Serial driver has been developed for and tested with the Texas Instruments TRS3253EIRSMR RS-232 transceiver. Other transceivers may be compatible.


Signal Name Pin #*



SERIAL2_TX 66 DIO_0 O Full-modem RS-232 serial port signals.

SERIAL2_RX 69 DIO_7 I

SERIAL2_RTS# 74 DIO_1 O

SERIAL2_CTS# 76 DIO_6 I

SERIAL2_DTR# 59 DIO_2 O

SERIAL2_DSR# 83 DIO_4 I

SERIAL2_DCD# 75 DIO_3 I

SERIAL2_RI# 68 DIO_5 I

* The pin numbers listed in this table are the pins used on the reference carrier board. For your carrier board design, you can use the sbRIO CLIP Generator to configure these pins for any FPGA DIO.


Chapter 2

User-D

efined FP

GA

Signals

2-10|

ni.com

Serial2 Reference SchematicFigure 2-3 shows a schematic design for the Serial2 implementation on the reference carrier board.


SERIAL2_RTS#SERIAL2_DTR#

SERIAL2_CTS#

SERIAL2_RI#

SERIAL2_DSR#

SERIAL2_DCD#

FPGA_CFG

SERIAL2_TX_F#SERIAL2_RTS_FSERIAL2_DTR_F

SERIAL2_CD_FSERIAL2_DSR_FSERIAL2_RX_F#SERIAL2_CTS_FSERIAL2_RI_F

SERIAL2_TX

SERIAL2_RX

SERIAL2_RTS_CONN

SERIAL2_DTR_CONN

SERIAL2_RX_CONN#

SERIAL2_CTS_CONN

SERIAL2_CD_CONN

SERIAL2_SIGNAL_GND_232

SERIAL2_CD_F

SERIAL2_RX_F#

SERIAL2_TX_F#

SERIAL2_DTR_F

SERIAL2_DSR_F

SERIAL2_CTS_F

SERIAL2_RI_F

SERIAL2_RTS_F

SERIAL2_TX_CONN#

SERIAL2_RI_CONN

SERIAL2_DSR_CONN

22

2

2

2

2

2

0.1 UF 10%50 V

0.1 UF 10%50 V

21C46

1 2C48

2

1

C1750.1 UF10%16 V

30

3

26

33

27

1718192021

3224

222325

15

1011121314

168

6

928

754

2

131

29

U19

DIN1DIN2DIN3

ROUT1ROUT2ROUT3ROUT4ROUT5

C1+

C1-C2+

C2-

INVALID~

FORCEONFORCEOFF~

TRS3253EIRSMR

VL

NC1NC4NC2NC3

THERMALPAD

V-

V+

DOUT1

RIN3RIN2RIN1

VCC

GND

RIN4

DOUT2DOUT3

RIN5

1

2 C1760.1 UF10%16 V 2

1 C1710.1 UF10%16 V 2

1 C1680.1 UF10%16 V

1

2

R804.7 K0.5%1/16 W

2

1

C761800 PF50 V5%

1

2

R1474.7 K0.5%1/16 W

2,3

1

2

3

4

5

6

7

8

9

1011

J11DSUB9-761918-A

12

34

5

67

89

2

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

R108

R0805, SPARE

C0603, SPARE

C0603, SPARE

C0603, SPARE

C0603, SPARE

C0603, SPARE

C0603, SPARE

C0603, SPARE

C0603, SPARE

C0603, SPARE

21R163

21R162

21R161

21R160

21R159

21R152

21R153

21 R154

21R155

0 5%1/16W

0 5%1/16W

0 5%1/16W

0 5%1/16W

0 5%1/16W

0 5%1/16W

0 5%1/16W

0 5%1/16W

0 5%1/16W

1

2

R811 K0.5%

39 0.5%1/16W

39 0.5%1/16W

39 0.5%1/16W

39 0.5%1/16W

39 0.5%1/16W

1 2R90

1 2R88

1 2R87

1 2R84

1 2R83

+3.3V

R145SPARER0402

1

2

C841 2

1 2

1 2

1 2

1 2

1 2

1 2

C66

C65

C63

C64

C83

C82

C81

C80

0.1 UF 10%50V

C58

Caps are placedto reduce emissions.

Standard practice.120pF, 220pF, 470pF, etc

can be used

1 2

1 2

1 2

1 2




RS-485 (Serial5, Serial6)You can use any FPGA pins to implement an RS-485 port.

The reference carrier board implements one RS-485 port (Serial5). You can implement an additional RS-485 port (Serial6) in the same way that the Serial5 signal is implemented on the reference carrier board.


Consideration Notes

Interface The reference carrier board demonstrates how to use the Serial2 interface to implement a null-modem RS-232 serial port.

Serial transceiver

U19 is the RS-232 serial transceiver that converts between RS-232 and LVTTL signal levels. To minimize the impact of higher voltage signals on your carrier board, place the serial transceiver near the RS-232 connector.

Series termination

• R83, R84, R87, R88, and R90 are the series termination for Serial2. Use series termination at the serial transceiver on all signals being driven to the sbRIO-9651 SOM.

• FPGA DIO signals from DIO Bank 0 include series termination on the sbRIO-9651 SOM. Use series termination at the SEARAY connector on all signals outside of Bank 0 being driven from the sbRIO-9651 SOM to the serial transceiver.

FPGA All serial port signals pass through the FPGA on the sbRIO-9651 SOM. The FPGA_CFG signal is used to disable the serial transceiver when the FPGA is not configured. Disabling the transceiver in this way prevents any unwanted glitches on the RS-232 port.

2-12 | ni.com


Serial5 Definitions on the Reference Carrier BoardTable 2-5 describes the Serial5 pins and signals on the sbRIO-9651 SOM connector used to implement an RS-485 port on the reference carrier board.

Note The NI-Serial driver has been developed for and tested with the Analog Devices ADM2587EBRWZ Isolated RS-485 transceiver. Other isolated and non-isolated transceivers may be compatible.


Signal Name Pin #*



SERIAL5_TX 70 DIO_11 O Isolated RS-485 interface signals.

SERIAL5_TX_EN 78 DIO_12 O

SERIAL5_RX 79 DIO_14 I

SERIAL5_RX_EN 87 DIO_15_MRCC O





Serial5 Reference SchematicFigure 2-4 shows a schematic design for the Serial5 implementation on the reference carrier board.


Vcc_RS485_1

SERIAL5_TXN

SERIAL5_RX_EN

SERIAL5_TX_EN

Vcc_RS485_1

SERIAL5_RXP

SERIAL5_TXP

SERIAL5_RXN

SERIAL5_RXP

SERIAL5_RXN

SERIAL5_TXP

SERIAL5_TXN

SERIAL5_TX

SERIAL5_RX

Vcc_RS485_1

3

9

10

11

16

2

1513

12

19

8

7

4

5

20

14

1

6

17

18

U25

TranceiverDigital

Isolation iCoupler

R

D

ISO

LAT

ION

BA

RR

IER

GND2-4VISOINGND2-3

VISOOUTGND2-2

GND2-1RE~

GND1-1

VDD1-1

GND1-2

VDD1-2

GND1-3

GND1-4

TxD

DE

RxD

YZ

A

B

isoPower

2

1

R14110 K1/16 W0.5%

2

1

C1600.1 UF10%16 V1

2 C1540.1 UF10%16 V

2

1

C15910 UF10%10 V

1

2

C1610.1 UF10%16 V 2

1 C16210 UF10%10 V 2

1 C1550.1 UF10%16 V

IGND0I

IGND0I

IGND0

IIGND0

I

IGND0

I

IGND0

I

2

2

2

2

1110

9

8

7

6

5

4

3

2

1 12

67

89

35

4

J7DSUB9-761918-A

+3.3V+3.3V

+3.3V

+3.3V

21

39 0.5%1/16W

R140

2

1 C1560.01 UF10%100 V2

1 C1530.01 UF10%100 V

0.1 uF and 0.01 uFAcross pin 19 and 20

10 uF and 0.1 uFAcross pin 12 and 11

10 uF and 0.1 uFAcross pin 8 and 9

0.1 uF and 0.01 uFAcross pin 2 and 1

DC-DC Converter

ADM2587E

2-14 | ni.com


Reference Schematic Design ConsiderationsTable 2-6 lists design considerations for the schematic shown in Figure 2-4

RS-485 Layout ConsiderationsPay close attention to how the ground planes are arranged under the isolated RS-485 transceiver. Isolated and non-isolated ground planes overlap across layers to provide some capacitance between the grounds and help with EMC. Refer to the datasheet for the RS-485 transceiver for more information.

CAN (CAN0, CAN1)You can use any FPGA pins to implement a CAN interface port.

The reference carrier board implements one CAN port (CAN0). You can implement an additional CAN port (CAN1) in the same way that the CAN0 signal is implemented on the reference carrier board.


Consideration Notes

Interface The reference carrier board demonstrates how to use the Serial5 interface to implement an isolated RS-485 serial port.

Serial transceiver

U25 is the RS-485 serial transceiver that converts between RS-485 and LVTTL signal levels. This transceiver provides functional isolation of the RS-485 signals to prevent ground loops from affecting the RS-485 signals.

Series termination

• R140 is the series termination for Serial5. Use series termination at the serial transceiver on all signals being driven to the sbRIO-9651 SOM.

• FPGA DIO signals from DIO Bank 0 include series termination on the sbRIO-9651 SOM. Use series termination at the SEARAY connector on all signals outside of Bank 0 being driven from the sbRIO-9651 SOM to the serial transceiver.



CAN0 Signal Definitions on the Reference Carrier BoardTable 2-7 describes the CAN0 pins and signals on the sbRIO-9651 SOM connector used to implement a CAN interface port on the reference carrier board.

Note The NI-Embedded CAN driver has been developed for and tested with the NXP PCA82C251T/YM CAN transceiver. Other transceivers may be compatible.

Table 2-7. CAN0 Signal Definitions

Signal Name Pin #*



CAN0_TX 85 DIO_8 O Transmit line.

CAN0_RX 54 DIO_9 I Receive line.

CAN0_RS 62 DIO_10 O Slope control and standby.



2-16 | ni.com


CAN0 Reference SchematicFigure 2-5 shows a schematic design for the CAN0 implementation1 on the reference carrier board.

Figure 2-5. CAN0 Reference Schematic

1 The NXP PCA82C251T CAN transceiver requires 5 V logic levels. The reference carrier board uses external discrete buffers to translate 3.3 V FPGA lines to 5 V logic levels.

CAN0_RS_5V

CAN0_TX_5VCAN0_TX

CAN0_RS

CAN0_RX

CAN0_RX_5V_R

CAN0_CANL

CAN0_CANH

NC_RESERVED1

NC_RESERVED2

NC_RESERVED3

CAN0_RX_5V

1

2

2

1 C1210.1 UF10%16 V

2

1

2

C1170.1 UF10%16 V

C1130.1 UF10%16 V

2

16

5

4 3

U6

74LVC1T45

ABDIR

VCCB

GND

VCCA

34

5

6 1

2

U4

74LVC1T45

B A

B A

DIR

VCCB

GND

VCCA

34

5

16

2

U2

74LVC1T45

DIR

VCCB

GND

VCCA

1

2 C1300.1 UF10%16 V

2

1

C1200.1 UF10%16 V

2

1 C60.1 UF10%16 V

2

2

1

C1140.1 UF10%16 V

5

31

4

8

2

6

7

U3

PCA82C251T

GND

VCC

TXD

RXD

CANL

CANH

VREF

RS

11

10

9

8

7

6

5

4

3

2

1

1

6

2

7

3

8

45

9

J4DSUB9-761918-A

+3.3V

+3.3V +3.3V

+3.3V+3.3V

2

+5V

+5V

+5V

+5V

+5V

+5V

2

1

R1301 K0.5%

2

1

R101 K0.5%

2

1

R1321 K0.5%

2

1

R121 K0.5%

2

39 0.5%1/16 W

39 0.5%1/16 W

39 0.5%1/16 W

49.9 0.5%1/16 W

1R11

21R9

21R7

R821

0.1 UF 10%50 V

1 2C11



Reference Schematic Design ConsiderationsTable 2-8 lists design considerations for the schematic shown in Figure 2-5

Table 2-8. CAN0 Reference Schematic Design Considerations

Consideration Notes

CANx_RX, CANx_TX, and CANx_RS

• The recommended CAN transceiver requires 5 V I/O.

• U2, U4, and U6 provide level translation between the 3.3 V I/O on the sbRIO-9651 SOM and the 5 V I/O on the transceiver. Use caution when implementing this level translation.

• The TXD and RS inputs of the CAN transceiver must remain high during power-down and power-up of the sbRIO-9651 SOM and carrier board. This prevents glitches on the CAN bus that might disrupt communication between other devices on the bus. The level translator IC in this schematic prevents these glitches.

• The level translator output remains at high impedance until both of its power supply rails are powered to allow the 5 V power supply to power-up before the 3.3 V power supply.

• All signals have series termination at the outputs to prevent over- or under-shoot at the receivers.

• FPGA DIO signals from DIO Bank 0 include series termination on the sbRIO-9651 SOM. Use series termination at the SEARAY connector on all signals outside of Bank 0 being driven from the sbRIO-9651 SOM to the CAN transceiver.

CANx_CANH and CANx_CANL

• Route these signals differentially with a 120 Ω differential trace impedance.

• Minimize the overall length of the traces so that you can place termination resistors in the CAN cabling as close as possible to the CAN transceiver.

• Depending on your design requirements, you can also place the CAN termination resistor on the carrier board.

2-18 | ni.com


Termination Resistors for CAN CablesThe termination resistors should match the nominal impedance of the CAN cable and therefore comply with the values in Table 2-9.

Table 2-9. Termination Resistor Specification

Characteristic Value Condition

Termination resistor 100 Ω minimum120 Ω nominal130 Ω maximum

Minimum power dissipation: 220 mW


3Carrier Board PCB Layout Guidelines

Use the guidelines in this chapter to help you arrange the I/O signals you implement in your carrier board design.

Impedance-Controlled SignalingUse the following guidelines for implementing impedance for all I/O signals:

• All signals connected to the sbRIO-9651 SOM must use impedance-controlled traces. Refer to the sections of this document listed in Table 3-1 for information about impedance requirements.

• Trace geometry to meet impedance requirements vary depending on your specific carrier board PCB stack-up. Collaborate with your vendor to match impedance requirements, stack-up, and trace geometry appropriate for your application.

• To properly maintain trace impedance and avoid discontinuities, you cannot route traces over gaps in the reference plane. Use stitching vias and capacitors when appropriate near layer changes to provide a transient return path between reference planes.

Table 3-1. Impedance Requirements Resources

Impedance Requirement Resource

General requirements for single-ended signals

Single-Ended Signal Best Practices section of this chapter

General requirements for differential signals

Differential Signal Best Practices section of this chapter

Signal-specific requirements Signal-specific sections in Chapter 1, Fixed Behavior Signals, or Chapter 2, User-Defined FPGA Signals

3-2 | ni.com

Chapter 3 Carrier Board PCB Layout Guidelines

Single-Ended Signal Best PracticesUse the following guidelines for implementing single-ended I/O signals:

• Route all single-ended signals that are implemented on your carrier board and connected to the sbRIO-9651 SOM with 50 Ω characteristic trace impedance.

• Maintain at minimum a 2 × H line spacing between single-ended traces, where H is the distance in the board stack-up from the trace to its reference plane.

• When you configure FPGA DIO signals from DIO Bank 1, 2, or 3 as single-ended traces, observe the following guidelines:

– Use the DIO_x positive signals first because those signals have slightly lower crosstalk in the J1 connector on the sbRIO-9651 SOM than the DIO_x negative (DIO_x_N) signals.

– To minimize crosstalk when using the DIO_x_N signals, ensure that you implement corresponding positive and negative signals in the same direction. For example, if you are using DIO_16 and DIO_16_N, implement both signals as inputs or both as outputs. Avoid implementing one as an input and the other as an output.

– To improve signal integrity on the carrier board, place series termination resistors on outputs from the sbRIO-9651 SOM as close to the mating connector as possible.

Note FPGA DIO signals from DIO Bank 0 include series termination resistors near the Xilinx Zynq SoC on the sbRIO-9651 SOM. Refer to the FPGA DIO section of the NI sbRIO-9651 System on Module OEM Device Specifications for more information.

Differential Signal Best PracticesUse the following guidelines for implementing differential I/O signals:

• Route all differential signals that are implemented on your carrier board and connected to the sbRIO-9651 SOM—other than USB data pair signals—with 100 Ω differential trace impedance. Route USB data pair signals with 90 Ω differential trace impedance.

• Maintain at minimum a 3 × H spacing between differential pairs and any other copper features on the same layer, where H is the distance in the board stack-up from the trace to its reference plane.



Ground and Power Plane RecommendationsUse the following guidelines for implementing ground and power planes:

• You must include ground planes on your carrier board. All GND pins on the J1 connector of the sbRIO-9651 SOM must connect to the carrier board ground planes.

• If possible, use planes to connect power to the sbRIO-9651 SOM. All power pins on the J1 connector of the sbRIO-9651 SOM must be connected and powered, even if a bank of DIO is unused.

Fanout and Layout OptionsRefer to Samtec SEARAY documentation for information about possible fanout and layout options with various layer count carrier boards.


4Mechanical Considerations

Proper mechanical design is critical for rugged environments in which the sbRIO-9651 SOM may be subjected to extreme temperatures, shock, vibration, and other factors. In particular, pay special attention to thermal performance to ensure that your application meets the sbRIO-9651 SOM operating requirements.

MountingYou can mount the sbRIO-9651 SOM and carrier board in a variety of ways in order to maximize system performance. Some mounting methods might require custom fasteners or unique assembly techniques to maintain required connector stack heights and enable improved thermal and structural design for rugged environments.

Selecting an Appropriate Mating ConnectorThe J1 connector on the sbRIO-9651 SOM is a Molex 45971-4185 320-pin, 8 × 40 position, SEARAY open-pin-field-array connector. To interface with the J1 connector, your carrier board design must implement a mating connector that is compatible with the Molex 45971 series or Samtec SEAF series. Table 4-1 lists compatible mating connectors, such as the Molex 45970 series or Samtec SEAM series.

Table 4-1. sbRIO-9651 SOM Connector and Compatible Mating Connectors

Connector Manufacturer, Part Number

sbRIO-9651 SOM J1 connector Molex, 45971-4185 (equivalent to Samtec SEAF-40-05.0-S-08-2-A-K-TR)

Recommended mating connector* Molex, 45970-4130

Alternative 7-mm stack height mating connectors

Molex, 45970-4185

Samtec, SEAM-40-02.0-S-08-2-A-K-TR

* Compatible connectors are available in multiple stack height and termination options. NI has secured a special Molex connector part number, 45970-4130, with a 7-mm mated pair stack height. Refer to the Ordering the Recommended Mating Connector section of this chapter for information about ordering connectors. Consult Molex or Samtec for alternative stack heights and terminations.

4-2 | ni.com

Chapter 4 Mechanical Considerations

Ordering the Recommended Mating ConnectorThe recommended mating connector is distributed through TTI, Inc. at NI-negotiated pricing and with shortened lead times. Complete the following steps to order individual bulk or reel quantities of the mating connector.

1. Visit www.ttiinc.com.

2. Search for the 45970-4130 part number. Table 4-2 describes the available parts.

3. Contact TTI, Inc. directly and request NI pricing when obtaining a quote. You may also be able to place an order directly from the TTI, Inc. website.

Note These recommended connectors are available only from TTI, Inc. distribution centers located in the United States but can be shipped internationally. Customers outside the U.S. should contact a U.S.-based distribution center and request international shipping.

Note Online pricing might not reflect negotiated pricing.

Selecting Appropriate StandoffsThe Molex 45970 series and Samtec SEAM series connectors are available in multiple heights. The height of the mating connector you select determines the height of the standoffs you need.

To prevent over-insertion, the SEARAY connector design requires that standoffs never be less than the stack height. Because standard nominal tolerances might result in a standoff being shorter than the stack height, NI requires that you use standoffs that are 0.15 mm (0.006 in.) taller than the combined height of the J1 connector on the sbRIO-9651 SOM and the mating SEARAY connector. Therefore, to determine the required standoff height, you must add the heights of the mated connectors plus an additional 0.15 mm (0.006 in.). Refer to Samtec documentation for more information about SEARAY standoff requirements.

Table 4-2. Orderable Mating Connector Parts from TTI, Inc.

Part Number Description

45970-4130 A packaged reel of 300 connectors.

45970-4130 BULK One or more individual connectors.

http://www.ttiinc.com/



Table 4-3 provides an example standoff height calculation using a Molex 45970-4130 mating connector.

NI Custom StandoffsNI offers a custom standoff that is an exact fit with the recommended or other compatible 7-mm stack height mating connectors listed in Table 4-1. This custom M3 × 7.15 mm (0.281 in.) is made from 4.5 mm (0.177 in.) stainless steel hex stock and includes a nylon threadlock patch. The external threads extend 4.78 mm (0.188 in.) and the internal threads are 5 mm (0.197 in.) deep. Table 4-4 lists orderable quantities of this custom standoff.

NI recommends that you use stainless steel fasteners for good corrosion resistance and strength. Tighten M3 fasteners to a torque of 0.76 N · m (6.70 lb · in), unless otherwise noted or required by your specific design constraints.

Table 4-3. Example Connector Configuration and Calculated Standoff Height

ComponentManufacturer, Part Number Height

J1 connector on the sbRIO-9651 SOM Molex, 45971-4185 5.00 mm (0.197 in.)

Mating connector Molex, 45970-4130 2.00 mm (0.079 in.)

Required additional standoff height — 0.15 mm (0.006 in.)

Total calculated standoff height — 7.15 mm (0.281 in.)

Table 4-4. Custom M3 × 7.15 mm (0.281 in.) Standoff Kits

Quantity Manufacturer, Part Number

20 NI, 157543-020

500 NI, 157543-500

4-4 | ni.com


Mounting Direction OptionsFigures 4-1 through 4-3 show possible mounting configurations and associated fastener types.

Mounting on a Panel or Plate (Recommended)If possible, NI recommends that you mount the sbRIO-9651 SOM on a panel or plate, as shown in Figure 4-1.

Figure 4-1. Mounting on a Panel or Plate

The sbRIO-9651 SOM was designed so that you can use the 15.00 mm (0.591 in.) standoffs between the carrier board and the base panel when the 7.15 mm (0.281 in.) standoffs are used between the carrier board and the sbRIO-9651 SOM, as shown in Figure 4-1.

1 Exploded view of all mounting components2 Complete assembled and mounted view3 Standoff, 15.00 mm (0.591 in.)4 Carrier board

5 Mounting surface6 Mounting screw, panel thickness +

12.00 mm (0.472 in.)7 sbRIO-9651 SOM8 Standoff, 7.15 mm (0.281 in.)

1 2

8

3

6

4

5

7



This method accommodates a layer of thermal grease that is 0.08 mm (0.003 in.) thick between the aluminum heat spreader of the sbRIO-9651 SOM and the metal base panel. However, thicker thermal interface materials may require different lengths of standoffs or mounting bosses. The direction of fastening may also require custom lengths or types of fasteners and might impact ease of assembly.

Mounting on a Panel or Plate with Flathead ScrewsAlternatively, use flathead screws when mounting on a panel or plate, as shown in Figure 4-2.

Figure 4-2. Mounting on a Panel or Plate with Flathead Screws

Mounting on a Panel or Plate with an Attached Heat SinkYour system design might require you to attach a heat sink or other thermal solution described in the Mounting Recommendations for Maximizing Thermal Performance section of this chapter. Figure 4-3 shows standoffs and fasteners that are compatible with the AlphaNovatech S01LZZ0E-A heat sink that is included in the sbRIO-9651 SOM development kit.

1 Exploded view of all mounting components2 Complete assembled and mounted view3 Mounting surface4 Carrier board

5 Mounting screw, 12.00 mm (0.472 in.)6 Standoff, 7.15 mm (0.281 in.)7 sbRIO-9651 SOM

1 2

5

6

3

4

7

4-6 | ni.com


Figure 4-3. Mounting on a Panel or Plate with an Attached Heat Sink

Managing Thermal ConditionsDue to the compact size of the sbRIO-9651 SOM, it is very important to appropriately dissipate the heat generated during operation. You must plan for the thermal conditions of your application throughout development and validation. This section provides design recommendations and validation tools and methods for maximizing the thermal performance of the system.

Designing a Suitable EnclosureNI sbRIO devices operate as components in a higher-level system and may require an enclosure to protect the internal circuit card assembles and dissipate heat. For the sbRIO-9651 SOM, the system integrator is responsible for designing an enclosure that meets the thermal requirements of your specific application.

1 Exploded view of all mounting components2 Complete assembled and mounted view3 Mounting surface4 Carrier board

5 Standoff, 7.15 mm (0.281 in.)6 sbRIO-9651 SOM7 Mounting screw, 16.00 mm (0.630 in.)

1 2

75

3

4

6



NI sbRIO devices integrated into an enclosure or system with proper thermal dissipation can be deployed in high- and low-temperature environments. However, the 85 °C local ambient operating temperature rating of the sbRIO-9651 SOM does not mean that the external temperature of the natural convection environment such as a room or larger enclosure can be 85 °C. In this way, properly designed NI sbRIO devices may still require an external ambient temperature of 70 °C or less and may still require specific mounting requirements to ensure that the local ambient and thermally-relevant component maximum operating temperatures are within specification.

Understanding Thermal SpecificationsA deployed system has several temperature measurement locations that indicate the thermal performance of the system and the devices the system contains. For example, in a natural convection system, the temperature of a critical component will be higher than the temperature of the air in the immediate vicinity of the component. This local air temperature will also be higher inside an enclosure than in the room ambient that surrounds the enclosure.

Figure 4-4 identifies these types of ambient temperatures.

Figure 4-4. Ambient Temperatures

1 External ambient temperature2 Internal/enclosure ambient temperature3 Carrier board

4 sbRIO-9651 SOM5 Local ambient temperature6 Enclosure

4 5

21

6

3

4-8 | ni.com


• External ambient—The maximum air temperature of the room or installation location that surrounds the system.

• Internal/enclosure ambient—The maximum air temperature inside the enclosure. This can be measured at various locations within the enclosure and is highly influenced by the proximity and dissipation of devices inside the enclosure.

• Local ambient—The maximum air temperature as specified directly adjacent to the NI sbRIO device. This is measured on all sides of a device that has exposed circuitry. Because the sbRIO-9651 SOM has an integrated heat spreader on the primary side, only the secondary side needs to be measured.

Because the system integrator may use any number of enclosure sizes, materials, thermal solutions, and room conditions when designing an enclosure for a specific application, NI sbRIO devices are specified in a manner that removes most of these external variables. Therefore, the sbRIO-9651 SOM thermal performance is not determined by measuring the external ambient or internal/enclosure ambient temperatures, but by measuring the local ambient and specific component temperatures. NI provides digitally reported temperatures to help you accurately measure these critical temperatures.

Validating the SystemNI recommends that you use a validation system for an extended period of time in a test environment with the same thermal, environmental, and functional utilization characteristics as the target deployment environment. You are responsible for final validation of your application.

Validating Temperature MeasurementsThe sbRIO-9651 SOM includes three onboard temperature-monitoring sensors to simplify validation of a thermal solution, as shown in Figure 4-5. The sensors provide an indication of thermal performance and are used to validate the system along with the local ambient operating temperature.



Figure 4-5. Onboard Temperature-Monitoring Sensors

• CPU/FPGA sensor—Digitally reports the die junction temperature of the Xilinx Zynq SoC.

• Primary System sensor—Digitally reports the temperature on the Xilinx Zynq SoC side of the circuit card assembly underneath the integrated heat spreader. This value is an approximation of the local ambient temperature inside the heat spreader.

• Secondary System sensor—Digitally reports the temperature on the SEARAY side of the circuit card assembly. This value is a conservative approximation of the local ambient temperature on that side of the circuit card assembly.

To meet the thermal specifications described in the NI sbRIO-9651 System on Module OEM Device Specifications, you must record the following measurements:

• The CPU/FPGA reported temperature, which must not exceed 98 °C

• The Primary System reported temperature, which must not exceed 85 °C

• The local ambient operating temperature near the device, which must not exceed 85 °C

Measure the local ambient temperature by placing a thermocouple near the center of the printed circuit board 5 mm (0.2 in.) from the board surface. Alternatively, you can rely on the reported Secondary System temperature to provide a conservative estimate of the local ambient

1 CPU/FPGA sensor 2 Primary System sensor 3 Secondary System sensor

3

1

2

4-10 | ni.com


temperature. This alternative method provides a completely digital validation scheme that does not require using a thermocouple and allows you to validate the sbRIO-9651 SOM as part of every deployment.

In addition to being useful for system validation, digitally reported temperatures also provide feedback about system health and can be used as triggers or set points. The TEMP_ALERT signal from the J1 connector on the sbRIO-9651 SOM asserts when the CPU/FPGA or Primary System reported temperatures exceed specification. However, you should not use the TEMP_ALERT signal in place of proper system validation because the TEMP_ALERT signal does not monitor the Secondary System or local ambient temperatures. Refer to the Temp Alert section of Chapter 1, Fixed Behavior Signals, for more information about the TEMP_ALERT signal.

NI recommends that you monitor the digitally reported temperatures on deployed systems, especially if the temperatures approach the maximum thermal specifications during system validation testing. Monitoring allows individual systems to identify adverse thermal changes caused by differences in environmental, operating, or process conditions.

For more information about how to access and use the digitally reported temperature sensor measurements, visit ni.com/info and enter the Info Code sbriosensors.

Managing Power and Feature UtilizationAn sbRIO-9651 SOM that heavily utilizes all of its performance and features consumes and dissipates substantially more power than when the device is idle. Certain features, such as LVDS outputs, can greatly increase the power that the Xilinx Zynq SoC dissipates and therefore also quickly raise the die junction temperature.

Consider the following options for reducing the die junction temperature:

• Design for additional thermal cooling that can appropriately dissipate power

• Reduce device feature utilization

Note Your final validation must consider software and hardware utilization that is representative of the final deployment conditions.

Note Refer to the Input Power Requirements section of the NI sbRIO-9651 System on Module OEM Device Specifications for specifications that approximate the maximum power requirement for each input rail on an sbRIO-9651 SOM with worst-case silicon manufacturing process and maximum junction temperatures. For a more accurate estimate of the power consumption for a specific application, NI recommends that you directly measure the power the sbRIO-9651 SOM consumes when running your application in an environment that is representative of the intended use case. You can use the Xilinx Power Estimator to calculate the VIO_BANK input rail power for a given configuration.



Mounting Recommendations for Maximizing Thermal PerformanceThe sbRIO-9651 SOM includes an integrated heat spreader that uses a thermal gap filler material to effectively conduct into the spreader the heat that the circuit card assembly components generate. NI recommends the following mounting procedures for maximizing the thermal performance of your application:

• Directly mount the flat and smooth exterior surface of the integrated heat spreader to a thermally-conductive surface, such as a metal enclosure wall or plate, as shown in Figure 4-1. An interface material such as thermal grease should be used to maximize the heat transfer from the integrated heat spreader to the enclosure or plate. The enclosure or plate conducts and convects the heat to the external ambient environment.

If design limitations prevent this solution, you can alternatively attach a heat sink or other thermal solution to the integrated heat spreader, as shown in Figure 4-3. This solution takes advantage of natural convection or forced convection cooling provided by a fan.

• Mount the sbRIO-9651 SOM vertically with respect gravity to take advantage of natural convection cooling.

• Mount the sbRIO-9651 SOM below and away from other heat-dissipating components.

Note Placing the sbRIO-9651 SOM within a system or enclosure will also influence thermal performance.

Figure 4-6 shows good, better, and best thermal mounting solutions for the sbRIO-9651 SOM.

Figure 4-6. Thermal Mounting Solutions Comparison

1 Good—Horizontal mounting with no additional thermal provisions2 Better—Vertical mounting with an attached heat sink, as described in Figure 4-33 Best—Vertical mounting directly to a thermally-conductive wall or plate, as described in Figure 4-1

1 2 3

4-12 | ni.com


Additional Resources for Managing Thermal ConditionsVisit ni.com/info and enter the Info Code sbriocooling for the following additional information to help you manage thermal conditions:

• Examples regarding the effect of the design factors discussed in this chapter

• Case study examples to help you estimate the achievable external ambient temperature for a representative system

Shock and VibrationThe mounting method you use, components you select, and assembly techniques you use influence the ability of the system to resist fretting corrosion and other damage caused by exposure to shock and vibration. Consider the following factors when designing your sbRIO-9651 SOM system to account for shock and vibration:

• In general, shorter SEARAY stack heights perform better than taller stack heights.

• Directly mounting the sbRIO-9651 SOM heat spreader to a rigid surface provides the best performance. If this method is not feasible for your design, minimize the amount of extra mass that only the sbRIO-9651 SOM supports, such as a heat sink or other thermal solution, that is fastened to the four standoffs. If you require substantial thermal solutions, provide additional structural support.

• NI recommends that you use connectors that provide the following benefits:

– Positive locking

– Provisions for strain relief

– Substantial gold plating on pins

• The connectors on the reference carrier board are representative of connectors that NI has used and validated for high shock and vibration environments. The connectors and the sbRIO-9651 SOM have been tested to industry specifications and are recommended, where possible, for rugged environments.

Exceptions to this recommendation are the barrel jack and Peripheral Module (Pmod) headers, which have designs that are not positive-locking or do not provide strain relief.

• NI offers a variety of cable assemblies and other connectivity accessories to complete your system design. Typically, these accessories include the best available designs, materials, and plating to maximize performance and longevity in rugged environments.

© National Instruments | A-1

AReference Carrier Board Specifications and User Guide

This appendix provides pinouts, connectivity information, and specifications for the reference carrier board included with the sbRIO-9651 SOM development kit.

The reference carrier board provides the following:

• A hardware environment for developing and evaluating designs that target the sbRIO-9651 SOM.

• Access to most of the onboard peripherals available on the sbRIO-9651 SOM, including Ethernet, serial RS-232 and RS-485, USB Device, USB Host, SD card, and FPGA I/O.

• Additional supported capability through five Pmod connectors on the breadboard circuit prototyping area.

Note Visit ni.com and search for 9651 for the reference carrier board schematic and PCB gerber files.

Parts Locator Diagram and Block DiagramRefer to the NI sbRIO-9651 System on Module Development Kit Quick Start Guide for the reference carrier board parts locator diagram and hardware block diagram.

SpecificationsThe following specifications are typical and not guaranteed.

Note Refer to the NI sbRIO-9651 System on Module OEM Device Specifications for complete specifications for each interface the sbRIO-9651 SOM supports. The specifications listed in this section pertain only to the interfaces implemented on the reference carrier board.

A-2 | ni.com

Appendix A Reference Carrier Board Specifications and User Guide

EthernetThe reference carrier board includes the following tri-mode Ethernet ports:

• Ethernet0—Utilizes the primary Ethernet (GBE0) fixed behavior interface from the sbRIO-9651 SOM.

• Ethernet1—Implemented from the secondary Ethernet user-defined FPGA interface.

Serial

Number of ports

TX/RX-only RS-232 1 (Serial1)

Full-modem RS-232 1 (Serial2)

RS-485 1 (Serial5)

CAN

Number of CAN ports 1 (CAN0)

SD Card

Number of full-size SD card sockets 1 (J2)

Refer to SanDisk Corporation or SD Association websites for information about SD I/O card specifications.

USB

Number of ports

USB Device 1 (USB0)

USB Host 1 (USB1)

USB Host maximum current 900 mA (supports USB3 Vision cameras)

PmodThe Pmod standard is defined by Digilent, Inc. and is used for small I/O interface boards that extend the capabilities of FPGA control boards. Pmods communicate with system boards via 6- or 12-pin connectors. The reference carrier board provides Pmod-compatible connectors to support quick connectivity to the Pmod ecosystem for prototyping and evaluating sensors, converters, connectors, and other devices.



Note Refer to the Digilent website at www.digilentinc.com for more information about Pmods.

Number of ports

Pmod 12-pin 4 (Pmod1, Pmod2, Pmod3, Pmod4)

Pmod I2C 1 (Pmod5)

Pmod Vcc

Voltage 3.3 V

Current 100 mA

Pmod Signal Definitions on the Reference Carrier BoardTable A-1 describes the pins and signals on the sbRIO-9651 SOM connector used to implement four Pmod 12-pin connectors.

Note Refer to the Pmod 12-Pin Connector Pinout section of this chapter for more information about the Pmod 12-pin connector pins and signals on the reference carrier board.

Table A-1. Pmod 12-pin Connector Signal Definitions

Signal Name* Pin # DIO Signal Signal Name* Pin # DIO Signal

PMOD1_PIN1PMOD1_PIN2PMOD1_PIN3PMOD1_PIN4PMOD1_PIN7PMOD1_PIN8PMOD1_PIN9PMOD1_PIN10

11490

12298

138146153161

DIO_20_NDIO_19_NDIO_20DIO_19DIO_21_NDIO_21DIO_18DIO_18_N


164131172139107155115163

DIO_28_NDIO_23DIO_28DIO_23_NDIO_22DIO_24DIO_22_NDIO_24_N


14811614012492

109100117

DIO_27DIO_26_NDIO_27_NDIO_26DIO_25_NDIO_29DIO_25DIO_29_N


135111143119159167142150

DIO_37_MRCCDIO_36_SRCCDIO_37_NDIO_36_NDIO_38_MRCCDIO_38_NDIO_34_NDIO_34

* All signals have both I/O directions and comply with the LVTTL I/O standard.

A-4 | ni.com


Table A-2 describes the specific pins and signals on the sbRIO-9651 SOM connector used to implement a Pmod I2C connector.

Note Refer to the Pmod I2C Connector Pinout section of this chapter for more information about the Pmod I2C connector pins and signals on the reference carrier board.

RTC BatteryThe reference carrier board provides a battery backup for the RTC on the sbRIO-9651 SOM.

Support SignalsThe reference carrier board implements support signals in the following ways:

• STATUS_LED and TEMP_ALERT signals are routed to user-visible LEDs.

• SYS_RST# is connected to a Reset push button.

Connector Pinouts

RS-232, RS-485, and CAN Connector PinoutsThe RS-232, RS-485, and CAN connectors on the reference carrier board use the port shown in Figure A-1. Table A-3 describes the pins and signals on each port.

Figure A-1. RS-232, RS-485, and CAN Port Pin Locations

Table A-2. Pmod I2C Connector Signal Definitions

Signal Name* Pin # DIO Signal

PMOD_I2C_SCL1PMOD_I2C_SCL2

105129

DIO_16DIO_17

PMOD_I2C_SDA1PMOD_I2C_SDA2

113137

DIO_16_NDIO_17_N

* All signals have both I/O directions and comply with the LVTTL I/O standard.

Pin 1

Pin 5

Pin 6

Pin 9



Pmod 12-Pin Connector PinoutThe Pmod 12-pin connectors on the reference carrier board use the port shown in Figure A-2. Table A-4 describes the pins and signals on the port.

Figure A-2. Pmod 12-Pin Port Pin Locations

Table A-3. RS-232, RS-485, and CAN Port Pins and Signals

TX/RX-only RS-232

Full-modem RS-232 RS-485 CAN

Pin Signal Pin Signal Pin Signal Pin Signal

1 NC 1 DCD 1 GND 1 NC

2 RXD 2 RXD 2 NC 2 CANL

3 TXD 3 TXD 3 NC 3 GND

4 NC 4 DTR 4 RXP 4 NC

5 GND 5 GND 5 RXN 5 SHIELD

6 NC 6 DSR 6 NC 6 GND

7 NC 7 RTS 7 NC 7 CANH

8 NC 8 CTS 8 TXP 8 NC

9 NC 9 RI 9 TXN 9 NC

Table A-4. Pmod 12-Pin Port Pins and Signals

Pin Signal Pin Signal

1 PMODx_PIN1 7 PMODx_PIN7




5 GND 11 GND

6 3.3 V power 12 3.3 V power

16

12

2345

891011 7

A-6 | ni.com


Pmod I2C Connector PinoutThe Pmod I2C connector on the reference carrier board uses the port shown in Figure A-3. Table A-5 describes the pins and signals on the port.

Figure A-3. Pmod I2C Port Pin Locations

Environmental ManagementNI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.

For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.

Waste Electrical and Electronic Equipment (WEEE)EU Customers At the end of the product life cycle, all products must be sent to a WEEE recycling center. For more information about WEEE recycling centers, National Instruments WEEE initiatives, and compliance with WEEE Directive 2002/96/EC on Waste and Electronic Equipment, visit ni.com/environment/weee.

Battery Replacement and DisposalBattery Directive This device contains a long-life coin cell battery. If you need to replace it, use the Return Material Authorization (RMA) process or contact an authorized National Instruments service representative. For more information about compliance with the EU Battery Directives 2006/66/EC about Batteries and Accumulators and Waste Batteries and Accumulators, visit ni.com/environment/batterydirective.

Table A-5. Pmod I2C Port Pins and Signals

Pin Signal Pin Signal

1 PMOD5_SCL1 5 GND

2 PMOD5_SCL2 6 GND

3 PMOD5_SDA1 7 3.3 V power

4 PMOD5_SDA2 8 3.3 V power

1

2 864

753

Cd/Hg/Pb



RoHSNational Instruments

(RoHS) National Instruments RoHS ni.com/environment/rohs_china (For information about China RoHS compliance, go to ni.com/environment/rohs_china.)

© National Instruments | B-1

BRevision History

Table B-1 lists changes to this document since its first iteration.

Table B-1.

Revision Edition Date Changes

B August 2015 • Added information about eliminating the effects of contact bounce to the Eliminating the Effects of Contact Bounce section of Chapter 1, Fixed Behavior Signals.

• Added more information about ordering the recommended mating connector (Molex, 45970-4130) from TTI, Inc. to the Ordering the Recommended Mating Connector section of Chapter 4, Mechanical Considerations.

A December 2014 —

© National Instruments | C-1

CNI Services

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To get started, register your product at ni.com/myproducts.

As a registered NI product user, you are entitled to the following benefits:

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Log in to your National Instruments ni.com User Profile to get personalized access to your services.

Services and Resources

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is extendable up to five years. NI offers repair services performed in a timely manner by highly trained factory technicians using only original parts at a National Instruments service center.

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http://www.ni.com/myproducts

http://www.ni.com

http://www.ni.com/services


http://www.ni.com/calibration

http://www.ni.com/alliance

C-2 | ni.com

Appendix C NI Services

• Training and Certification—The NI training and certification program is the most effective way to increase application development proficiency and productivity. Visit ni.com/training for more information.

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– Software Support Service Membership—The Standard Service Program (SSP) is a renewable one-year subscription included with almost every NI software product, including NI Developer Suite. This program entitles members to direct access to NI Applications Engineers through phone and email for one-to-one technical support, as well as exclusive access to online training modules at ni.com/self-paced-training. NI also offers flexible extended contract options that guarantee your SSP benefits are available without interruption for as long as you need them. Visit ni.com/ssp for more information.

• Declaration of Conformity (DoC)—A DoC is our claim of compliance with the Council of the European Communities using the manufacturer’s declaration of conformity. This system affords the user protection for electromagnetic compatibility (EMC) and product safety. You can obtain the DoC for your product by visiting ni.com/certification.

For information about other technical support options in your area, visit ni.com/services, or contact your local office at ni.com/contact.

You also can visit the Worldwide Offices section of ni.com/niglobal to access the branch office websites, which provide up-to-date contact information, support phone numbers, email addresses, and current events.

http://www.ni.com/training

http://www.ni.com/skills-guide

http://www.ni.com/skills-guide

http://www.ni.com/support

http://www.ni.com/support

http://www.ni.com/forums

http://www.ni.com/self-paced-training

http://www.ni.com/self-paced-training

http://www.ni.com/ssp

http://www.ni.com/certification


http://www.ni.com/contact

http://www.ni.com/niglobal

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