DESIGN EXAMPLE REPORT · Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 2 Scope This...

Power Integrations

5245 Hellyer Avenue, San Jose, CA 95138 USA. Tel: +1 408 414 9200 Fax: +1 408 414 9201

www.powerint.com

DESIGN EXAMPLE REPORT

Title 20 W Power Supply with Very Low No-load Power Consumption Using TOP255PN

Specification 85 – 265 VAC Input; 12 V, 1.67 A Output

Application Various

Author Applications Engineering Department

Document number

DER-188

Date September 30, 2008

Revision 1.0

Summary and Features

• Very low no-load consumption: <100 mW at 230 VAC

• High active-on average efficiency: 85% / 86% at 115 VAC / 230 VAC

• Exceeds ENERGY STAR 2.0 efficiency requirement of 81%

• High available standby output power at 115 VAC / 230 VAC:

• 0.75 W at 1.0 W input power



• Line sensing

• Line feed-forward for excellent line ripple rejection

• Intelligent brown-out protection (undervoltage lockout (UVLO), with auto-restart)

• Extended line surge immunity (overvoltage shutdown)

• No heat sink necessary, by design

• Hysteretic thermal over load and output short-circuit protection PATENT INFORMATION

The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered

by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A

complete list of Power Integrations' patents may be found at www.powerint.com. Power Integrations grants its customers a license under

certain patent rights as set forth at <http://www.powerint.com/ip.htm>.

DER-188 – Generic 12 V, 20 W TOPSwitch-HX Low No-load Input Power Design 30-Sep-08

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Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com

Table of Contents 1 Introduction.................................................................................................................3

2 Scope .........................................................................................................................4

3 Power Supply Specification ........................................................................................5

4 Schematic...................................................................................................................6

5 Circuit Description ......................................................................................................7

5.1 TOP255PN Operation .........................................................................................7

5.2 Input Filtering.......................................................................................................7

5.3 TOP255PN Primary.............................................................................................7

5.4 TOP255PN Secondary........................................................................................9

5.5 Output Rectification and Filtering ........................................................................9

6 PCB Layout ..............................................................................................................10

7 Bill of Materials .........................................................................................................11

8 Transformer Details ..................................................................................................12

8.1 Electrical and Mechanical Diagram ...................................................................12

8.2 Electrical Specifications.....................................................................................12

8.3 Materials............................................................................................................12

8.4 Build Diagram....................................................................................................13

8.5 Transformer Construction..................................................................................13

9 Design Spreadsheet .................................................................................................14

10 Power Supply Performance ..................................................................................18

10.1 Energy Efficiency...............................................................................................18

10.2 Output Regulation and Quality ..........................................................................21

10.3 Transient Load ..................................................................................................24

10.4 Startup...............................................................................................................25

11 Conducted EMI .....................................................................................................26

11.1 Waveform Plots .................................................................................................27

12 Revision History ....................................................................................................29

Important Note: Although this board is designed to satisfy safety isolation requirements, the engineering prototype has not been agency approved. Therefore, all testing should be performed using an isolation transformer to provide the AC input to the prototype board.

30-Sep-08 DER-188 – Generic 12 V, 20 W TOPSwitch-HX Low No-load Input Power Design

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Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201

www.powerint.com

1 Introduction

This engineering report describes a generic universal input, 12 V, 20 W output power supply employing the Power Integrations® TOPSwitch®-HX integrated off-line switcher TOP255PN. This power supply provides very low no-load power consumption and excellent standby efficiency.

Figure 1 – Populated Circuit Board Photograph.

This document contains the specifications, schematic, bill of materials, transformer construction details, and performance data for designing this power supply. This document also includes design considerations specific to addressing low no-load power consumption.


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2 Scope

This report focuses on energy efficiency with special considerations given to the no-load input power consumption of this design. Performance test data is contained in this report with the exception of thermal tests. The conducted EMI test results suggest radiated EMI would be passed without significant additional work.

The following calibrated test equipment was used in gathering data for this report:

• Power meter Yokogawa WT210

• Programmable AC source Chroma model # 61502

• Programmable DC load Chroma model # 6314/63103

• Digital Storage Oscilloscope Yokogawa DL1740

• Current probe Tektronix A6302 and current probe amplifier Tektronix AM503

• Voltage probe 10:1 Tektronix P6105A

• DMM Fluke 87

• EMI test receiver Rhode & Schwarz ESPC

• Two-line V-Network Rhode & Schwarz ESH 3-Z5


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3 Power Supply Specification Description Min. Typ. Max. Peak Unit Notes

Input

Voltage 85 115/230 265 VAC

Frequency 47 50 63 Hz

2 wire input

Output

Output Voltage 11.4 12.0 12.6 V ±5%

Output Voltage Ripple 120 mVpp 1%, 20 MHz bandwidth

Output Current 0 1.67 A

Total Output Power 0 20 W

Energy Efficiency

Full load efficiency 81% 84% Measured at 20 W, +25 °C

Average active-on 81% 84% 25%, 50%, 75%, 100% at 115/230 VAC per ENERGY STAR 2.0 (March 6, 2008)

Standby output power 0.70 0.75 W At 1.0 W input power

0.30 0.35 W At 0.50 W input power

0.15 0.20 W At 0.30 W input power

No-load consumption 0.08 0.1 W At 230 VAC

Environmental

Conducted EMI Meets EN 55022 Class B

Safety Designed to meet EN 60950, Class II

Ambient Temperature 0 +50 °C Free convection, sea level

Table 1 – Power Supply Specification.


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4 Schematic

Figure 2 – Power Supply Schematic.


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5 Circuit Description

This design centers around the TOP255PN in a flyback topology for a very low no-load power supply operating from universal inputs and providing a 12 V, 20 W output.

5.1 TOP255PN Operation

The TOP255PN (U1) converts a current at the CONTROL pin to a duty cycle at the open drain output of its integrated, high-power MOSFET. IC U1 also provides high-voltage start-up, cycle-by-cycle current limiting, loop compensation circuitry, and auto-restart and thermal shutdown. The high-voltage (700 V) MOSFET and all low-voltage control circuitry are cost-effectively integrated onto a single monolithic IC. IC U1 uses the Multi-function (M) pin to combine the features normally requiring several pins onto one. The M pin acts as the single input for line overvoltage (OV), line under-voltage (UV), line feed-forward with DCMAX reduction, output overvoltage protection (OVP), external current-limit adjustment, remote ON/OFF, and device reset functions. In this design only the UV, OV and DCMAX reduction features are used, via R3 and R4. During normal MOSFET operation, duty cycle decreases linearly with increasing C-pin current. See Figure 9 in the TOPSwitch-HX data sheet for details. Capacitor C6 is the decoupling capacitor for U1. Capacitor C5 both sets the auto-restart timing and, with R6, provides control loop compensation.

5.2 Input Filtering

Fuse F1 provides catastrophic fault protection to the circuit, and isolates it from the AC source. X-capacitor C1 reduces differential-mode EMI. Y-capacitor C7 (across the isolation barrier) and common-mode inductor L1 filter common-mode EMI. The value of C1 is sufficiently low to allow safe removal of the AC source without bleed resistors, in compliance with UL standard 60950-1. Diodes D1 through D4 rectify the AC input. Capacitor C2 filters the resulting DC.

5.3 TOP255PN Primary

A clamp network formed by VR1, R9, C3, R8, and D5 protects U1 from voltage spikes caused by leakage inductance on the transformer primary side at MOSFET turn off. Resistors R3 and R4 sense the DC bus voltage to provide line feed-forward information (for improved line ripple rejection), set the UVLO startup voltage threshold (intelligent brown-out protection), and provide extended line surge immunity via the OV shutdown feature.


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The current fed from the DC bus into U1’s M pin is proportional to the DC voltage across capacitor C2. When this voltage reaches approximately 95 V DC, the current through this resistor becomes greater than 25 µA. This causes the line under-voltage threshold to be exceeded, enabling U1. Resistors R3 and R4 are rated for ¼ W each to withstand the DC voltage expected across them. The TOPSwitch HX regulates the output using PWM-based voltage-mode control. At high loads the controller operates at full switching frequency (66 kHz for this design). Changes in the CONTROL pin current cause changes to the duty cycle. This regulates the output voltage. The internal current limit provides cycle-by-cycle peak current limit protection. The integrated controller has a second current limit comparator for monitoring the actual peak drain current (IP) relative to the programmed current limit ILIMITEXT. When the ratio IP/ILIMITEXT falls below 55%, the peak drain current is held constant and the TOPSwitch operates in a fixed duty cycle variable frequency mode (variable frequency PWM control mode). As the load continues to decrease, the switching frequency also decreases linearly down to 30 kHz. Once the switching frequency drops to 30 kHz, the controller keeps it constant and reduces the peak current to regulate the output (reverting to a fixed frequency, direct duty-cycle PWM control mode). As the load continues to decrease and the ratio IP/ILIMITEXT reaches 25%, the controller enters multi-cycle-modulation mode. This mode offers excellent efficiency under light-load conditions (such as in standby operation), and low no-load input power consumption. Using a fast-recovery (rather than an ultra-fast) diode for D5 allows some of the clamp energy to be recovered. This improves efficiency at light loads and reduces the no-load consumption of the power supply. Resistor R8 limits reverse diode current and dampens high-frequency ringing. Zener diode VR1 reduces no-load dissipation effectively disconnecting R9 when the voltage across C3 falls below 150 V. The bias winding of transformer T1 bias winding is designed such that during no-load the bias voltage supplying optocoupler U5 drops to approximately 8.5 V. This reduces the power drawn from the bias winding to supply U1 and moves its operation into multi-cycle-modulation mode during this load condition. As a consequence the power supply no-load consumption is reduced and the standby efficiency is increased. The output of the bias winding is rectified by diode D6 and filtered by capacitor C4. Optocoupler U5 supplies the control and supply current directly to the CONTROL (C) pin of U1.


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The power supply’s output voltage is regulated by the feedback circuit on the secondary side, which controls the output voltage by changing the optocoupler current. A change in the optocoupler current causes a change in current flowing into the CONTROL pin. Variation of the current into the C pin results in a variation of the duty cycle, which changes the power supply’s output voltage.

5.4 TOP255PN Secondary

Optocoupler U5 supplies the necessary IC supply and feedback current to the CONTROL pin. Using a high-gain optocoupler, such as the PC817D, with a CTR of 300% to 600% reduces secondary side dissipation. A high CTR also allows a higher value for R11, which reduces no-load input power even further (by approximately 30 mW) at 265 VAC. Reference IC (shunt regulator) U4 has a 400 µA typical minimum cathode current requirement for correct operation which is provided via R12. Resistors R15 and R16 form a voltage divider which is used to sense the output. Resistor R13 and capacitor C10 are compensation elements around U4 which set the feedback circuit frequency response. Resistor R11 sets the overall DC loop gain and limits the current through U5 during transient state conditions.

5.5 Output Rectification and Filtering

A snubber network on the output formed by R14 and C11 attenuates high-frequency ringing for reduced EMI. These two components were chosen with smaller values to allow high-frequency ringing to be damped while keeping any power dissipation they cause at no-load to a minimum. Inductor L2 and capacitor C9 form an output second-stage filter.


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6 PCB Layout

Figure 3 – Printed Circuit Board Layout.


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7 Bill of Materials Item Qty Ref

Des Description Mfg Part Number Mfg

1 1 C1 100 nF, 275 VAC, Film, X2 ECQ-U2A104ML Panasonic

2 1 C2 47 µF, 400 V, Electrolytic, Low ESR, 750 mΩ, (18 x 20)

EKMX401ELL470MM20S Nippon Chemi-Con

3 1 C3 2.2 nF, 1 kV, Disc Ceramic NCD222K1KVY5FF NIC Components Corp

4 1 C4 10 µF, 50 V, Electrolytic, Gen. Purpose, (5 x 11) KME50VB10RM5X11LL Nippon Chemi-Con

5 1 C5 47 µF, 35 V, Electrolytic, Gen. Purpose, (5 x 11) EKMG350ELL470ME11D Nippon Chemi-Con

6 2 C6 C10

100 nF, 50 V, Ceramic, X7R B37987F5104K000 Epcos

7 1 C7 1 nF, Ceramic, Y1 440LD10-R Vishay

8 1 C8 680 µF, 25 V, Electrolytic, Very Low ESR, 23 mΩ, (10 x 20)

EKZE250ELL681MJ20S Nippon Chemi-Con

9 1 C9 220 µF, 25 V, Electrolytic, Very Low ESR, 72 mΩ, (8 x 11.5)

EKZE250ELL221MHB5D Nippon Chemi-Con

10 1 C11 1 nF, 100 V, Ceramic, COG B37979G1102J000 Epcos

11 4 D1 D2 D3 D4

1000 V, 1 A, Rectifier, DO-41 1N4007-E3/54 Vishay

12 1 D5 800 V, 1 A, Fast Recovery Diode, 500 ns, DO-41 FR106 Diodes Inc.

13 1 D6 75 V, 300 mA, Fast Switching, DO-35 1N4148 Vishay

14 1 D7 100 V, 5 A, Schottky, DO-201AD1 SB5100 Fairchild

15 1 F1 3.15 A, 250V,Fast, TR5 37013150410 Wickman

16 1 J1 3 Position (1 x 3) header, 0.156 pitch, Vertical 26-48-1031 Molex

17 1 J2 2 Position (1 x 2) header, 0.156 pitch, Vertical, Straight-Friction Lock Header

26-48-1025 Molex

18 1 JP1 Wire Jumper, Insulated, 22 AWG, 0.5 in C2004-12-02 Gen Cable

19 1 L1 10 mH, 0.7 A, Common Mode Choke ELF15N007A Panasonic

20 1 L2 3.3 µH, 5.5 A, 8.5 x 11 mm R622LY-3R3M Toko

21 2 R3 R4 2.0 MΩ, 5%, 1/4 W, Carbon Film CFR-25JB-2M0 Yageo

22 1 R6 6.8 Ω, 5%, 1/8 W, Carbon Film CFR-12JB-6R8 Yageo

23 1 R8 22 Ω, 5%, 1/4 W, Carbon Film CFR-25JB-22R Yageo

24 1 R9 2.7 kΩ, 5%, 1/4 W, Carbon Film CFR-25JB-2K7 Yageo

25 1 R11 1 kΩ, 1%, 1/4 W, Metal Film MFR-25FBF-1K00 Yageo

26 1 R12 2 kΩ, 5%, 1/4 W, Carbon Film CFR-25JB-2K0 Yageo

27 1 R13 2.2 kΩ, 5%, 1/4 W, Carbon Film CFR-25JB-2K2 Yageo

28 1 R14 10 Ω, 5%, 1/2 W, Carbon Film CFR-50JB-10R Yageo

29 1 R15 10 kΩ, 1%, 1/4 W, Metal Film ERO-S2PHF1002 Panasonic

30 1 R16 38.3 kΩ, 1%, 1/4 W, Metal Film MFR-25FBF-38K3 Yageo

31 1 T1 Bobbin, EF25/13/7, Vertical, 10 pins FE0106 Miles-Platt

32 1 U1 TOPSwitch-HX, TOP255PN, DIP-8C TOP255PN Power Integrations

33 1 U4 2.495 V Shunt Regulator IC, 2%, 0 to 70C, TO-92

TL431CLPG On Semiconductor

34 1 U5 Opto coupler, 35 V, CTR 300-600%, 4-DIP PC817X4 Sharp

35 1 VR1 150 V, 1.5 W, DO-41 BZY97C150 Fagor


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8 Transformer Details

8.1 Electrical and Mechanical Diagram

Figure 4 – Transformer Electrical Diagram.

8.2 Electrical Specifications

Electrical Strength 1 second, 60 Hz, from Primary to Secondary 3000 VAC

Primary Inductance Pins 1 - 3, all other windings open, measured at 66 kHz, 0.4 VRMS

1.56 mH, ±5%

Resonant Frequency Pins 1 - 3, all other windings open 1500 kHz (Min.)

Primary Leakage Inductance Pins 1 - 3, with Pins 10 and 9 shorted, measured

at 66 kHz, 0.4 VRMS 14 µH (Max.)

8.3 Materials

Item Description

[1] Core: EF25, NC-2H or Equivalent, gapped for ALG of 244 nH/t²

[2] Bobbin: EF25, 5 pri. + 5 sec.

[3] Barrier Tape: Polyester film 15.60 mm wide

[4] Varnish

[5] Magnet Wire: 0.32 mm, Solderable Double Coated

[6] Magnet Wire: 0.45 mm, Solderable Double Coated

[7] Triple Insulated Wire: 0.4 mm


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8.4 Build Diagram

Figure 5 – Transformer Mechanical Drawing.

8.5 Transformer Construction

WD #1

Primary Winding #1 Start on pin 3 and wind 40 turns (x 1 filar) of item [5] in 1 layer from left to right. On the final layer, spread the winding evenly across entire bobbin. Finish this winding on pin 4.

Insulation Add 1 layer of tape, item [3], for insulation. WD#2

Feedback/Bias Start on pin 5 and wind 10 turns (x 1 filar) of item [6]. Wind in same rotational direction as primary winding. Spread the winding evenly across entire bobbin. Finish this winding on pin 2.

Insulation Add 3 layers of tape, item [3], for insulation.

WD #3 Secondary Winding

Start on pin 10 and wind 10 turns (x 2 filar) of item [7]. Spread the winding evenly across entire bobbin. Wind in same rotational direction as primary winding. Finish this winding on pin 9.

Insulation Add 3 layers of tape, item [3], for insulation.

WD #4 Primary Winding #2

Start on pin 4 and wind 40 turns (x 1 filar) of item [5] in 1 layer from left to right. On the final layer, spread the winding evenly across entire bobbin. Finish this winding on pin 1.

Insulation Add 3 layers of tape, item [3], for insulation. Core Assembly Assemble and secure core halves. Item [1].

Varnish Dip varnish uniformly in item [4]. Do not vacuum impregnate.


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9 Design Spreadsheet ACDC_TOPSwitchHX_021308

; Rev.1.8; Copyright Power Integrations 2008

INPUT INFO OUTPUT

UNIT TOP_HX_021308: TOPSwitch-HX Continuous/Discontinuous Flyback Transformer Design Spreadsheet

ENTER APPLICATION VARIABLES Customer

VACMIN 85 Volts Minimum AC Input Voltage VACMAX 265 Volts Maximum AC Input Voltage

fL 50 Hertz AC Mains Frequency

VO 12.00 Volts Output Voltage (main)

PO_AVG 20.00 Watts Average Output Power

PO_PEAK 20.00 Watts Peak Output Power n 0.80 %/100 Efficiency Estimate

Z 0.50 Loss Allocation Factor

VB 11 Info Volts Ensure proper operation at no load.

tC 3.00 mSeconds Bridge Rectifier Conduction Time Estimate

CIN 47.0 47 uFarads Input Filter Capacitor

ENTER TOPSWITCH-HX VARIABLES

TOPSwitch-HX TOP255PN/GN

Universal / Peak

115 Doubled/230V

Chosen Device TOP255 PN/GN

Power Out

22 W / 35 W 30W

KI 0.73 External Ilimit reduction factor (KI=1.0 for default ILIMIT, KI <1.0 for lower ILIMIT)

ILIMITMIN_EXT 0.780 Amps Use 1% resistor in setting external ILIMIT

ILIMITMAX_EXT 0.899 Amps Use 1% resistor in setting external ILIMIT Frequency (F)=132kHz, (H)=66kHz

H H Half frequency option is only available for P, G and M packages in addition to TOP259-TOP261YN devices. For full frequency operation choose E package or TOP254-TOP258YN devices.

fS 66000 Hertz TOPSwitch-HX Switching Frequency: Choose between 132 kHz and 66 kHz

fSmin 59400 Hertz TOPSwitch-HX Minimum Switching Frequency

fSmax 72600 Hertz TOPSwitch-HX Maximum Switching Frequency

High Line Operating Mode FF Full Frequency, Jitter enabled

VOR 100.00 Volts Reflected Output Voltage

VDS 10 Volts TOPSwitch on-state Drain to Source Voltage

VD 0.50 Volts Output Winding Diode Forward Voltage Drop

VDB 0.70 Volts Bias Winding Diode Forward Voltage Drop

KP 0.58 Ripple to Peak Current Ratio (0.3 < KRP < 1.0 : 1.0< KDP<6.0)

PROTECTION FEATURES

LINE SENSING Note - For P/G package devices only one of either Line sensing or Overload power limiting protection featues can be used. For all other packages both these functions can be simultaneously used.

VUV_STARTUP 95 Volts Minimum DC Bus Voltage at which the power supply will start-up

VOV_SHUTDOWN 445 Volts Typical DC Bus Voltage at which power supply will shut-down (Max)

RLS 4.0 M-ohms Use two standard, 2 M-Ohm, 5% resistors in series for line sense functionality.

OUTPUT OVERVOLTAGE

VZ 20 Volts Zener Diode rated voltage for Output Overvoltage shutdown protection

RZ 5.1 k-ohms Output OVP resistor. For latching


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shutdown use 20 ohm resistor instead OVERLOAD POWER LIMITING

Overload Current Ratio at VMAX

1.2 Enter the desired margin to current limit at VMAX. A value of 1.2 indicates that the current limit should be 20% higher than peak primary current at VMAX

Overload Current Ratio at VMIN 1.00 Margin to current limit at low line.

ILIMIT_EXT_VMIN 0.73 A Peak primary Current at VMIN

ILIMIT_EXT_VMAX 0.75 A Peak Primary Current at VMAX

RIL 8.65 k-ohms Current limit/Power Limiting resistor. RPL N/A M-ohms Resistor not required. Use RIL resistor

only

ENTER TRANSFORMER CORE/CONSTRUCTION VARIABLES

Core Type Auto EF25 Core Type Core EF25 P/N: PC40EF25-Z

Bobbin EF25_BOBBIN

P/N: *

AE 0.518 cm^2 Core Effective Cross Sectional Area

LE 5.78 cm Core Effective Path Length AL 2000 nH/T^2 Ungapped Core Effective Inductance

BW 15.6 mm Bobbin Physical Winding Width

M 0.00 mm Safety Margin Width (Half the Primary to Secondary Creepage Distance)

L 2.00 Number of Primary Layers NS 10 10 Number of Secondary Turns

DC INPUT VOLTAGE PARAMETERS

VMIN 84 Volts Minimum DC Input Voltage

VMAX 375 Volts Maximum DC Input Voltage CURRENT WAVEFORM SHAPE PARAMETERS

DMAX 0.58 Maximum Duty Cycle (calculated at PO_PEAK)

IAVG 0.30 Amps Average Primary Current (calculated at average output power)

IP 0.73 Amps Peak Primary Current (calculated at Peak output power)

IR 0.42 Amps Primary Ripple Current (calculated at average output power)

IRMS 0.40 Amps Primary RMS Current (calculated at average output power)

TRANSFORMER PRIMARY DESIGN PARAMETERS

LP 1563 uHenries Primary Inductance

LP Tolerance 5 5 Tolerance of Primary Inductance

NP 80 Primary Winding Number of Turns

NB 9 Bias Winding Number of Turns

ALG 244 nH/T^2 Gapped Core Effective Inductance BM 2756 Gauss Maximum Flux Density at PO, VMIN

(BM<3000)

BP 3558 Gauss Peak Flux Density (BP<4200) at ILIMITMAX and LP_MAX. Note: Recommended values for adapters and external power supplies <=3600 Gauss

BAC 799 Gauss AC Flux Density for Core Loss Curves (0.5 X Peak to Peak)

ur 1776 Relative Permeability of Ungapped Core

LG 0.23 mm Gap Length (Lg > 0.1 mm)

BWE 31.2 mm Effective Bobbin Width

OD 0.39 mm Maximum Primary Wire Diameter including insulation

INS 0.06 mm Estimated Total Insulation Thickness (= 2 * film thickness)

DIA 0.33 mm Bare conductor diameter


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AWG 28 AWG Primary Wire Gauge (Rounded to next smaller standard AWG value)

CM 161 Cmils Bare conductor effective area in circular mils

CMA 399 Cmils/Amp Primary Winding Current Capacity (200 < CMA < 500)

Primary Current Density (J) 5.03 Amps/mm^2 Primary Winding Current density (3.8 < J < 9.75)

TRANSFORMER SECONDARY DESIGN PARAMETERS (SINGLE OUTPUT EQUIVALENT)

Lumped parameters ISP 5.85 Amps Peak Secondary Current

ISRMS 2.78 Amps Secondary RMS Current

IO_PEAK 1.67 Amps Secondary Peak Output Current

IO 1.67 Amps Average Power Supply Output Current

IRIPPLE 2.22 Amps Output Capacitor RMS Ripple Current

CMS 556 Cmils Secondary Bare Conductor minimum circular mils

AWGS 22 AWG Secondary Wire Gauge (Rounded up to next larger standard AWG value)

DIAS 0.65 mm Secondary Minimum Bare Conductor Diameter

ODS 1.56 mm Secondary Maximum Outside Diameter for Triple Insulated Wire

INSS 0.46 mm Maximum Secondary Insulation Wall Thickness

VOLTAGE STRESS PARAMETERS

VDRAIN 575 Volts Maximum Drain Voltage Estimate (Includes Effect of Leakage Inductance)

PIVS 59 Volts Output Rectifier Maximum Peak Inverse Voltage

PIVB 55 Volts Bias Rectifier Maximum Peak Inverse Voltage

TRANSFORMER SECONDARY DESIGN PARAMETERS (MULTIPLE OUTPUTS)

1st output

VO1 12 Volts Output Voltage IO1_AVG 1.67 Amps Average DC Output Current

PO1_AVG 20.00 Watts Average Output Power

VD1 0.5 Volts Output Diode Forward Voltage Drop

NS1 10.00 Output Winding Number of Turns

ISRMS1 2.778 Amps Output Winding RMS Current

IRIPPLE1 2.22 Amps Output Capacitor RMS Ripple Current PIVS1 59 Volts Output Rectifier Maximum Peak Inverse

Voltage

CMS1 556 Cmils Output Winding Bare Conductor minimum circular mils

AWGS1 22 AWG Wire Gauge (Rounded up to next larger standard AWG value)

DIAS1 0.65 mm Minimum Bare Conductor Diameter

ODS1 1.56 mm Maximum Outside Diameter for Triple Insulated Wire

2nd output

VO2 Volts Output Voltage

IO2_AVG Amps Average DC Output Current PO2_AVG 0.00 Watts Average Output Power



ISRMS2 0.000 Amps Output Winding RMS Current

IRIPPLE2 0.00 Amps Output Capacitor RMS Ripple Current

PIVS2 3 Volts Output Rectifier Maximum Peak Inverse Voltage



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AWGS2 N/A AWG Wire Gauge (Rounded up to next larger standard AWG value)

DIAS2 N/A mm Minimum Bare Conductor Diameter

ODS2 N/A mm Maximum Outside Diameter for Triple Insulated Wire

3rd output

VO3 Volts Output Voltage

IO3_AVG Amps Average DC Output Current

PO3_AVG 0.00 Watts Average Output Power



ISRMS3 0.000 Amps Output Winding RMS Current IRIPPLE3 0.00 Amps Output Capacitor RMS Ripple Current

PIVS3 3 Volts Output Rectifier Maximum Peak Inverse Voltage


AWGS3 N/A AWG Wire Gauge (Rounded up to next larger standard AWG value)

DIAS3 N/A mm Minimum Bare Conductor Diameter

ODS3 N/A mm Maximum Outside Diameter for Triple Insulated Wire

Total Continuous Output Power 20 Watts Total Continuous Output Power

Negative Output N/A If negative output exists enter Output

number; eg: If VO2 is negative output, enter 2


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10 Power Supply Performance

All tests were performed open frame at room temperature (+25 °C) and 60 Hz line frequency, unless noted otherwise.

10.1 Energy Efficiency

70%

75%

80%

85%

90%

85 115 145 175 205 235 265

Input Voltage (VAC)

Eff

icie

ncy

Figure 6 – Full Load Efficiency Over Input Voltage Range.


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70%

75%

80%

85%

90%

0 5 10 15 20

Output Power (W)

Eff

icie

nc

y

115 VAC

230 VAC

Figure 7 – Efficiency Over Load.

Table 2 lists the average active-on efficiency as defined by the Energy Star 2.0 specification (Final April 23, 2008).

Efficiency at Relative Load Point Input Voltage 25% 50% 75% 100%

Average Efficiency

115 VAC 86.05% 84.67% 84.25% 84.00% 85%

230 VAC 85.76% 85.61% 85.47% 85.40% 86%

Minimum efficiency Energy Star 2.0: 0.0626 * LN(20) + 0.622 81%

Table 2 – Average Active-on Efficiency.


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0.05

0.10

0.15

85 115 145 175 205 235 265

Input Voltage (VAC)

Inp

ut

Po

we

r (W

)

Figure 8 – No-load Input Power Consumption Over Line.


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Figure 9 depicts the available output power in standby with the input power limited to 1.0 W.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

85 115 145 175 205 235 265

Input Voltage (VAC)

Ou

tpu

t P

ow

er

(W)

Pin=1.0 W Pin=0.5 W Pin=0.3 W

Figure 9 – Standby Output Power Over Line and Input Power.

10.2 Output Regulation and Quality

99.8%

99.9%

100.0%

100.1%

100.2%

85 115 145 175 205 235 265

Input Voltage (VAC)

No

rmalize

d O

utp

ut

Vo

lta

ge

Full load (20 W)

No-load (0 W)

Figure 10 – Regulation Over Line and Load.


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Figures 11 to 15 depict output noise and ripple performance at various load and line conditions. The measurements were taken with a local voltage probe decoupling capacitance of 1 µF/50 V (electrolytic) and 0.1 µF/50 V (ceramic) with a 20 MHz DSO input filter.

Figure 11 – Output Noise at 20 W, 85 VAC. VOUT (100 mV/Div, 10 µs/div).

Figure 12 – Output Noise at 20 W, 265 VAC. VOUT (100 mV/Div, 10 µs/div).

Figure 13 – Output Noise at No-load, 85 VAC. Upper: ID (0.2 A/Div, 2 ms/div). Lower: VOUT (20 mV/div).

Figure 14 – Output Noise at No-load, 265 VAC. Upper: ID (0.2 A /Div, 2 ms/div). Lower: VOUT (50 mV/div).


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Figure 15 – Output Ripple at 20 W, 85 VAC. VOUT (0.1 V/Div, 5 ms/div).


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10.3 Transient Load

Figures 16 through 19 depict the step-load performance at various load combination and line-voltage conditions. The current slew rate was set to 10 mA/µs.

Figure 16 – Step Load 50-100%, 85 VAC. Upper: VOUT (0.5 V/div, 2 ms/div). Lower: ILOAD (0.5 A/div).





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10.4 Startup

Figures 20 through 23 depict the startup performance at various load and line conditions.

Figure 20 – Startup at no-load, 85 VAC. Upper: VDS (50 V/div, 5 ms/div). Middle: ID (0.2 A/div). Lower: VOUT (2 V/div).

Figure 21 – Startup at no-load, 265 VAC. Upper: VDS (100 V/div, 5 ms/div). Middle: ID (0.2 A/div). Lower: VOUT (2 V/div).

Figure 22 – Startup at 20 W, 85 VAC. Upper: VDS (50 V/div, 5 ms/div). Middle: ID (0.2 A/div). Lower: VOUT (2 V/div).

Figure 23 – Startup at 20 W, 265 VAC. Upper: VDS (100 V/div, 5 ms/div). Middle: ID (0.2 A/div). Lower: VOUT (2 V/div).


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11 Conducted EMI

Conducted EMI was measured with a 7.2 Ω resistive load (20 W).

Figure 24 – Conducted EMI, 115 VAC. Output RTN Floating.

Figure 25 – Conducted EMI, 230 VAC. Output RTN Floating.

Figure 26 – Conducted EMI, 115 VAC. Output RTN Connected to Artificial Hand.

Figure 27 – Conducted EMI, 230 VAC. Output RTN Connected to Artificial Hand.


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11.1 Waveform Plots

Figure 28 – Drain Waveforms at 20 W, 85 VAC. Upper: VDS (50 V/div, 5 µs/div). Lower: ID (0.2 A/div).

Figure 29 – Drain Waveforms at 20 W, 265 VAC. Upper: VDS (100 V/div, 5 µs/div). Lower: ID (0.2 A/div).

Figure 32 depicts the output voltage and Drain waveforms during an output short circuit (applied at the DC load). The input power under this condition is 0.9 W.

Figure 30 – Output Short Circuit, 265 VAC. Upper: VDS (100 V/div, 500 ms/div). Middle: ID (0.2 A/div). Lower: VOUT (2 V/div).

Figure 31 – Output diode reverse voltage at 20 W, 265 VAC. Upper: VRR(D7) (20 V/div, 1 µs/div). Lower: ID (0.2 A/div).


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Figure 32 – Clamp Zener Voltage at 20 W, 265 VAC. Upper: VVR1 (50 V/div, 5 µs/div). Lower: ID (0.2 A/div).

Figure 33 – Clamp Zener Voltage at 0 W, 265 VAC. Upper: VVR1 (50 V/div, 2 ms/div). Lower: ID (0.2 A/div).


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12 Revision History

Date Author Rev. Description & changes Reviewed 30-Sep-08 SGK 1.0 Initial Release


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For the latest updates, visit our website: www.powerint.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or

manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit

described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL

WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,

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may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications

assigned to Power Integrations. A complete list of Power Integrations’ patents may be found at www.powerint.com.

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