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Design, Automation and Test in Europe - GBV · Proceedings Design, Automation and Test in Europe...
Transcript of Design, Automation and Test in Europe - GBV · Proceedings Design, Automation and Test in Europe...
Proceedings
Design, Automation andTest in Europe
Munich, Germany
March 7-11,2005
Sponsored by the European Design and Automation Association, The EDA Consortium,The IEEE Computer Society TTTC, The IEEE Computer Society DATC,
ECSI, ACM SIGDA, RAS
IEEE
COMPUTERSOCIETY
http://computer.orgLos Alamitos, California
Washington • Brussels • Tokyo
Table of Contents Volume IDesign, Automation and Test in Europe Conference and Exhibition — DATE 2005
DATE Executive Committee xviTechnical Program Chairs xviiDATE Sponsor Committee xixTechnical Program Committee xxReviewers xxivForeword xxviiBest Paper Awards xxixTutorials xxxMaster Courses xxxiv
Keynote Addresses
SoC in Nanoera: Challenges and Endless Possibility 2J. Kong
Striking a New Balance in the Nanometer Era: First-Time-Right and Time-To-MarketDemands Versus Technology Challenges 3
G. Hughes
1A: Partitioning and Optimisation for Reconfigurable ComputingModerators: S. Vernalde, IMEC, BE; S. Vassiliadis, TU Delft, NL
A Register Allocation Algorithm in the Presence of Scalar Replacement forFine-Grain Configurable Architectures 6
N. Baradaran and P. Diniz
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture forDomain-Specific Optimization 12
Y. Kim, M. Kiemb, C Park, J. Jung, and K. Choi
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores UsingDynamic Hardware/Software Partitioning 18
R. Lysecky and F. Wahid
Reconfigurable Elliptic Curve Cryptosystems on a Chip 24R. Cheung, W. Luk, and P. Cheung
Interactive Presentations
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs 30R. Rodrigues and J. Cardoso
FPGA Architecture for Multi-Style Asynchronous Logic 32N. Huot, H. Dubreuil, L Fesquet, and M. Renaudin
1B: Hot Topic — Analogue/Digital Circuit Design in 65nm: End of the RoadOrganiser/Moderator: G. Gielen, KU Leuven, BESpeakers: G. Gielen, KU Leuven, BE; W. Dehaene, KU Leuven, BE; D. Drexelmayr, Infineon, AT;E. Janssens, ST Microelectronics, BE; T. Vucurevich, Cadence, US; K. Maex, 1MEC, BE; P. Christie, Philips, NL
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? 36G. Gielen, W. Dehaene, P. Christie, D. Draxelmayr, E. Janssens, K. Maex, and T. Vucurevich
1C: SoC Design-for-TestModerators: E. Larsson, Linkoping U, SE; R. Dorsch, IBM, DE
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips 44S. Goel and E. Marinissen
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores 50A. Sehgal, F. Liu, S. Ozev, and K. Chakrabarty
Logic Design for On-Chip Test Clock Generation — Implementation Details andImpact on Delay Test Quality 56
M. Beck, O. Barondeau, M. Kaibel, F. Poehl, X. Lin, and R. Press
Interactive Presentation
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture 62A. Amory, M. Lubaszewski, F. Moraes, and E. Moreno
1E: Embedded Tutorial — Cross-Pollination between HW and SW —Hard Lessons for Software, and Vice VersaOrganiser: G. Martin, Tensilica, USModerator: L. Lavagno, Politecnico di Torino, ITSpeakers: S. Edwards, Columbia U, US; A. Dean, North Carolina State U, US; I. Oliver, Nokia, FI
The Challenges of Hardware Synthesis from C-like Languages 66S. Edwards
Software Thread Integration and Synthesis for Real-Time Applications 68A. Dean
Applying UML and MDA to Real Systems Design 70/. Oliver
1F: Low Power Design with Error ToleranceModerators: C. Piguet, CSEM, CH; A. Macii, Politecnico di Torino, IT
Energy Bounds for Fault-Tolerant Nanoscale Designs 74D. Marculescu
DVS for On-Chip Bus Designs Based on Timing Error Correction 80H. Kaul, D. Sylvester, D. Blaauw, T. Mudge, and T. Austin
Joint Power Management of Memory and Disk 86L. Cai and Y.-H. Lu
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Assertion-Based Design Exploration of DVS in Network Processor Architectures 92J. Yu, W. Wu, X. Chen, H. Hsieh, J. Yang, and F. Balarin
2A: Scheduling and Synthesis for Reconfigurable ComputingModerators: F. Kurdahi, UC Irvine, US; C. Passerone, Politecnico di Torino, IT
Instruction Scheduling for Dynamic Hardware Configuration 100E. Panainte, K. Bertels, and S. Vassiliadis
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the ReconfigurationOverhead of Dynamically Reconfigurable Hardware 106
J. Resano, D. Mozos, and F. Catthoor
Optimized Generation of Data-Path from C Codes for FPGAs 112Z Guo, B. Buyukkurt, W. Najjar, and K. Vissers
2B: Analogue Simulation, Placement and Statistical AnalysisModerators: G. Vandersteen, IMEC, BE; H. Graeb, TU Munich, DE
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration andOrthogonal Polynomial Series 120
E. Martens and G. Gielen
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling andCorrelation Loop Tracing 126
F. Liu, J. Flomenberg, D. Yasaratne, and S. Ozev
On Statistical Timing Analysis with Inter and Intra-die Variations 132H. Mangassarian and M. Anis
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis 138R. Badaoui and R. Vemuri
2C: Analogue and Gigahertz TestModerators: A. Chatterjee, Georgia Institute of Technology, US; J. Carbonero, STMicroelectronics, FR
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits 146K. Noguchi and M. Nagata
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL 152D. Keezer, C. Gray, A. Majid, and N. Taher
Noise Figure Evaluation Using Low Cost BIST 158M. Negreiros, L. Carro, and A. Susin
Specification Test Compaction for Analog Circuits and MEMS 164S. Biswas, R. Blanton, L. Pileggi, and P. Li
Interactive Presentations
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach 170V. Danelon, J. Carbonero, R. Kheriji, and S. Mir
IEEE 1149.4 Compatible ABMs for Basic RF Measurements 172P. Syri, J. Hakkinen, and M. Moilanen
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Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits 174C. Savioli, C. Czendrodi, J. Calvano, and A. Mesquita
2E: Ubiquitous Computing: Security and Energy AspectsModerators: T. Basten, TU Eindhoven, NL; R. Marculescu, Carnegie Mellon U, US
Secure Embedded Processing through Hardware-Assisted Run-time Monitoring 178D. Arora, N. Jha, S. Ravi, and A. Raghunathan
Energy-Aware Routing for E-Textile Applications 184J.-C. Kao and R. Marculescu
LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling inWireless Sensor Networks . 190
A. Ghosh and T. Givargis
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks:Modeling and Improvement Perspectives 196
B. Bougard, F. Catthoor, D. Daly, A. Chandrakasan, and W. Dehaene
Interactive Presentation
Lifetime Modeling of a Sensor Network 202V. Rai and R. Mahapatra
2F: Power Aware Design in DSM TechnologyModerators: E. Schmidt, Chip Vision Design Systems, DE; J. Haid, Infineon, DE
A Fast Concurrent Power-Thermal Model for Sub-lOOnm Digital ICs 206J. Rossello, V. Canals, S. Bota, J. Segura, and A. Keshavarzi
Activity Packing in FPGAs for Leakage Power Reduction 212H. Hassan, M. Anis, A. El Daher, and M. Elmasry
Simultaneous Partitioning and Frequency Assignment for On-chip Bus Architectures 218S. Srinivasan, L. Li, and N. Vijaykrishnan
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits 224S. Mukhopadhyay, S. Bhunia, and K. Roy
Interactive Presentation
Leakage-Aware Interconnect for On-Chip Network . 230Y. -F. Tsai, V. Narayaynan, Y. Xie, and M. Irwin
3A: Reconfigurability in MPSoCModerators: K. Goossens, Philips Research, NL; P. lenne, EPFL, CH
Centralized Run-Time Resource Management in a Network-on-ChipContaining Reconfigurable Hardware Tiles 234
V. Nollet, T. Marescaux, P. Avasare, J.-Y. Mignolet, and D. Verkest
Symmetric Multiprocessing on Programmable Chips Made Easy 240A. Hung, W. Bishop, and A. Kennings
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A Complete Network-On-Chip Emulation Framework _246N. Genko, G. De Micheli, D. Atienza, J. Mendias, R. Hermida, and F. Catthoor
Interactive Presentations
Low Cost Task Migration Initiation in a Heterogeneous MP-SoC 252V. Nollet, P. Avasare, J.-Y. Mignolet, and D. Verkest
Predictable Embedding of Large Data Structures in Multiprocessor Networks-On-Chip 254S- Stuijk, T. Basten, B. Mesman, and M. Geilen
3B: Analogue, Mixed-Signal and RF Circuits and SystemsModerators: T. Ifstrom, Robert Bosch, DE; A. Rodriguez, IMSE-CNM, ES
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated OscillatorClock-Recovery Circuit 258
P. Muller, Y. Leblebici, M. Atarodi, and A. Tajalli
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized forSignal Path Complexity, Sensitivity and Power Consumption 264
H. Tang, Y. Wei, and A. Doboli
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF CircuitsIncluding Interconnect Resistance 270
C. Soens, P. Wambacq, G- Van Der Plas, and S. Donnay
Interactive Presentations
Systematic Figure of Merit Computation for the Design of Pipeline ADC 277L. Barrandon, S. Crand, and D. Houzet
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters 279Y.-T. Chien, J.-H. Lou, D. Chen, G.-K. Ma, R. Rutenbar, andT. Mukherjee
3C: Reliability at the Very Deep Sub-Micron RegionModerators: C Metra, Bologna U, IT; R. Leveugle, TIMA Laboratory, FR
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices 282S. Krishnaswamy, G. Viamontes, I. Markov, and J. Hayes
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits 288Y. Dhillon, A. Diril, and A. Chatterjee
Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing andStatistical Techniques 294
O. Neiroukh and X. Song
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown 300J. Carter, S. Ozev, and D. Sorin
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Interactive Presentations
An Accurate SER Estimation Method Based on Propagation Probability 306G. Asadi and M. Tahoori
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation 308C. Lopez-Ongil, M. Garcia-Valderas, M. Portela-Garcia, and L. Entrena-Arrontes
3E: Techniques for IP-Based DesignModerators: R. Seepold, Carlos III de Madrid U, ES; G. Martin, Tensilica, US
TDM A Time Slot and Turn Optimization with Evolutionary Search Techniques 312A. Hamann and R. Ernst
Scheduling of Soft Real-Time Systems for Context-Aware Applications 318J. Wong, F. Li, W. Liao, L. He, and M. Potkonjak
Model Reuse through Hardware Design Patterns 324F. Rincon, F. Moya, J. Barba, and J. Lopez
A Public-Key Watermarking Technique for IP Designs 330
A. Abdel-Hamid, S. Tahar, and E. Aboulhamid
Interactive Presentation
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer 336P. Martin
3F: HW/SW Solutions for Low Power Multimedia SystemsModerators: J. Henkel, Karlsruhe U, DE; W. Nebel, OFFIS, DE
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing 340S. Yardi, M. Hsiao, T. Martin, and D. Ha
HEBS: Histogram Equalization for Backlight Scaling 346A. Iranli, H. Fatemi, and M. Pedram
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using aDecomposition Approach 352
U. Ogras and R. Marculescu
A Way Memoization Technique for Reducing Power Consumption of Caches inApplication Specific Integrated Processors 358
T. lshihara and F. Fallah
4A: Embedded System Partitioning and ValidationModerators: F. Petrot, Pierre et Marie Curie U, Paris VI, FR; H. Hsieh, UC Riverside, US
Design Space Exploration for Dynamically Reconfigurable Architectures 366B. Miramond and J. -M. Delosme
A Dependability-Driven System-Level Design Approach for Embedded Systems 372A. Jhumka, S. Klaus, and S. Huss
A Time Slice Based Scheduler Model for System Level Design 378V. Shah, C. Passerone, L Lavagno, and Y. Watanabe
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-LevelHardware/Software Co-Emulation 384
J.-G. Lee, M.-K. Chung, K.-Y. Ahn, S-H. Lee, and C.-M. Kyung
Automated Synthesis of Assertion Monitors Using Visual Specification 390A. Gadkari and S. Ramesh
Interactive Presentation
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms 396G. Stitt and F. Vahid
4B: Logic SynthesisModerators: M. Berkelaar, Magma Design Automation, NL; T. Villa, DIEGM —Udine U, IT
Statistical Timing Based Optimization Using Gate Sizing 400A. Agarwal, K. Chopra, and D. Blaauw
An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs 406M. Teslenko and E. Dubrova
SAT-Based Complete Don't-Care Computation for Network Optimization 412A. Mishchenko and R. Brayton
Efficient Solution of Language Equations Using Partitioned Representations 418A. Mishchenko, R. Brayton, R. Jiang, T. Villa, and N. Yevtushenko
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement 424G. Bouesse, M. Renaudin, S. Dumont, and F. Germain
Interactive Presentations
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition 430A. Martinelli and E. Dubrova
Uniformly-Switching Logic for Cryptographic Hardware 432/. Markov and D. Maslov
Exact Synthesis of 3-qubit Quantum Circuits from Non-Binary Quantum Gates UsingMultiple-Valued Logic and Group Theory 434
G. Yang, W. Hung, X. Song, and M. Perkowski
4C: Defect Detection and CharacterisationModerators: R. Aitken, Artisan, US; C. Hawkins, New Mexico U, US
Memory Testing under Different Stress Conditions: An Industrial Evaluation 438A. Majhi, M. Azimane, G. Gronthoud, M. Lousberg, S. Eichenberger, and F. Bowen
Worst-Case and Average-Case Analysis of n-Detection Test Sets 444/. Pomeranz and S. Reddy
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Defect Aware Test Patterns 450H. Tang, G. Chen, S. Reddy, C. Wang, J. Rajski, and I. Pomeranz
Computational Intelligence Characterization Method of Semiconductor Device 456E. Liau and D. Schmitt-Landsiedel
Interactive Presentations
A New Embedded Measurement Structure for eDRAM Capacitor 462L. Lopez, D. Nee, and J. Portal
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs 464S. Bota, M. Rosales, J. Rosselo, and J. Segura
4E: Real-Time SchedulingModerators: S. Baruah, North Carolina U, US; J.-D. Decotignie, CSEM, CH
An Approximation Algorithm for Energy-Efficient Scheduling on a Chip Multiprocessor 468C.-Y. Yang, J.-J. Chen, and T.-W. Kuo
Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model 474H. Wu, B. Ravindran, and E. Jensen
Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies 480R. Henia and R. Ernst
A New Task Model for Streaming Applications and its Schedulability Analysis 486S. Chakraborty and L. Thiele
Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling 492K. Albers and F. Slomka
Interactive Presentation
Unified Modeling of Complex Real-Time Control Systems 498H. He, Y.-F. Zhong, and C.-L. Cai
4F: SoC Power OptimisationModerators: M. Poncino, Verona U, IT; R. Zafalon, STMicroelectronics, IT
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique 502C. Marcon, A. Susin, N. Calazans, F. Moraes, F. Hessel, and I. Reis
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs:Snoop-Based Cache Coherence vs. Software Solutions 508
M. Loghi and M. Poncino
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints 514A. Andrei, P. Eles, Z. Peng, M. Schmitz, and B. Al Hashimi
Tag Overflow Buffering: An Energy-Efficient Cache Architecture 520P. Azzoni, M. Loghi, and M. Poncino
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Interactive Presentations
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique 526M. Li, X. Wu, R. Yao, andX. Yan
Hardware Accelerated Power Estimation 528J. Coburn, S. Ravi, and A. Raghunathan
4G: Embedded Tutorial — Platforms and Tools for Automotive System DesignOrganiser/Moderator: J. Bortolazzi, DaimlerChrysler, DESpeakers: A. Sangiovanni-Vincentelli, UC Berkeley, US; H. Brinkmeyer, IBB, DE; S. Ortmann, Carmeq, DE;J. Langenwalter, The MathWorks Inc, US/DE
Integrated Electronics in the Car and the Design Chain Evolution or Revolution? 532A. Sangiovanni-Vincentelli
A New Approach to Component Testing 534H. Brinkmeyer
Process Oriented Software Quality Assurance — An Experience Report in Process Improvement —OEM Perspective 536
T. lllgen and S. Ortmann
Embedded Automotive System Development Process Steer-by-Wire System 538J. Langenwalter
5A: System Level Languages, Verification and SimulationModerators: P. Ellervee, TU Tallinn, ES; S. Singh, Microsoft, US
Functional Validation of System Level Static Scheduling 542S. Abdi and D. Gajski
Defining an Enhanced RTL Semantics 548S. Zhao and D. Gajski
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC 554H. Hassan, K. Sakanushi, Y. Takeuchi, and M. Imai
Design for Verification of SystemC Transaction Level Models 560A. Habibi and S. Tahar
Interactive Presentations
Systematic Transaction Level Modeling of Embedded Systems with SystemC 566W. Klingauf
Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures 5685. Dasgupta and A. Yakovlev
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5B: Panel Session — Semiconductor Industry Disaggregation vs. Reaggregation:Who will be the Shark?Organiser: Y. Zorian, Virage Logic, USModerator: J. Barr, Buckingham Capital, USPanellists: D. Wassung, AH&H, US; J. Ensel, Virage Logic, US; G. Stark, Synopsys, US;M. Gianfagna, eSilicon, US; K. Ruparel, Cisco Systems, US; A. de la Haye, Philips Semiconductors, NL
Semiconductor Industry Disaggregation vs Reaggregation: Who will be the Shark? 572Y. Zorian, J. Barr, D. Wassung, J. Ensel, G. Stark, M. Gianfagna, K. Ruparel, A. de la Haye
5C: Reliable Memory DesignModerators: D. Gizopoulos, Piraeus U, GR; M. Sonza Reorda, Politecnico di Torino, IT
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories 574J.-F. Li, T.-W. Tseng, and C.-L. Wey
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults inHighly Reliable Memories 580
L. Schiano, M. Ottavi, F. Lombardi, S. Pontarelli, and A. Salsano
Increasing Register File Immunity to Transient Errors 586G. Memik, M. Kandemir, and O. Ozturk
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories 592B. Gill, M. Nicolaidis, F. Wolff, C Papachristou, and S. Garverick
5E: Execution-Time AnalysisModerators: P. Puschner, TU Vienna, AT; G. Fohler, Malardalen U, SE
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software 600L. Wehmeyer and P. Marwedel
Automatic Timing Model Generation by CFG Partitioning and Model Checking 606/. Wenzel, B. Rieder, R. Kirner, and P. Puschner
A Contribution to Branch Prediction Modeling in WCET Analysis 612C. Burguiere and C. Rochange
Interactive Presentations
Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software byAbstract Interpretation 618
C. Ferdinand and R. Heckman
5F: Battery and Current Considerations in CMOS DesignModerators: C. Svensson, Linkoping U, SE; A.J. Acosta Jimenez, Seville U, ES
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms 622J. Khan and R. Vemuri
Design Method for Constant Power Consumption of Differential Logic Circuits 628K. Tiri and I. Verbauwhede
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Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling 634L.-F. Leung, C.-Y. Tsui, andX. Hu
Low Power Oriented CMOS Circuit Optimization Protocol 640A. Verle, X. Michel, N. Azemard, P. Maurine, and D. Auvergne
Interactive Presentations
Area-Efficient Selective Multi-Threshold CMOS Design Methodology forStandby Leakage Power Reduction 646
T. Kitahara, N. Kawabe, F. Minami, K. Seta, and T. Furusawa
Hotspot Prevention through Runtime Reconfiguration in Network-On-Chip 648G. Link and N. Vijaykrishnan
Power-Performance Trade-offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage 650R. Bai, N.-S. Kim, T. Kgil, T. Mudge, andD. Sylvester
5G: Panel Session — Automotive System ArchitecturesOrganiser/Moderator: J. Bortolazzi, DaimlerChrysler, DESpeakers: J.-L Mate, SiemensVDO, FR; J. Becker, Karlsruhe U, DE; C. Morgano, Microsoft Europe
Panel Session — Automotive System Architectures 654
J. Bortolazzi, J- -L. Mate, J. Becker, and C. Morgano
5K: Keynote
Automotive System Design — Challenges and Potential 656H. Heinecke
Author Index 659A