CSE 494: Electronic CSE 494: Electronic Design Automation Design Automation

Lecture 2Lecture 2

VLSI Design, Physical Design Automation, VLSI Design, Physical Design Automation, Design StylesDesign Styles

OrganizationOrganization

IntroductionIntroduction VLSI Design CycleVLSI Design Cycle Physical Design Cycle and AutomationPhysical Design Cycle and Automation Design StylesDesign Styles PackagingPackaging

Electronic Design Automation (EDA)Electronic Design Automation (EDA)

Also known as VLSI CAD.Also known as VLSI CAD. It refers to the utilization of CAD It refers to the utilization of CAD

techniques for VLSI design.techniques for VLSI design. The course will cover CAD algorithms for The course will cover CAD algorithms for

physical design automation (primary physical design automation (primary focus) and logic synthesis (secondary focus) and logic synthesis (secondary focus).focus).

Why EDA?Why EDA?

Complexity of current day electronic Complexity of current day electronic design (P4 : 55 million transistors, P4 EE: design (P4 : 55 million transistors, P4 EE: 178 million transistors).178 million transistors). Manual design is unrealistic.Manual design is unrealistic.

Fewer errors.Fewer errors. Time to market.Time to market.

Industry perspectiveIndustry perspective

Major EDA tool vendors:Major EDA tool vendors: Synopsys, Cadence, Mentor graphicsSynopsys, Cadence, Mentor graphics

Major semiconductor design houses:Major semiconductor design houses: Intel, IBM, Motorola, Xilinx …Intel, IBM, Motorola, Xilinx …

Course offers key skill set for CAD Course offers key skill set for CAD Engineer.Engineer.

Research perspectiveResearch perspective

Active area of research.Active area of research. Major conferences:Major conferences:

Design Automation Conference (DAC)Design Automation Conference (DAC) Design and Test in Europe (DATE)Design and Test in Europe (DATE) International Conference on CAD (ICCAD)International Conference on CAD (ICCAD) International Conference on Low Power Electronic International Conference on Low Power Electronic

Design (ISLPED)Design (ISLPED) International Conference on Computer Design (ICCD)International Conference on Computer Design (ICCD) ......

Course acts a stepping stone for research in Course acts a stepping stone for research in VLSI CAD.VLSI CAD.

VLSI Design CycleVLSI Design Cycle

System Specification

Architectural Design

Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication

Packaging andTesting

Functional verification by simulation

VLSI Design CycleVLSI Design Cycle

System specificationSystem specification: High level functional : High level functional description (informal) of the design with size, description (informal) of the design with size, speed, and power constraints.speed, and power constraints.

Architectural designArchitectural design: Micro-architectural : Micro-architectural specification (informal) of the design with specification (informal) of the design with architecture style number of ALUs, floating point architecture style number of ALUs, floating point units, number and structure of pipelines, and units, number and structure of pipelines, and size of caches.size of caches.

Functional designFunctional design: The functionality of each : The functionality of each unit and their interconnection is described by unit and their interconnection is described by HDL. The area, power, and time of each unit is HDL. The area, power, and time of each unit is identified. identified.

VLSI Design CycleVLSI Design Cycle

Logic designLogic design: Register transfer level (RTL) : Register transfer level (RTL) description of the design in HDL is generated. It description of the design in HDL is generated. It consists of boolean expressions and timing consists of boolean expressions and timing information.information.

Circuit designCircuit design: A circuit description in logic : A circuit description in logic gates (or netlist) is developed. gates (or netlist) is developed. Automated circuit Automated circuit design is called logic synthesis.design is called logic synthesis.

Physical designPhysical design: The circuit representation (or : The circuit representation (or netlist) is converted into a geometric netlist) is converted into a geometric representation called the layout. representation called the layout. Automated Automated physical design is called physical synthesis.physical design is called physical synthesis.

VLSI Design CycleVLSI Design Cycle

FabricationFabrication: After a layout is generated : After a layout is generated the design is ready for actual fabrication or the design is ready for actual fabrication or manufacturing. manufacturing.

Packaging, Testing and DebuggingPackaging, Testing and Debugging: The : The fabricated wafer is diced into individual fabricated wafer is diced into individual chips that are then packaged, tested, and chips that are then packaged, tested, and de-bugged.de-bugged.

New Trends in VLSI DesignNew Trends in VLSI Design

Increased interconnect delayIncreased interconnect delay: interconnect : interconnect not scaling at the same pace as the device.not scaling at the same pace as the device.

Increasing interconnect areaIncreasing interconnect area: Upto 40 % of : Upto 40 % of the area devoted to interconnect.the area devoted to interconnect.

Increasing number of metal layersIncreasing number of metal layers: Upto 5 : Upto 5 layers for microprocessors.layers for microprocessors.

Increasing planning requirementsIncreasing planning requirements: Physical : Physical design early on in the design cycle.design early on in the design cycle.

Automated synthesisAutomated synthesis: Logic and high-level.: Logic and high-level.

Physical Design CyclePhysical Design Cycle

InputInput: A netlist of gates (or blocks) and : A netlist of gates (or blocks) and their interconnections.their interconnections.

OutputOutput: A geometrical layout of the netlist : A geometrical layout of the netlist within an area constraint.within an area constraint.

Other goalsOther goals: Minimize signal delays, : Minimize signal delays, interconnection area, power, cross-talk. interconnection area, power, cross-talk.

An Example NetlistAn Example Netlist

An Example LayoutAn Example Layout

An Example LayoutAn Example Layout

An Example LayoutAn Example Layout

Physical Design CyclePhysical Design Cycle

PartitioningPartitioning: Divide the net-list into sub-: Divide the net-list into sub-sets. sets.

Floorplanning and placementFloorplanning and placement: : Determine the dimensions of the various Determine the dimensions of the various units and their placement.units and their placement.

Global routingGlobal routing: Determine the regions : Determine the regions through the chip that the wires or net through the chip that the wires or net would be routed.would be routed.

Physical Design CyclePhysical Design Cycle

Detailed routingDetailed routing :: Determine the actual Determine the actual layout of the nets within each routing layout of the nets within each routing region.region.

CompactionCompaction : Compress the layout to : Compress the layout to reduce the area.reduce the area.

Extraction and verificationExtraction and verification : Design rule : Design rule checking for ensuring that the layout checking for ensuring that the layout meets the fabrication constraints. meets the fabrication constraints. Extraction and simulation against previous Extraction and simulation against previous specification.specification.

Physical Design AutomationPhysical Design Automation

Physical design automation refers Physical design automation refers to the computer-aided physical to the computer-aided physical design cycle.design cycle.

Design StylesDesign Styles Full CustomFull Custom

Utilized for large production volume chips such as Utilized for large production volume chips such as microprocessors.microprocessors.

No restriction on the placement of functional blocks No restriction on the placement of functional blocks and their interconnections.and their interconnections.

Highly optimized, but labour intensive.Highly optimized, but labour intensive.

Standard CellStandard Cell Utilized for smaller production ASICs that are Utilized for smaller production ASICs that are

generated by synthesis tools.generated by synthesis tools. Layout arranged in row of cells that perform Layout arranged in row of cells that perform

computation.computation. Routing done on “channels” between the rows.Routing done on “channels” between the rows.

Full Custom LayoutFull Custom Layout

Standard Cell LayoutStandard Cell Layout

Standard Cell LayoutStandard Cell Layout

Design StyleDesign Style

Gate ArraysGate Arrays Pre-fabricated array of gates (could be NAND).Pre-fabricated array of gates (could be NAND). Design is mapped onto the gates, and the Design is mapped onto the gates, and the

interconnections are routed.interconnections are routed. Field programmable gate arraysField programmable gate arrays

Pre-fabricated array of programmable logic and Pre-fabricated array of programmable logic and interconnections.interconnections.

No fabrication step required.No fabrication step required.

Field Programmable Gate Array Field Programmable Gate Array (FPGA)(FPGA)

Configurable Logic BlockConfigurable Logic Block

Design StyleDesign Style

Sea of gatesSea of gates Pre-fabricated sea of gates with no area for Pre-fabricated sea of gates with no area for

routing.routing. Simpler gates with very high density.Simpler gates with very high density. Routing through gates or by fabricating over Routing through gates or by fabricating over

the cell routing.the cell routing.

Design Style ComparisonsDesign Style Comparisons

STYLESTYLE

Full Full CustomCustom

Standard Standard CellCell

Gate Gate ArrayArray

FPGAFPGA

Cell sizeCell size VariableVariable Fixed Fixed heightheight

FixedFixed FixedFixed

Cell typeCell type VariableVariable VariableVariable FixedFixed Prog.Prog.

Cell placementCell placement VariableVariable In rowIn row FixedFixed FixedFixed

InterconnectionsInterconnections VariableVariable VariableVariable VariableVariable Prog.Prog.

Design costDesign cost HighHigh MediumMedium MediumMedium LowLow

Design Style ComparisonsDesign Style Comparisons

STYLESTYLE

Full Full CustomCustom

Standard Standard CellCell

Gate Gate ArrayArray

FPGAFPGA

AreaArea CompactCompact Compact to Compact to ModerateModerate

ModerateModerate LargeLarge

PerformancePerformance HighHigh High to High to ModerateModerate

ModerateModerate LowLow

FabricateFabricate All All LayersLayers

All LayersAll Layers RoutingRouting NoneNone

PackagingPackaging

Printed Circuit BoardsPrinted Circuit Boards Packaged chips are soldered on a substrate.Packaged chips are soldered on a substrate. Larger wire delays, lower integration.Larger wire delays, lower integration.

Multichip Modules (MCM)Multichip Modules (MCM) Un-packaged chips are soldered on a substrate.Un-packaged chips are soldered on a substrate. Medium wire delays, medium integration.Medium wire delays, medium integration.

Wafer Scale IntegrationWafer Scale Integration Multiple chips are fabricated on a single wafer.Multiple chips are fabricated on a single wafer. High performance, high integration, lower High performance, high integration, lower

yields.yields.

SummarySummary

VLSI Design Cycle was explained.VLSI Design Cycle was explained. PDA defined, and introduced.PDA defined, and introduced. Overview of design styles and Overview of design styles and

packaging.packaging.