Design and Implementation of Floating Point Multiplier ... · PDF filevhdl implementation of...
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VHDL IMPLEMENTATION OF FLOATING POINT MULTIPLIER BASED ON VEDIC MULTIPLICATION TECHNIQUE
PRAGATI SACHAN
M.Tech (VLSI) Scholar, Electronics and communication Engineering, Jayoti Vidyapeeth Women’s University Jaipur, Rajasthan, India, [email protected]
ABSTRACT
In this paper, IEEE floating point format was a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In that work VHDL implementation of Floating Point Multiplier using ancient Vedic mathematics is presented. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhvatriyakbhyam sutra will be used for the multiplication of Mantissa. The underflow and over flow cases will be handled. The inputs to the multiplier in 32 bit format. The multiplier is designed in VHDL or VERILOG and simulated using Modelsim.
Key words: Vedic Mathematics, Urdhva‐triyakbhyam sutra, Floating Point multiplier, FPGA.
1. INTRODUCTION
1.1 FLOATING POINT MULTIPLIER FOR IEEE FORMATE
Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise, crosswise means diagonal multiplication and vertically means straight above multiplication and taking their sum. The feature is any multi‐bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product, the efficient use of Vedic multiplication method in order to multiply two floating point numbers .This work presents an implementation of a floating point multiplier that supports the IEEE 754‐2008 binary interchange format. Based on the discussion made above it is very clear that a multiplier is a very important element in any processor design and a processor spends considerable amount of time in performing multiplication and generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. An improvement in multiplication speed by using new techniques can greatly improve system performance. In the next stage of the project the design will be designed using VHDL or VERILOG and will be simulated using Modelsim Simulator. The design will be synthesized using Xilinx ISE 12.1 tool. A test bench will be used to generate the stimulus and the multiplier operation is to be verified.The over flow and under flow flags are to incorporated in the design in order to show the over flow and under flow cases. The theory states that the efficient use of Vedic multiplication method in order to multiply two floating point numbers. That the hardware requirement is reduced, thereby reducing the power consumption. The power consumption upon reducing affectively may not compromise delay so much. Multiplication of the floating point numbers described in IEEE 754 single precision valid. Floating point multiplier
is done using VHDL.Implementation in VHDL(VHSIC Hardware Description Language) is used because it allow direct implementation on the hardware while in other language they have to convert them into HDL then only can be implemented on the hardware. In floating point multiplication, adding of the two numbers is done with the help of various types of adders but for multiplication some extra shifting is needed. This floating point multiplication handles various conditions like overflow, underflow, normalization, rounding. In this work they use IEEE rounding method for perform the rounding of the resulted number.This work focuses only on single precision normalized binary interchange format targeted for Xilinx Spartan‐3 FPGA based on VHDL. The multiplier was verified against Xilinx floating point multiplier core. It handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit.
1.2 VEDIC MULTIPLIER FOR BINARY NUMBERS
The design of high speed and area efficient Binary Number Multiplier often called Binary Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics i.e.Urdhva Tiryagbhyam Sutra. Urdhva Tiryagbhyam Sutra is the Vedic method for multiplication which strikes a difference in the actual process of multiplication itself, giving minimum delay for multiplication of all types of numbers, either small or large. The work has proved the efficiency of Binary Number Multiplier designed using Urdhva Tiryagbhyam Sutra where multiplication process enables parallel generation of intermediate products and eliminates unwanted multiplication steps. Further, the Verilog HDL coding of Urdhva Tiryagbhyam Sutra for 23x23 bits multiplication and their implementation in Xilinx Synthesis Tool on Spartan 3E kit have been done. The propagation time for the proposed architecture is 26.559 ns.The work then extends multiplication to 16×16 Vedic multiplier using "Nikhilam Sutra" technique. The 16×16
PRAGATI SACHAN et al. Volume 3 Issue 4: 2015
Citation: 10.2348/ijset07150914 Impact Factor- 3.25
ISSN (O): 2348-4098 ISSN (P): 2395-4752
International Journal of Science, Engineering and Technology- www.ijset.in 914
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VEDIC THODOLOGI
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MATHEES FOR MUL
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EMATICS LTIPLICATIO
osed which This multiplidigital signalgorithms inputations. T4 bit addier using Vedroposed multmultiplier i.e.4 multiplier caltipliers. Thisas digital sigalgorithms inurther be imed.The Vedicn Self Test) compared widelay and poigh speed aultiplication ts purpose.Hiomparing thisier and Boomented using delay report x ISE tool an
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ur 8×8 Vedve adders, ave adder in td of additionlier is coded Xilinx ISE 10d on SpartanVedic multipliter than 16xhyam Sutra” h operands a
DIFFERENON
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. METHODO
.1 VEDIC MU
SP applicatioinary floatingrovides the loating poinumbers are rhe Single conits. The forxponent andtructure of Standard. In ca3 bits and 1 xponent is rectually the Eormat and MShe sign bit is when the sign n 64 bits formhe Exponent i023 and the M
.2.1 Urdhva–
rdhva tiryakormula appliterally meanhis multiplicmultiplication he conventioequire 16 lternative mryakbhyam Se multiplied aquare as showows and coluo one of the dhus, each dommon to a dre partitioneach digit ofmultiplied witwo‐digit prodigits lying onrevious carryumber acts aor the next stne on the ext
.2 FLOATING
OLOGY
ULTIPLIER
ons essentiallg point numformat for
nt numbers. represented nsist of 32 bitrmats are cd Mantissa. Single and Dase of Single, bit is added epresented inxponent is rSB of Single i1 that meanbit is 0 that mat the Mantis representeMSB of Doubl
–TriyaKbhya
kbhyam Sutricable to als “Vertically cation scheof two decional methodmultiplicatio
method of mSutra is showare written own in the figumns where edigit of either digit of the digit of the md into two hf the multipth every digiduct is written a crosswisey. The least sias the result tep. Carry forreme right si
G POINT MUL
ly require thembers. The IEr representThe Binaryin Single andts and the Docomposed ofThe FigureDouble formthe Mantissato the MSB fn 8 bits whichrepresented iis reserved fns the numbemeans the nutissa is repreed in 11 bits wle is reserved
am (Vertical
a is a generl cases of and Crossw
eme, let umal numberds already kons and 15multiplicationwn in Fig. 1.1on two consecure. The squaeach row/cola multiplier multiplier h
multiplicand. Thalves by theplier is theit of the mulen in the come dotted line ignificant digdigit and ther the first steide) is taken t
LTIPLICATIO
e multiplicatiEEE 754 stanation of Biy Floating pd Double formuble consist f 3 fields; e 3.1 showsmats of IEEE a is representfor normalizah is biased toin excess 12for Sign bit. Wer is negativeumber is posesented in 52which is biasd for sign bit.
lly & Crossw
ral multiplicmultiplicatio
wise”. To illuss consider s (5498 × 23know to us 5 additions.n using Ur. The numbecutive sides oare is dividedumn correspor a multiplichas a small These small be crosswise len independltiplicand andmmon box. Alare added togit of the obtae rest as the cep (i.e., the doto be zero.
ON
on of ndard inary point mats. of 64 Sign, s the 754
ted in ation, o 127, 7 bit When e and sitive. bits, ed to
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. An rdhva ers to of the d into ponds cand. box
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PRAGATI SACHAN et al. Volume 3 Issue 4: 2015
Citation: 10.2348/ijset07150914 Impact Factor- 3.25
ISSN (O): 2348-4098 ISSN (P): 2395-4752
International Journal of Science, Engineering and Technology- www.ijset.in 915
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Where EA andnd B respectimultiplication he mantissa o 24 BIT by amantissas are
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ow setting upnormalizing gnificant 1) w
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9.5
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mediate resuissa by elis:
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epresentatio
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g the after
0000
result most
PRAGATI SACHAN et al. Volume 3 Issue 4: 2015
Citation: 10.2348/ijset07150914 Impact Factor- 3.25
ISSN (O): 2348-4098 ISSN (P): 2395-4752
International Journal of Science, Engineering and Technology- www.ijset.in 916
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PROPOSED D
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a0b0;
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e c1 is carry amultiplicatiowith b0.
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t step is to awith b2 and a2
3=c2+a1b2+a
ilarly the last
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w the final r4s3s2s1s0.
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) 2
DESIGN
e of Mantissaance of the Flonsigned multVedic Multipntation of thit in terms oftion system ihich describemathematicale Urdhva‐triy In this methtaneously whod fast. The mmber is showB where A = aplied with the
plied with b1ts are added t
1;
and s1 is sumn results of a
a1b1 + a0b2;
add c3 with t2 with b1.
a2b1;
t step
result of mu
first the basiave been mak has been marrysave add
a calculation Uoating Point Mtiplier for mlication technis unit. This tf speed and is based on 1es natural wal problems. Oyakbhyam suhod the partiahich itself redmethod for mwn Figure 3.4a2a1a0 and Be LSB of B:
1, and b0 is mtogether as:
m. Next step isa0 with b2, a
the multiplica
ultiplication o
ic blocks, thaade and themade by addders and then
Unit dominatMultiplier. Thultiplication nique is chostechnique givpower [6].T16 Vedic sutrays of solvingOut of these utra is suitabal products aduces delay amultiplication4. Consider tB = b2b1b0. T
multiplied wi
s to add c1 wia1 with b1 a
ation results
of A and B
at are the 2en, using theding the partn using this 4
tes his of en ves The ras g a 16 ble are nd of the The
ith
ith nd
of
is
x2 ese tial 4x4
bl32
ThbiTiAldequmpr
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ThMcostthth
AnExretwsuov
lock, 8x8 bit 2 bit Multipli
he design stait multiplier iryakbhyam lgorithm” forevelop digitauite differemultiplication,roducts.
o scale the lgorithm can considered antegers. It is bmultiplication igit multiplicdigit subtracdditions and
Fig 3.6: H
he proposedwo different cdd and Vedmultipliers. Itncrease in spe
he number oMultiplier is onsumption itructure of thhe time requhan the other
n Overflow oxponent is hespectively. Owo Exponentsubtracting thverflow occu
block, 16x16er as shown i
arts first withas shown Sutra” or
r multiplicatioal multiplier ant from t, which is t
multiplier be employedas one of thebased on the dof 2n digit
cations, one (ctions, two letwo 2n digit
Hardware R
d multiplicaticoding technidic techniquet is evident eed of the Ved
of LUTs and less and
is reduced. Ahe multiplier uired for comr multiplicatio
or Underflowigher than thOverflow mays which can bhe bias fromurs the overf
6bit block andinfigure 3.5 h
h Multiplier din figure 3.6“Vertically
on has been earchitecture. the traditioto add and
further, Kard. Karatsuba‐e fastest waysdivide and cointeger is r(n+1) digit meft shift operaadditions.
Realization o
ons were imiques viz., cone for 4, 8, that there idic architectu
slices requirdue to wh
Also the repetmakes it easmputing multon technique
w case occurshe 8 BIT or y occur durinbe compensam the exponeflow flag goe
d then finallyhas been mad
design that is6. Here, “Urand Cross
effectively usThis algorithnal methodshift the pa
ratsuba – O‐Ofman algors to multiplyonquer stratereduced to twmultiplicationations, two n
of 2x2 block
mplemented unventional sh16, and 32is a consideure.
red for the Vhich the ptitive and regier to designtiplication iss.
s when the rlower than 8ng the additioated at the timent result. Wes up. The u
y 32 x de.
s 2x2 rdhva swise ed to hm is d of artial
fman rithm y long egy. A wo n , two digit
using hift & 2 bit rable
Vedic ower gular . And s less
result 8 BIT on of me of When under
PRAGATI SACHAN et al. Volume 3 Issue 4: 2015
Citation: 10.2348/ijset07150914 Impact Factor- 3.25
ISSN (O): 2348-4098 ISSN (P): 2395-4752
International Journal of Science, Engineering and Technology- www.ijset.in 917
flowexpoand of nunde
3. SI
We hmultperfinpuhaveposi
For ‘B’ is
For c0.37also convget ‐float1101hexa
w can occur onent, it is ththis situationnormalizationer flow flag g
IMULATION
have taken twtiplicand thesform multipliuts and will be taken as tive edge of c
case I we taks ‐2.25. Here
case II we tak75. Here ‘A’ isa signed Flovert value of ‐1.1101x2^3 ting point 1000000000adecimal form
after the suhe case whenn can be handn. When the goes high.
N RESULTS
wo inputs ‘A’se are floatiner using Vedbe stored in o‘Z’ all operclock.
ke value of ‘A‘A’ is unsigne
ke value of ‘As signed floaoating Point ‘A’ to binarythen we havformat the0000000000mat we get 0
btraction of n the numberdled by addinunderflow c
’ and ‘B’ as ang point signeic Algorithm other output ations are p
A’ is 134.062ed floating pi
A’ is ‐14.5 andting pint numNumber. No
y format afterve to convertn we get 0 then con0xC1680000.
bias from tr goes belowng 1 at the timcase occur t
multiplier aed value we abetween theport which wperforming
25 and value int number a
Fig 3.1: Sim
d value of ‘B’ imber and ‘B’ow we have r normalize wt it into IEE‐1 100000
nvert it in. Now we ha
the w 0 me the
nd are ese we on
of nd
‘BcogeIE00hetowflo00hem0x30da
mulation Res
is ‐’ is to we 32 10 nto ave
towflo10hem0xfig
B’ is Signed Fonvert value et 1.0000110EE‐32 floatin0001100001exadecimal fo convert valwe get ‐1.001xoating poin0100000000exadecimal multiplication xC396D200 01.640625figata.
sult of Case I
o convert valwe get ‐1.1x2^oating poin0000000000exadecimal multiplication x40AE0000 tg 3.2 shows t
Floating Poinof ‘A’ to bina00001x2^7 thng point form0000000000format we geue of ‘B’ to bx2^1 then went format t0000000000format weusing V
the value og 3.1 shows
ue of ‘B’ to b^‐2 then we nt format t0000000000format weusing V
the value of tthe simulation
nt Number. ary format afhen we have mat then we 000 then cet 0x4306100binary formae have to convthen we ge000 then ce get 0xCVedic Multof this hexathe simulati
binary formahave to convthen we ge000 then ce get 0xBVedic Multthis hexadecin result of th
Now we havfter normalizto convert itget 0 1000convert it 00. Now we at after normvert it into IEet 1 1000convert it C0100000. iplier we decimal no. ion result of
at after normvert it into IEet 1 0111convert it BEC00000. iplier we imal no. is 5.4is data.
ve to ze we t into 0110 into have
malize EE‐32 0000 into After get is ‐
f this
malize EE‐32 1101 into After get
4375
PRAGATI SACHAN et al. Volume 3 Issue 4: 2015
Citation: 10.2348/ijset07150914 Impact Factor- 3.25
ISSN (O): 2348-4098 ISSN (P): 2395-4752
International Journal of Science, Engineering and Technology- www.ijset.in 918
For 15.5also convget float1110hexa
case III we t5. Here ‘A’ is ua unsigned Fvert value of 1.111x2^2 thting point 0000000000adecimal form
ake value of unsigned floaFloating Poin‘A’ to binaryhen we haveformat the0000000000mat we get 0
‘A’ is 7.5 andating pint nunt Number. Ny format aftere to convert n we get 0 then con0x40F00000.
Fig 3.2: Sim
d value of ‘B’mber and ‘B’Now we have r normalize wit into IEE‐0 100000
nvert it in. Now we ha
Fig 3.3: Simu
mulation Resu
’ is ’ is to we 32 01 nto ave
tow3211hemthth
ulation Resu
ult of Case II
o convert valwe get 1.11112 floating p1110000000exadecimal multiplication he value of thhe simulation
ult of Case II
I
ue of ‘B’ to b1x2^3 then wpoint format0000000000format weusing Vedic
his hexadecimn result of this
I
binary formawe have to cot then we g000 then ce get 0x4Multiplier w
mal no. is 116s data.
at after normonvert it intoget 0 1000convert it 41780000. we get 0x42E6.25 fig 3.3 sh
malize o IEE‐0010 into After 8800 hows
PRAGATI SACHAN et al. Volume 3 Issue 4: 2015
Citation: 10.2348/ijset07150914 Impact Factor- 3.25
ISSN (O): 2348-4098 ISSN (P): 2395-4752
International Journal of Science, Engineering and Technology- www.ijset.in 919
3.1 S
Fig 3we a
4. F
The by multin tiselecfurthareaoper
SYNTHESIS R
3.4 shows theattach the syn
UTURE EXP
time taken employing tiplier architeime. Dependcted by the aher extend ta. It can be rations like
RESULTS
e RTL of our nthesis repor
PECTS
for multiplicthe Vedic ecture is proding on the architecture io increase thextended toe ad‐der/s
code, fig 3.5 rt of our code
cation operatalgorithms.
posed for furinputs, the bitself. Futurehe more speo have moresubtractor,
shows the in.
Fig
Fig 3
Fig 3.6
tion is reduc. Here Vedrther reductibetter sutra e work can aleed and redue mathematicdivider a
nternal RTL a
g 3.4: Main R
3.5: Internal
6: Device Util
ced dic on is lso uce cal nd
exspsy
5
ThPoTLA
and fig 3.6 sh
RTL
l RTL
lization
xponential fupeed by usinystem perform
. CONCLUSI
his paper naoint Multipechnique” uARGE SCALE
hows the devi
unctions.An imng new techmance.
ION
med “VHDL plier basedundertook byE INTEGERA
ices utilized i
mprovementhniques can
Implementad on Vedicy the studentATION) FOU
in our work.
t in multiplicgreatly imp
ation of Floac Multiplicat of M.Tech (URTH SEMES
Here
ation prove
ating ation (VERI STER
PRAGATI SACHAN et al. Volume 3 Issue 4: 2015
Citation: 10.2348/ijset07150914 Impact Factor- 3.25
ISSN (O): 2348-4098 ISSN (P): 2395-4752
International Journal of Science, Engineering and Technology- www.ijset.in 920
under the guidance and support of our teacher.The paper shows the efficient use of Vedic multiplication method in order to multiply two floating point numbers. The lesser number of LUTs verifies that the hardware requirement is reduced, thereby reducing the power consumption.
REFERENCES
1. Manoranjan Pradhan et al, “Speed Comparison of 16x16 Vedic Multipliers” International Journal of Computer Applications (0975 – 8887) Volume 21– No.6, May 2011.
2. Brian Hickman et al, “A Parallel IEEE P754 Decimal Floating‐Point Multiplier” University of Wisconsin – Madison Dept. of Electrical and Computer Engineering Madison, WI 53706
3. IEEE 754‐2008, IEEE Standard for Floating‐Point Arithmetic, 2008.
4. Rekha K James, Poulose K Jacob, Sreela Sasi, “Decimal Floating Point Multiplication using RPS Algorithm,” IJCA Proceedings on International Conference on VLSI, Communications and Instrumentation (ICVCI): 2011.
5. Brian Hickmann, Andrew Krioukov, and Michael Schulte, Mark Erle,”A Parallel IEEE 754 Decimal Floating‐Point Multiplier,” In 25th International Conference on Computer Design ICCD, Oct. 2007.
PRAGATI SACHAN et al. Volume 3 Issue 4: 2015
Citation: 10.2348/ijset07150914 Impact Factor- 3.25
ISSN (O): 2348-4098 ISSN (P): 2395-4752
International Journal of Science, Engineering and Technology- www.ijset.in 921