M ULTIPLIERS Multipliers Booth’s Multiplier Floating Point Arithmetic.
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Transcript of M ULTIPLIERS Multipliers Booth’s Multiplier Floating Point Arithmetic.
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MULTIPLIERSMultipliers
Booth’s Multiplier
Floating Point Arithmetic
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WHY MULTIPLIERS? Used in a lot of DSP applications
Vector product, matrix multiplication Convolution Filtering (tap filters, FIR, …) ...
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“At least one good reason for studying multiplicationand division is that there is an infinite number of waysof performing these operations and hence there is aninfinite number of PhDs (or expense-paid visits toconferences in USA) to be won from inventing new formsof multiplier”
Alan ClementsThe Principles of Computer Hardware, 1986
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BASIC ARITHMETIC AND THE ALU
Now Integer multiplication
Booth’s algorithm Floating point representation Floating point addition, multiplication
Floating point are not crucial for the project
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MULTIPLICATION
Flashback to 3rd gradeMultiplierMultiplicandPartial productsFinal sum
Base 10: 8 x 9 = 72PP: 8 + 0 + 0 + 64 = 72
How wide is the result? log(n x m) = log(n) + log(m)32b x 32b = 64b result
4
1 0 0 0
x 1 0 0 1
1 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
1 0 0 1 0 0 0
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COMBINATIONAL MULTIPLIER
Generating partial products 2:1 mux based on multiplier[i] selects
multiplicand or 0x0 32 partial products (!)
Summing partial products Build Wallace tree of CSA
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COMBINATIONAL MULTIPLIER: IDEA Use an array of AND gates to generate the partial
products in parallel
LSB
LSB1 1 0
1
1
0
1 1 0
01001
multiplier
multiplicand
1 1 0
0 0 0
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COMBINATIONAL MULTIPLIER: ADDING PPRODS
HA FA FA HA
X3 X2 X1 X0Y1
X3 X2 X1 X0Y0
Z0
FA FA FA HA
X3 X2 X1 X0Y2
Z1
FA FA FA HA
X3 X2 X1 X0Y3
Z2
Z3Z4Z5Z6Z7
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COMBINATIONAL MULTIPLIER: CRITICAL PATH(S)
A lot of critical paths: same delay. (AND gates not shown)
HA FA FA HA
FA FA FA HA
FA FA FA HA
Critical Path 1
Critical Path 2
Delay=(M+N-2)tcarry+(N-1)tsum+tAND
MxNMultiplier
N
M
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COMBINATIONAL MULTIPLIER: LAYOUT
HA FA FA HA
FA FA FA HA
FA FA FA HA
Better floorplan for compact layout: Send partial product
diagonally Results in better area (AND gates and
hence the first row not shown)
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CARRY SAVE ADDER
A + B => SSave carries A + B => S, Cout
Use Cin A + B + C => S1, S2 (3# to 2# in parallel)
Used in combinational multipliers by building a Wallace Tree
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c b a
c s
CSA
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WALLACE TREE
11
abc def
CSA
CSA
CSA
CSA
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MULTICYCLE MULTIPLIERS
Combinational multipliers Very hardware-intensive Integer multiply relatively rare Not the right place to spend resources
Multicycle multipliers Iterate through bits of multiplier Conditionally add shifted multiplicand
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MULTIPLIER (F4.25)
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1 0 0 0
x 1 0 0 1
1 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
1 0 0 1 0 0 0
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MULTIPLIER (F4.26)
14Done
1. TestMultiplier0
1a. Add multiplicand to product andplace the result in Product register
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
Start
Multiplier0 = 0Multiplier0 = 1
No: < 32 repetitions
Yes: 32 repetitions
1 0 0 0
x 1 0 0 1
1 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
1 0 0 1 0 0 0
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MULTIPLIER IMPROVEMENTS Do we really need a 64-bit adder?
No, since low-order bits are not involved Hence, just use a 32-bit adder
Shift product register right on every step Do we really need a separate multiplier
register? No, since low-order bits of 64-bit product are
initially unused Hence, just store multiplier there initially
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MULTIPLIER (F4.31)
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ControltestWrite
32 bits
64 bits
Shift rightProduct
Multiplicand
32-bit ALU
1 0 0 0
x 1 0 0 1
1 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
1 0 0 1 0 0 0
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MULTIPLIER (F4.32)
17
Done
1. TestProduct0
1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register
2. Shift the Product register right 1 bit
32nd repetition?
Start
Product0 = 0Product0 = 1
No: < 32 repetitions
Yes: 32 repetitions
1 0 0 0
x 1 0 0 1
1 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
1 0 0 1 0 0 0
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SIGNED MULTIPLICATION Recall
For p = a x b, if a<0 or b<0, then p < 0 If a<0 and b<0, then p > 0Hence sign(p) = sign(a) xor sign(b)
HenceConvert multiplier, multiplicand to positive
number with (n-1) bitsMultiply positive numbersCompute sign, convert product accordingly
Or,Perform sign-extension on shifts for F4.31
designRight answer falls out
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BOOTH’S ENCODING Recall grade school trick
When multiplying by 9: Multiply by 10 (easy, just shift digits left) Subtract once
E.g. 123454 x 9 = 123454 x (10 – 1) = 1234540 –
123454 Converts addition of six partial products to one
shift and one subtraction Booth’s algorithm applies same
principleExcept no ‘9’ in binary, just ‘1’ and ‘0’So, it’s actually easier! 1
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BOOTH’S ENCODING
Search for a run of ‘1’ bits in the multiplierE.g. ‘0110’ has a run of 2 ‘1’ bits in the
middleMultiplying by ‘0110’ (6 in decimal) is
equivalent to multiplying by 8 and subtracting twice, since 6 x m = (8 – 2) x m = 8m – 2m
Hence, iterate right to left and:Subtract multiplicand from product at first
‘1’Add multiplicand to product after first ‘1’Don’t do either for ‘1’ bits in the middle
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BOOTH’S ALGORITHM
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Current bit
Bit to right
Explanation Example Operation
1 0 Begins run of ‘1’ 00001111000
Subtract
1 1 Middle of run of ‘1’
00001111000
Nothing
0 1 End of a run of ‘1’ 00001111000
Add
0 0 Middle of a run of ‘0’
00001111000
Nothing
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BOOTH’S ENCODING
Really just a new way to encode numbers Normally positionally weighted as 2n
With Booth, each position has a sign bit Can be extended to multiple bits
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0 1 1 0 Binary+1 0 -1 0 1-bit Booth+2 -2 2-bit Booth
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BOOTH’S EXAMPLE
Negative multiplicand: -6 x 6 = -361010 x 0110, 0110 in Booth’s encoding is +0-0Hence:
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1111 1010 x 0 0000 0000
1111 0100 x –1 0000 1100
1110 1000 x 0 0000 0000
1101 0000 x +1 1101 0000
Final Sum: 1101 1100 (-36)
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BOOTH’S EXAMPLE
Negative multiplier: -6 x -2 = 121010 x 1110, 1110 in Booth’s encoding is 00-0Hence:
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1111 1010 x 0 0000 0000
1111 0100 x –1 0000 1100
1110 1000 x 0 0000 0000
1101 0000 x 0 0000 0000
Final Sum: 0000 1100 (12)
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MODIFIED BOOTH
Booth 2 modified to produce at most n/2+1 partial products.
Algorithm: (for unsigned numbers)1. Pad the LSB with one zero.2. Pad the MSB with 2 zeros if n is even and 1
zero if n is odd.3. Divide the multiplier into overlapping groups
of 3-bits.4. Determine partial product scale factor from
modified booth 2 encoding table.5. Compute the Multiplicand Multiples6. Sum Partial Products
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Spring 2006EE 5324 - VLSI Design II - © Kia Bazargan 26
MODIFIED BOOTH MULTIPLIER: IDEA (CONT.)
Can encode the digits by looking at three bits at a time
Booth recoding table: Must be able to add
multiplicand times –2, -1, 0, 1 and 2
Since Booth recoding got rid of 3’s, generating partial products is not that hard (shifting and negating)
i+1 i i-1 add
0 0 0 0*M 0 0 1 1*M 0 1 0 1*M 0 1 1 2*M 1 0 0 –2*M 1 0 1 –1*M 1 1 0 –1*M 1 1 1 0*M
[©Hauck]
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MODIFIED BOOTH
Example: (n=4-bits unsigned)1. Pad LSB with 1 zero
2. n is even then pad the MSB with two zeros
3. Form 3-bit overlapping groups for n=8 we have 5 groups
Y3
Y2
Y1
Y0
Y3
Y2
Y1
Y0
0
0
Y3
Y2
Y1
Y0
0
0 1 0 0 0
Y7
Y6
Y5
Y4
Y7
Y6
Y5
Y4
0 0 0 1
Y7
Y6
Y5
Y4
00
00
00
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2-BITS/CYCLE MODIFIED BOOTH MULTIPLIER For every pair of multiplier bits
If Booth’s encoding is ‘-2’ Shift multiplicand left by 1, then subtract
If Booth’s encoding is ‘-1’ Subtract
If Booth’s encoding is ‘0’ Do nothing
If Booth’s encoding is ‘1’ Add
If Booth’s encoding is ‘2’ Shift multiplicand left by 1, then add
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2 BITS/CYCLE MODIFIED BOOTH’S
29
Current
Previous
Operation Explanation
00 0 +0;shift 2 [00] => +0, [00] => +0; 2x(+0)+(+0)=+0
00 1 +M; shift 2 [00] => +0, [01] => +M; 2x(+0)+(+M)=+M
01 0 +M; shift 2 [01] => +M, [10] => -M; 2x(+M)+(-M)=+M
01 1 +2M; shift 2
[01] => +M, [11] => +0; 2x(+M)+(+0)=+2M
10 0 -2M; shift 2
[10] => -M, [00] => +0; 2x(-M)+(+0)=-2M
10 1 -M; shift 2 [10] => -M, [01] => +M; 2x(-M)+(+M)=-M
11 0 -M; shift 2 [11] => +0, [10] => -M; 2x(+0)+(-M)=-M
11 1 +0; shift 2 [11] => +0, [11] => +0; 2x(+0)+(+0)=+0
1 bit Booth
00 +0
01 +M;
10 -M;
11 +0
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WALLACE TREE: IDEA
Idea: divide & conquer Why add the k numbers one by one?
Tree structure logarithmic
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .. . . . . .
. . . . . .. . . . . .
. . . . . .
. . . . . . . . . . . . . . . . . .
. . . . . .
. . . . . .
. . . . . .. . . . . .
. . . . . .
. . . . . .
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Sprin
g 2
00
6WALLACE TREE EXAMPLE
Delay = 4 CSA + 1 CLA
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WALLACE TREE: STRUCTURE FOR 7 K-BIT NUMBERS
[0,k-1] [0,k-1] [0,k-1] [0,k-1]
[1,k][0,k-1]
[1,k] [0,k-1]
K-bit CSA K-bit CSA
[1,k][0,k-1]
K-bit CSA
[2,k+1] [1,k]
K-bit CSA
[2,k+1] [1,k+1]
K-bit CSA
[0,k-1] [0,k-1] [0,k-1]
[1,k-1], ‘0’
K-bit CPA
[0][1]
[2,k+1]
[2,k+1][k+2]
‘0’,[2,k]
[k+1]
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At each step, # of operands reduces to 2/3
WALLACE TREE: TIMING
CSA CSA CSA CSA CSA CSA
CSA CSA CSA CSA
CSA CSA CSA
CSA CSA
n k-bit numbersn k-bit numbers
(2/3) nnums
(2/3) nnums
CSA CSA CSA CSA(2/3)2 n(2/3)2 n
CSA
. . .
(2/3)h n = 2(2/3)h n = 2
h levels
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WALLACE TREE: TIMING (CONT.) Delay depends on height h h = O ( log n ) Logarithmic delay
Max # N of k-bit numbers that can be addedusing a Wallace tree of height h
h N h N h N
0 2 7 28 14 474
1 3 8 42 15 711
2 4 9 63 16 1066
3 6 10 94 17 1599
4 9 11 141 18 2398
5 13 12 211 19 3597
6 19 13 316 20 5395
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FLOATING POINT35
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FLOATING POINT Want to represent larger range of numbers
Fixed point (integer): -2n-1 … (2n-1 –1) How? Sacrifice precision for range by
providing exponent to shift relative weight of each bit position
Similar to scientific notation:3.14159 x 1023
Cannot specify every discrete value in the range, but can span much larger range
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FLOATING POINT
Still use a fixed number of bits Sign bit S, exponent E, significand F Value: (-1)S x F x 2E
IEEE 754 standard
37
Size Exponent
Significand
Range
Single precision
32b 8b 23b 2x10+/-38
Double precision
64b 11b 52b 2x10+/-308
S E F
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FLOATING POINT EXPONENT Exponent specified in biased or excess
notation Why?
To simplify sorting Sign bit is MSB to ease sorting 2’s complement exponent:
Large numbers have positive exponent Small numbers have negative exponent
Sorting does not follow naturally
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EXCESS OR BIASED EXPONENT
Value: (-1)S x F x 2(E-bias)
SP: bias is 127DP: bias is 1023 3
9
Exponent 2’s Compl Excess-127
-127 1000 0001 0000 0000
-126 1000 0010 0000 0001
… … …
+127 0111 1111 1111 1110
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FLOATING POINT NORMALIZATION S,E,F representation allows more than
one representation for a particular value, e.g. 1.0 x 105 = 0.1 x 106 = 10.0 x 104
This makes comparison operations difficultPrefer to have a single representation
Hence, normalize by convention:Only one digit to the left of the floating
point In binary, that digit must be a 1
Since leading ‘1’ is implicit, no need to store it Hence, obtain one extra bit of precision for free 4
0
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FP OVERFLOW/UNDERFLOW
FP OverflowAnalogous to integer overflowResult is too big to representMeans exponent is too big
FP UnderflowResult is too small to representMeans exponent is too small (too negative)
Both can raise an exception under IEEE754
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IEEE754 SPECIAL CASES
42
Single Precision Double Precision Value
Exponent Significand
Exponent Significand
0 0 0 0 0
0 nonzero 0 nonzero denormalized
1-254 anything 1-2046 anything fp number
255 0 2047 0 infinity
255 nonzero 2047 nonzero NaN (Not a Number)
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FP ROUNDING
Rounding is importantSmall errors accumulate over billions of
ops FP rounding hardware helps
Compute extra guard bit beyond 23/52 bitsFurther, compute additional round bit
beyond that Multiply may result in leading 0 bit, normalize
shifts guard bit into product, leaving round bit for rounding
Finally, keep sticky bit that is set whenever ‘1’ bits are “lost” to the right Differentiates between 0.5 and 0.500000000001
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FLOATING POINT ADDITION
Just like grade school First, align decimal points Then, add significands Finally, normalize result
Example
44
9.997 x 102 9.997000 x 102
4.631 x 10-1 0.004631 x 102
Sum 10.001631 x 102
Normalized 1.0001631 x 103
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FP ADDER (F4.45)
45
0 10 1 0 1
Control
Small ALU
Big ALU
Sign Exponent Significand Sign Exponent Significand
Exponentdifference
Shift right
Shift left or right
Rounding hardware
Sign Exponent Significand
Increment ordecrement
0 10 1
Shift smallernumber right
Compareexponents
Add
Normalize
Round
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FP MULTIPLICATION Sign: Ps = As xor Bs Exponent: PE = AE + BE
Due to bias/excess, must subtract biase = e1 + e2E = e + 1023 = e1 + e2 + 1023E = (E1 – 1023) + (E2 – 1023) + 1023E = E1 + E2 –1023
Significand: PF = AF x BFStandard integer multiply (23b or 52b +
g/r/s bits)Use Wallace tree of CSAs to sum partial
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FP MULTIPLICATION
Compute sign, exponent, significand Normalize
Shift left, right by 1 Check for overflow, underflow Round Normalize again (if necessary)
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