Design and Implementation of an SDR receiver for the VHF band

8/9/2019 Design and Implementation of an SDR receiver for the VHF band

1/103

Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

Design and Implementation of an SDR receiver forthe VHF band

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan i Linköping

av

Emad Athari & Petter Lerenius

LITH-ISY-EX--07/3946--SE

Linköping 2007

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping


2/103


3/103

Design and Implementation of an SDR receiver forthe VHF band

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköpingav



Handledare: Per LöwenborgISY, Linköpings universitet

Jonas NilssonSignal Processing Devices Sweden AB

Examinator: Per LöwenborgISY, Linköpings universitet

Linköping, 31 January, 2007


4/103


5/103

Avdelning, Institution

Division, Department

ElektroniksystemDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

Datum

Date

2007-01-31

Språk

Language

Svenska/Swedish

Engelska/English

Rapporttyp

Report category

Licentiatavhandling

Examensarbete

C-uppsats

D-uppsats

Övrig rapport

URL för elektronisk version

http://www.es.isy.liu.sehttp://www.ep.liu.se/2007/3946

ISBN

—

ISRN


Serietitel och serienummer

Title of series, numberingISSN

—

TitelTitle

Design och implementation av en SDR-mottagare för VHF-bandet

Design and Implementation of an SDR receiver for the VHF band

FörfattareAuthor


Sammanfattning

AbstractThe purpose of this thesis work is to examine the possibility of building a software-defined radio (SDR) for the VHF-band. The goal is to accomplish this with as fewcomponents as possible, thus cutting down the size and the production cost.

An SDR solution means that the sampling of the signal is done as close to theantenna as possible. The wide bandwidth needed in such a product is achievedby using SP Devices algorithm for time-interleaved ADCs. Two hardware proto-types and two versions of the software were designed and implemented using thistechnology.

They were also analyzed within this thesis work. The results proved to be good,and the possibilities to produce a commercial software-defined radio receiver forthe VHF-band are good.

Nyckelord

Keywords SDR, software-defined radio, radio, GMSK, receiver, FPGA


6/103


7/103

Abstract

The purpose of this thesis work is to examine the possibility of building a software-defined radio (SDR) for the VHF-band. The goal is to accomplish this with as fewcomponents as possible, thus cutting down the size and the production cost.

An SDR solution means that the sampling of the signal is done as close to theantenna as possible. The wide bandwidth needed in such a product is achievedby using SP Devices algorithm for time-interleaved ADCs. Two hardware proto-types and two versions of the software were designed and implemented using thistechnology.

They were also analyzed within this thesis work. The results proved to be good,and the possibilities to produce a commercial software-defined radio receiver forthe VHF-band are good.

Sammanfattning

Syftet med det här examensarbetet är att utreda möjligheten att bygga en mjuk-varudefinierad radiomottagare (SDR) för VHF-bandet. Målet är att göra dettagenom att använda så få komponenter som möjligt, och därigenom minska stor-leken och produktionskostnaden.

En SDR lösning ger att samplingen kommer att ske så nära antennen sommöjligt. Den stora bandbredd som behövs för en sådan produkt uppnås genomatt använda SP Devices algoritm för att ”tidsinterleava” höghastighets ADC:er.Två hårdvaruprototyper och två versioner av mjukvaran har designats och imple-menterats.

Analyserna har visat bra resultat, och möjligheterna att bygga en komersiellmjukvarudefinierade radiomottagare för VHF-bandet ses som goda.

v


8/103


9/103

Acknowledgments

The completion of this thesis had not been possible without the help and supportthat we have received throughout this work. Therefore we would like to thank thepeople the persons that has made this possible.

Firstly we would like to thank our supervisors Per Löwenborg, at the Divisionof Electronics Systems at Linköping University, and Jonas Nilsson, at SP Devices,for their enormous support and for believing in us.

We would also like to thank all of the personnel at SP Devices and Peter,Christian, Marcus and Anders for great help and support.

Last but not least we would like to thank our families and friends for theirendless love and support.

vii


10/103


11/103

Abbreviations

ACK AcknowledgementAD Analog-to-DigitalADC Analog-to-Digital ConverterAGC Automatic Gain ControlBB BasebandBER Bit Error RateBPF Bandpass FilterBW BandwidthBWch Channel BandwidthDAC Digital-to-Analog ConverterdB DecibeldBc Decibel relative to the carrier

dBFS Decibel relative to Full Scale RangedBm Decibel relative to 1 mWDC Direct CurrentDDS Direct Digital SythesisDSP Digital Signal ProcessingDR Dynamic RangeEMC Electromagnetic CompatibilityENOB Effective Number of BitsFFT Fast Fourier TransformFIR Finite length Impulse Response

FPGA Field-Programmable Gate ArrayFSR Full Scale RangeGMSK Gaussian Minimum Shift KeyingHDLC High Level Data Link ControlIF Intermediate FrequencyIP3 Third-Order Intercept PointIIP3 Third-Order Input Intercept PointIMD Intermodulation DistortionIMD3 Third-Order Intermodulation DistortionIQ In phase and Quadrature

IR Image RejectionLNA Low Noise AmplifierLO Local Oscillator

ix


12/103

x

LPF Lowpass FilterLSB Least Significant BitMAC Multiply and AccumulateNF Noise Figure

NRZ Non Return to ZeroNRZI Non Return to Zero InvertedOIP3 Third-Order Output Intercept PointPER Packet Error RatePG Process GainRF Radio FrequencySAW Surface Acustic WaveSDR Software Defined RadioSFDR Spurious-Free Dynamic RangeSNDR Signal-to-Noise and Distortion Ratio

SNR Signal-to-Noise RationSNRreq SNR requiredv4 Xilinx virtex 4v5 Xilinx virtex 5VGA Variable Gain AmplifierVHF Very High Frequency


13/103

Contents

1 Introduction 11.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Purpose and Method . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.4.1 Protel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.2 Matlab and Simulink . . . . . . . . . . . . . . . . . . . . . . 21.4.3 Xilinx ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.4 Microsoft Visual Studio . . . . . . . . . . . . . . . . . . . . 2

1.5 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.6 Report Disposition . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.7 Reading Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Linearizer 52.1 Problems with Interleaved ADCs . . . . . . . . . . . . . . . . . . . 5

2.1.1 Gain Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . 62.1.2 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.3 Time-Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 The Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Superheterodyne vs. SDR 113.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Traditional Superheterodyne RF Receiver . . . . . . . . . . . . . . 113.2.1 Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2.2 Disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 Software-Defined Radio Receiver . . . . . . . . . . . . . . . . . . . 133.3.1 Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3.2 Disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Basic RF Receiver Concepts 154.1 Signal-to-Noise Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . 154.2 Receiver Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3 Intermodulation Distortion & Intercept Point . . . . . . . . . . . . 164.4 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.5 Spurious-Free Dynamic Range . . . . . . . . . . . . . . . . . . . . . 18

xi


14/103

xii Contents

4.6 Effective Number of Bits . . . . . . . . . . . . . . . . . . . . . . . . 184.7 Oversampling in Analog-to-Digital

Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Requirements 215.1 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.2 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.3 Intermodulation Response Rejection and

Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.4 Adjacent Channel Selectivity . . . . . . . . . . . . . . . . . . . . . 225.5 Signal-to-Noise Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6 Analog Front-End 256.1 Front-End Architecture . . . . . . . . . . . . . . . . . . . . . . . . 256.2 Choise of Components . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.2.1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.2.2 LNA and VGA . . . . . . . . . . . . . . . . . . . . . . . . . 276.2.3 Analog Filters . . . . . . . . . . . . . . . . . . . . . . . . . 286.2.4 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.2.5 USB-to-UART Interface . . . . . . . . . . . . . . . . . . . . 316.2.6 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.2.7 Crystal Oscillator and Clock Buffer . . . . . . . . . . . . . . 326.2.8 Linear Voltage Regulators . . . . . . . . . . . . . . . . . . . 32

6.3 Theoretical Calculations . . . . . . . . . . . . . . . . . . . . . . . . 34

6.3.1 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.3.2 IMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366.4 PCB and EMC[13] . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7 Data Packets 397.1 The Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1.1 Training Sequence . . . . . . . . . . . . . . . . . . . . . . . 407.1.2 Start Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.1.3 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.1.4 Frame Check Sequence . . . . . . . . . . . . . . . . . . . . . 41

7.2 Bit Stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417.3 NRZI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417.4 GMSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.4.1 Gaussian filter . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 FPGA 438.1 Hardware Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.1.1 DSP-slices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448.2 First Attempt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.2.1 Linearizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.2.2 First Decimation . . . . . . . . . . . . . . . . . . . . . . . . 468.2.3 I - Q Modulation . . . . . . . . . . . . . . . . . . . . . . . . 468.2.4 Second Decimation . . . . . . . . . . . . . . . . . . . . . . . 47


15/103

Contents xiii

8.2.5 Third Decimation . . . . . . . . . . . . . . . . . . . . . . . 478.2.6 Phase Differentiator . . . . . . . . . . . . . . . . . . . . . . 488.2.7 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488.2.8 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.2.9 DAC Controller . . . . . . . . . . . . . . . . . . . . . . . . . 498.3 Second attempt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498.3.1 Linearizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498.3.2 IQ-modulation . . . . . . . . . . . . . . . . . . . . . . . . . 498.3.3 Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . 518.3.4 Phase Differentiator . . . . . . . . . . . . . . . . . . . . . . 578.3.5 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.3.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 578.3.7 DAC Controller . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.4 Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.4.1 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.4.2 Word Length . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9 PC 619.1 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619.2 Matlab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.2.1 Symbol Syncronization . . . . . . . . . . . . . . . . . . . . . 619.2.2 Decode NRZI . . . . . . . . . . . . . . . . . . . . . . . . . . 639.2.3 Extraction of the Data . . . . . . . . . . . . . . . . . . . . . 63

10 Tests and Results 6510.1 Filter Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.1 Board 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6510.1.2 Board 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.2 External LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6610.3 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.3.1 Variable Gain - Fixed Signal Level . . . . . . . . . . . . . . 6710.3.2 Fixed Gain - Variable Signal Level . . . . . . . . . . . . . . 68

10.4 Sensitivity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.4.1 Board 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7010.4.2 Board 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7210.5 Blocking Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7210.6 Intermodulation Test . . . . . . . . . . . . . . . . . . . . . . . . . . 7410.7 Adjacent Channel Selectivity . . . . . . . . . . . . . . . . . . . . . 7510.8 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11 Conclusions and Future Work 7711.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.1.1 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.1.2 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7811.1.3 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7811.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79


16/103

xiv Contents

References 81


17/103

Contents xv

List of Figures

2.1 Effect of problems that occur when interleaving ADCs. . . . . . . . 52.2 Result of a gain error in an ADC. . . . . . . . . . . . . . . . . . . . 72.3 Result of an offset error in an ADC. . . . . . . . . . . . . . . . . . 72.4 Result of time-skew in an ADC. . . . . . . . . . . . . . . . . . . . . 82.5 The block diagram of the linearizer . . . . . . . . . . . . . . . . . . 82.6 Interleaved sequencies with missmatch, before and after linearization. 9

3.1 Superheterodyne receiver architecture . . . . . . . . . . . . . . . . 11

4.1 Intercept Points/1-dB Compression Points . . . . . . . . . . . . . . 17

6.1 The architecture of the analog front-end. . . . . . . . . . . . . . . . 256.2 BPF1 - 1st order bandpass filter. . . . . . . . . . . . . . . . . . . . 29

6.3 BPF2 - 2nd order bandpass filter. . . . . . . . . . . . . . . . . . . . 296.4 BPF1 - 1st order bandpass filter. . . . . . . . . . . . . . . . . . . . 306.5 The configuration for IMD measurements. . . . . . . . . . . . . . . 36

7.1 Block schematic for the modulation. . . . . . . . . . . . . . . . . . 397.2 A packet’s different components. . . . . . . . . . . . . . . . . . . . 397.3 The training sequence before and after NRZI encoding. . . . . . . 407.4 An example bit stream which has been bit stuffed. . . . . . . . . . 417.5 An example bit stream encoded with NRZI . . . . . . . . . . . . . 41

8.1 DSP48-slice in virtex 4. . . . . . . . . . . . . . . . . . . . . . . . . 448.2 DSP48E-slice in virtex 5. . . . . . . . . . . . . . . . . . . . . . . . 458.3 System overview for the first attempt. . . . . . . . . . . . . . . . . 458.4 The frequency response for the first decimation filter. . . . . . . . . 468.5 Impulse response for the second decimation filter. . . . . . . . . . . 478.6 Impulse response for the third decimation filter. . . . . . . . . . . . 488.7 System overview for the second attempt. . . . . . . . . . . . . . . . 508.8 The difference between the two DDS blocks. . . . . . . . . . . . . . 518.9 The frequency response for the complete decimation filter. . . . . . 52

8.10 A zoomed in portion of the frequency response in Figure 8.9. . . . 528.11 Impulse response for the first decimation filter. . . . . . . . . . . . 538.12 Impulse response for the filter h2 . . . . . . . . . . . . . . . . . . . 538.13 Impulse response for the filter h3. . . . . . . . . . . . . . . . . . . . 548.14 Impulse response for the filter h4 . . . . . . . . . . . . . . . . . . . 548.15 Impulse response for the filter h5. . . . . . . . . . . . . . . . . . . . 558.16 Impulse response for the filter h6. . . . . . . . . . . . . . . . . . . . 558.17 Impulse response for the filter h7. . . . . . . . . . . . . . . . . . . . 568.18 Impulse response for the filter h8. . . . . . . . . . . . . . . . . . . . 56

9.1 The impulse response for the correlation filter. . . . . . . . . . . . 629.2 An example output from the correlation filter. . . . . . . . . . . . . 629.3 Zoomed in on the detected message. . . . . . . . . . . . . . . . . . 63


18/103

xvi Contents

9.4 An example bit stream decoded from NRZI. . . . . . . . . . . . . . 63

10.1 Frequency response for board 1. . . . . . . . . . . . . . . . . . . . . 6610.2 Frequency response for board 2. . . . . . . . . . . . . . . . . . . . . 6610.3 Setup for SNR test, without and with external LNA. . . . . . . . . 6710.4 The setup for the sensitivity test for board 1. . . . . . . . . . . . . 7010.5 The setup for the sensitivity test for board 1 with LNA. . . . . . . 7110.6 The setup for the sensitivity test for board 2. . . . . . . . . . . . . 7210.7 The setup for the sensitivity test for board 2 with LNA. . . . . . . 7210.8 The setup for the blocking test. . . . . . . . . . . . . . . . . . . . . 7310.9 Plot from the IMD3 test on board 2. . . . . . . . . . . . . . . . . . 74


19/103

List of Tables

2.1 Time-interleaved ADC matching requirements at 180 MHz clockfrequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.1 SNR requirement at different sampling frequencies. . . . . . . . . . 276.2 Properties for the VGA. . . . . . . . . . . . . . . . . . . . . . . . . 286.3 Component values for the analog bandpass filters. . . . . . . . . . . 316.4 Current consumption of the first PCB . . . . . . . . . . . . . . . . 326.5 Current consumption of the second PCB . . . . . . . . . . . . . . . 33

7.1 Packet components and their sizes. . . . . . . . . . . . . . . . . . . 40

8.1 L2-norm scaling of the decimation filters. . . . . . . . . . . . . . . 588.2 SNR for different word lengths. . . . . . . . . . . . . . . . . . . . . 59

10.1 Properties for the external LNA. . . . . . . . . . . . . . . . . . . . 6710.2 SNR for a -70dBm signal without and with external LNA on board 1. 6810.3 SNR for a -70dBm signal without and with external LNA on board 2. 6810.4 SNR for various signal levels without and with external LNA on

board 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910.5 SNR for various signal levels without and with external LNA on

board 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910.6 Sensitivity test using PCB 1. . . . . . . . . . . . . . . . . . . . . . 7010.7 Sensitivity test using PCB 1 with external LNA. . . . . . . . . . . 71

10.8 Sensitivity test using PCB 2. . . . . . . . . . . . . . . . . . . . . . 7210.9 Sensitivity test using PCB 2 with external LNA. . . . . . . . . . . 7310.10IMD test performed on board 2. . . . . . . . . . . . . . . . . . . . 74

11.1 Results from the tests . . . . . . . . . . . . . . . . . . . . . . . . . 77


20/103

xviii Contents


21/103

Chapter 1

Introduction

1.1 Background

Signal Processing Devices Sweden AB (SP Devices) was started in 2003, withan algorithm that solves the problems that occur when time-interleaving highprecision ADCs. The algorithm was a result of research done by Håkan Johanssonand Per Löwenborg at Linköping University.

The possibility of time-interleaving ADCs opens up many new fields for digi-talization. For example, with two 14-bit time-interleaved ADCs, sampling speedsof above 400 MSps can be achieved. This means that the Nyquist criterion can bemet for a 200 MHz bandwidth.

The field of software-defined radios (SDR) is a big research area. The SDRcan revolutionize the market of radio receivers. They are much more flexible andin some cases cheaper to produce than todays receivers.

The goal with this thesis is to show that SP Devices’ algorithm applied ontwo ADCs can be used to build a software-defined radio receiver for the VHF-band (112-174 MHz) with as few components as possible. This thesis work wasconducted at SP Devices in Linköping.

1.2 Purpose and Method

The purpose of this thesis is to design, implement and analyze a prototype of a software-defined radio for the VHF frequencies 112-174 MHz from idea all theway to a working prototype. The SDR architechture will be compared with thesuperheterodyne receiver architechture, which is commonly used today.

During this work an incremental method of development will be used. Byimproving the design in small steps, the work will advance in steps that are easilycontrolled. This will be achieved by first building a model of the SDR in Matlab

and then implement it as a prototype in two steps.Two versions of both the hardware and the software will be completed duringthe thesis. This will make it possible to make an attempt and then refine it

1


22/103

2 Introduction

and correct possible errors. The two versions are analyzed and their performancemeasured and compared.

1.3 Prerequisites

To grasp this thesis the reader should have some previous knowledge of electronicsand concepts like field-programmable gate arrays (FPGAs). Also some under-standing of digital signal processing and radio technology could be useful.

1.4 Tools

During the work of this thesis some software tools have been used to complete thetasks of building a prototype. Here follows a description of the programs used and

a description of their purpose.

1.4.1 Protel

Protel is a CAD program for designing printed circuit boards (PCB) and it alsoprovides the possibility to do simulations on schematic level.

The schematic of the front-end architechture was drawn and simulated beforethe PCB was designed. The PCB was then routed by hand before it was sent formanufacturing at Elprint1.

1.4.2 Matlab and Simulink

Matlab and Simulink was used to make a model of the system and to predict itsbehavior. Matlab is convenient to use when dealing with simulations of digitalprocessing. For simulations of the analog parts it is better to use Protel.

Matlab was also used for the decoding process and to present the results duringthe performance tests.

1.4.3 Xilinx ISE

Xilinx ISE is an integrated development environment (IDE) for Xilinx FPGAs. Ittranslates, synthesizes and routes the Verilog or VHDL code onto the designatedFPGA. In this project only Verilog was used. ISE is easy to work with and allowscode modules to be in different files, which makes the development process mucheasier. It is free if developing for Xilinx Virtex 4 FPGAs, but needs a license whenusing a Xilinx Virtex 5.

1.4.4 Microsoft Visual Studio

C code was written to produce a dynamically linked library (dll) file used bymatlab to fetch data from the usb port. It was written and compiled in the

1http://www.elprint.se


23/103

1.5 Restrictions 3

Microsoft Visual Studio environment. Visual Studio is Microsoft’s IDE for C,C++ and many more languages.

1.5 Restrictions

This thesis work will produce a prototype for decoding a specific kind of digitalmessages that are modulated with GMSK. No other modulations will be treatedor discussed. This report analyzes the prototypes designed and it will not coverany other solutions.

1.6 Report Disposition

This report will present the work performed during this thesis and its results. The

first chapters cover the more theoretical parts while the later chapters describe thework and the results.

Chapter 2 explains the problems that come up when time-interleaving ADCs,and the solution that SP Devices has developed. Chapter 3 will explain moreabout how SDR works and what the advantages are compared to the commonsuperheterodyne receivers that are commonly used today. It is followed by Chapter4 that discusses the parameters of a receiver performance, while Chapter 5 presentsthe requirements for this project.

The work performed in this thesis will then be presented. It starts with thePCB and its analog front-end in Chapter 6. The data packages that are used for

testing the receivers’ performance is explained in Chapter 7. It is followed by thedescription of the digital signal processing performed in the FPGA in Chapter 8and the PC in Chapter 9.

The tests and their results are described in Chapter 10. Finally the conclusionsmade in this thesis are presented in Chapter 11 together with some ideas of howto continue with this work.

1.7 Reading Instructions

Those who have good knowledge in electronics and radio technologies could skipthe first theoretical chapters, except for Chapter 5 which could be good to haveread to understand the decisions made in Chapter 6.

The most interesting chapter is probably Chapter 10 where the results arepresented.


24/103

4 Introduction


25/103

Chapter 2

Linearizer

To achieve high speed analog-to-digital conversion, time-interleaving multiple ADCsseems to be a good solution. This has been used for low resolution ADCs since1980, but higher resolutions matching problems deteriorate the quality of the sig-nal.

An 8-bit system that provides a dynamic range of 50 dB can tolerate a gainmismatch of 0.25% and a clock-skew error of 5 ps. This accuracy can be met bytraditional methods like, matching the physical channel layouts, using commonADC reference voltages, prescreening devices, and active analog trimming, butthis is not enough for higher resolutions[10].

The problems that need to be considered when ADCs are interleaved are shownin figure 2.1 were four ADCs have been time interleaved.

In this chapter the problems caused by interleaving will be discussed and thenSP Devices’ algorithm for solving these problems will be presented.

Resulting digital signalDesired digital signal

Figure 2.1. Effect of problems that occur when interleaving ADCs.

2.1 Problems with Interleaved ADCs

There are three main categories of problems that arise when ADCs are interleaved.They all come from the fact that it is impossible to manufacture two silicon chips

5


26/103

6 Linearizer

that are identical. The surrounding environment also affects how well the ADCsmatch, e.g., if they have different temperature. This results in differences in gain,offset and timing, which affects the output in a way depicted by the Figure 2.1.For narrowband signals, there will be unwanted spurious frequencies in the output

signal, called spurs.

IS gain(dB) = 20 log(IS gain) = 20 log

Ge2

(2.1)

Ge = gain error ratio =

1 − V FSAV FSB (2.2)

IS phase(dB) = 20 log(IS phase) = 20 log

θep

2

(2.3)

θep = ωa∆te(radians) (2.4)ωa = analog input frequency (2.5)

∆te = clock skew error (2.6)

IS tot(dB) = 20 log

(IS gain)2 + (IS phase)2

(2.7)

From equations 2.1 - 2.7 it is possible deduce that even very small divergencesbetween the ADCs will result in large spurs that will deteriorate the dynamic range.Table 2.1 shows the matching requirements for a time-interleaved system[10].

Number of bits SFDR Gain Matching Aperture Matching(dBc) (%) (fs)

12 74 0.04 012 74 0 35012 74 0.02 30014 86 0.01 014 86 0 8814 86 0.005 77

Table 2.1. Time-interleaved ADC matching requirements at 180 MHz clock frequency.

2.1.1 Gain Mismatch

The gain error cause the ADC to affect the output by changing the signal am-plitude. As seen in Figure 2.2, this would not affect the signal noticeably if onlyone ADC was used, but when two ADCs are interleaved it will result in aliasing

distortion. The differences in gain between two ADCs affects the output even if itis as small as 0.01%, as shown in equations 2.1 and 2.2. The spurs deteriorate thesignal quality, or destroy the wanted signal if they coincide.


27/103

2.1 Problems with Interleaved ADCs 7

Gain error

Figure 2.2. Result of a gain error in an ADC.

2.1.2 Offset Error

An ADC has a small DC offset in its output, and when using two ADCs they willhave different offsets. When two ADCs are time-interleaved different offsets willresult in a spur at π. The figure 2.3 shows an exaggerated offset error.

Offset error

Offset

Figure 2.3. Result of an offset error in an ADC.

2.1.3 Time-Skew

Time-skew errors, or phase errors, arise when the ADC’s samples are taken at thewrong instants in time. When more than one ADC samples the signal the time-

skew will be experienced as a phase error. This will cause aliasing distortion thatcoincide with the gain error[10]. The time-skew is depicted in Figure 2.4, wherethe samples are taken with a delay in time.


28/103

8 Linearizer

Time skew

Figure 2.4. Result of time-skew in an ADC.

2.2 The Solution

SP Devices has developed a clever algorithm, called linearizer, that corrects theseerrors by filtering the digital result. Figure 2.5 shows a block diagram of thelinearizer.

ADC 1

ADC 2

Reconstructor

Estimator

Monitor

&

Control

Linearizer

Figure 2.5. The block diagram of the linearizer

The linearizer is purely digital and uses advanced signal processing algorithmsto correct the errors mentioned in the previous section. Since the correction isdone digitally it can function with any ADC. The linearizer could also be used toincrease the resolution while maintaining the speed.

The estimator uses a batch of data to estimate the different errors. Theseestimates are used for calculating the filter coefficient values. The coefficients arethen passed on to the reconstructor. The reconstructor block consists of a filterthat corrects the errors from the differencies in the ADCs in real time.

By using the linearizer, as depicted in Figure 2.6 it is possible to construct veryfast ADCs with high performance, that opens up many new possibilities in fieldspreviously not conceivable. The software-defined radio developed in this thesis is


29/103

2.2 The Solution 9

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

Linearizer

Figure 2.6. Interleaved sequencies with missmatch, before and after linearization.

just one example made possible by the linearizer.


30/103

10 Linearizer


31/103

Chapter 3

Superheterodyne vs. SDR

3.1 Introduction

This chapter will explain the pros and cons of the commonly used superheterodyneradio frequency (RF) receiver and a software-defined radio (SDR) receiver. It alsocovers the differences between the two types and why the SDR receiver togetherwith SP Devices’ technology is preferred in a broadband RF receiver where smallarea, low power consumption and low cost are the main requirements.

3.2 Traditional Superheterodyne RF Receiver

One of the most common RF receiver architecture types used in radio applicationsfor the last century and today is the superheterodyne receiver. This receiver typeis often preferred because of its great performance regarding receiver character-istics such as sensitivity and selectivity. A simple description of the traditionalsuperheterodyne architecture can be seen in the block diagram in Figure 3.1.

RF

Filter

LNA

BPF

LO

IF Amp

BPF

AGC Amp

IQ-

demodulator

Rx

IQ

Figure 3.1. Superheterodyne receiver architecture

The first block after the antenna is an RF bandpass filter (BPF) which atten-uates the undesired out-of-band frequencies. The signal is then amplified in a lownoise amplifier (LNA) which amplifies the signal with relatively low noise contri-

bution. This device is the most crucial part of the receiver chain because of themany system requirements depending on it. After the amplification and bandpassfiltering the signal is down-converted by a mixer. This process is the principle of

11


32/103

12 Superheterodyne vs. SDR

heterodyning which is the generation of an intermediate frequency by mixing (mul-tiplying) the incoming high frequency signal with another high frequency signalgenerated by a local oscillator (LO). The mixer circuit has significant requirementson linearity and noise and can cause severe DC-offset problems in the receiver.

The generated IF-signal is amplified in the IF-amplifier before selection of thedesired channel in the last BPF. In the last stage the signal amplitude is adjustedby the automatic gain control (AGC) to fit the dynamic range of the analog-to-digital converter(s) (ADC).

3.2.1 Advantages

• A major advantage of the superheterodyne receiver is that by mixing downthe signal to lower frequencies the cost of the components reduces. Gener-ally for RF components, such as filters and mixers, cost is proportional tofrequency[4]. This is due to the fact that low frequency components are lesscomplex and easier to find/build.

• The down-conversion to IF gives the receiver high selectivity i.e. high abilityof sorting out the desired signal by supressing the undesired signals. This isbecause the requirements on the filters are relaxed when operating at lowerfrequencies (IF), which makes it easier to build more effective selective filterswith much narrower passband.

3.2.2 Disadvantages

• One of the biggest cons of the superheterodyne receiver is the amount of external components. The wider frequency spectrum the harder it is to findor build narrow-passband filters to a reasonable cost, if not impossible. Morecomponents means higher cost, higher power consumption, larger area andhigher architecture complexity.

• The complexity mentioned above leads to another problem which is the low

achievable level of integration. This also depends on the fact that the highperformance of discrete components is hard to achieve in an integrated so-lution.

• Another problem in this architecture is the mixer and local oscillator stages.One problem that is associated with mixer circuits, besides the cost, is theso called LO-leakage. This leakage can get mixed with the oscillator itself and/or get picked up by the antenna and get amplified in the LNA producinga spur.

• The wanted channel is predefined by hardware. Each channel require aseparate receiver which increases the need of hardware if multiple channelsare desired.


33/103

3.3 Software-Defined Radio Receiver 13

3.3 Software-Defined Radio Receiver

One of the newest and most interesting concepts in radio architecture developmentis software-defined radio (SDR). In this thesis project only the receiver part isdiscussed.

The basic idea of the SDR receiver is to digitalize the incoming analog RF signalas close to the antenna as possible and then do the signal processing digitally. In anideal SDR receiver the ADC(s) would be attached directly to the antenna sendingthe samples to some kind of processor (FPGA, DSP etc.) where the data would betransformed/shaped as desired by software. The sampling frequency (f s) wouldhave to be greater than twice the signal bandwidth to be able to reconstruct thesignal from the digital samples (Nyquist theorem)[11]. In practice this is hard toachieve due to the fact that todays ADC:s with the required resolution, are yettoo slow to receive radio signals at higher frequencies.

In current commercial software receivers the problem mentioned above is solvedby mixing down the radio signal to a lower frequency using local oscillators, asmentioned above in Section 3.2. This will not be the case here hence the main goalis to significantly reduce the use of analog hardware. Instead the problem is ap-proached by taking advantage of time-interleaving. As it was described in Chapter2, interleaving allows faster f s than the specified f s of the ADC. By interleaving N ADCs the f s could be N times the f s of a single ADC. Also described in Chapter2 was that SP Devices algorithm makes it possible to interleave high-speed ADC:swithout degrading the resolution. This technology allows high enough samplingfrequency for sampling the signal without requiring down-conversion, i.e. no mix-

ers or local oscillators are needed.The hardware architecture used in this project is further explained in Chapter6.

3.3.1 Advantages

• The SDR receiver has the ability to receive different modulation types whileusing the same hardware platform.

• Its funcionality can be changed by downloading and running new software

whenever desired, without any change of hardware.• Reduction/elimination of the use of analog hardware which means lower

cost, lower power consumption, smaller area needed and lower architecturecomplexity.

• The channel is not predefined by hardware which means that any channelwithin the bandwidth can be chosen by software. It is even possible to receiveseveral channels in parallel.

3.3.2 Disadvantages

• Finding the right components, such as amplifiers, for a flexible front-end canbe rather hard due to problems like linearity, dymanic range, noise figure.


34/103

14 Superheterodyne vs. SDR

• Filters are expensive and hard to design for such broadband applications.• Writing software for different applications can be quite complex.


35/103

Chapter 4

Basic RF Receiver Concepts

4.1 Signal-to-Noise Ratio

Signal-to-noise ratio (SNR) is the ratio between the power of the desired signal andthe average power of the noise in the system. In other words, the higher SNR theless noise in the system and the clearer signal. SNR is calculated using Equation4.1[11].

SNR = 10log

P signalP noise

(4.1)

In the process of choosing components for the receiver it must be consideredhow much a specific component affects the overall SNR, due to its noise contribu-tion. This means that in order to do an approximate calculation of the systemsSNR for a specific signal level the total receiver noise must be calculated. Thesection below shows the equations used for noise calculation. The SNR calulationsfor this system are done in Section 6.3.1.

4.2 Receiver Noise

In order to do a calculation of the receiver noise the thermal noise at the antennamust be calculated by using Equation 4.3[21] is Boltzmann’s constant, T is ab-solute temperature in kelvins and B is the Nyquist bandwidth, f s/2. Usually inreceiver noise calculations T is chosen to be 290K and gives 10log kT = -174 dBm.dBm is a representation of a power level in dB relative to 1 mW. This representa-tion gives a clue of how much stronger the measured signal is in comparison with1 mW.

N th = kTB (4.2)

N th(dBm) = 10 logkT + 10 logB =

= −174dBm + 10 log B (4.3)

15


36/103

16 Basic RF Receiver Concepts

After the calculation of the thermal noise the noise and gain contribution of allparts in the receiver are added, as shown in Equations 4.4 - 4.5. N in is the totalnoise power of the receiver before the A/D-conversion.

Fi = Ni−1 + NiNi−1

= 1 + NiNi−1

⇒

⇒ NiNi−1

= Fi − 1 (4.4)Nin = G1G2kTB + G1G2[F1 - 1]kTB + G2[F2 - 1]kTB =

= G1G2[F1 + F2 − 1

G1]kTB =

= GsysFsyskTB[W] (4.5)

Equation 4.5 represents the noise in a system containing two gain and/or noisecontributing devices. Fi is the noise factor of the i:th device after the antennaand Gi is the gain factor of ditto. As shown in Equation 4.5, the noise factor of a device is divided by the gain factor of all previous devices. This means thatdevices that are placed far from the antenna contributes less to the overall noisethan the ones closer to the antenna.

Notice that all noise and gain factors for the cascaded parts are linear valuesnot logarithmic. Usually in the devices’ data sheets the noise is represented asnoise figure (NF). NF is the common logarithm of the noise factor.

4.3 Intermodulation Distortion & Intercept Point

Intermodulation distortion (IMD) occurs when two or more different input fre-quencies exist in a device, resulting in production of undesired output signals(intermodulation products) at other frequencies. This is a problem in all ampli-fiers and mixers but also in passive components. In this project only amplifiersand passives are taken into account because of the absence of mixers. These in-termodulation products (IMD products) are produced at the sum and difference

of integer multiples of the existing frequencies. Equation 4.6 expresses the outputfrequency components when two different input frequencies exist in the device,which results in two-tone intermodulation distortion.

IMD = m · f 1 ± n · f 2 (4.6)The sum of the integers m and n in Equation 4.6 defines the order of the IMD

product. Most of these products are either too weak to be detected or too far awayto interfere with the desired frequencies. Generally in RF systems, and in the caseof this project, the third-order products (IMD3: 2f 1 + f 2, 2f 1 − f 2, 2f 2 − f 1,2f 2 + f 1) are of great concern, since the probability of them falling inband andinterfere with the desired frequency is high[21]. Intermodulation rejection raitois the ratio between the desired signal and the highest IMD3 product. It is an


37/103

4.3 Intermodulation Distortion & Intercept Point 17

imortant parameter which describes the receivers ability to handle strong IMDproducts.

Commonly IMD3 products are specified in terms of third-order intercept point(IP3). This is a measure of the devices tolerance against interfering signals outside

the desired passband. In Figure 4.1[7] the output power is plotted versus the inputpower, both in logarithmic scale. It is shown that both the output signal and theIMD3 product increase linearly with increased input signal. For every 1-dB of signal increase the IMD3 product amplitude increases 3 dB because of increaseddistortion in the device. At a certain level of input signal strength the wantedsignal and the IMD3 product will be equal. This point is called the IP3 whichusually is referenced to either the input or the output of the device. IIP3 is theinput power at the IP3 and OIP3 is the output power at the IP3. The relationshipbetween the two is OIP 3 = I IP 3 + system gain.

Figure 4.1. Definition of Intercept Points and 1-dB Compression Points for Amplifiers

Also seen in Figure 4.1 is the 1-dB compression point which shows the inputsignal level at which the receiver begins to get a non-linear amplitude response.This means that the device is linear up to a certain input signal level after whichthe output becomes saturerad and stop increasing with increased input signal.Both IP3 and 1-dB compression point are important parameters in the choice of amplifiers and most often one or both these values are given in the devices datasheet.

The power of an intermodulation product is calculated using Equation 4.7[5].PIM out is the power of the IMD product at the output of the device and Pout isthe signal power at the output.

PIM out = 3 · Pout − 2 · OIP3 (4.7)


38/103


This equation will be used in Section 6.3.2 to calculate a theoretical value of the total PIM generated in the chosen system configuration.

4.4 Dynamic Range

Dynamic Range (DR) is the ratio between the maximum and the minimum signalthat a receiver is designed to handle simultaneously. This measure is used fordescribing the limits of receivers. DR is of great concern in SDR solutions becauseof the wide frequency band of interest where signal levels can differ significantly.

4.5 Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) measures the ratio between the root-mean-

square (rms) level of the desired signal and the rms level of the highest spur in thespectrum. It is an important parameter in cases where harmonic distortion andspurious signals are undesirable. One example of these cases is analog-to-digitalconverters (ADCs) in which noise and harmonics limit the dynamic range.

4.6 Effective Number of Bits

The ADC resolution is defined as the number of bits at its output, i.e. the sizeof the binary word which represents the sampled analog signal. An alternative

definition is the size of the least significant bit (LSB), Equation 4.10. It should benoted that it is not a measure of the conversion quality. There are different errorsources in an ADC degrading its performance. When all sources are included, theresolution is usually lower than the specified number of bits of the converter[11].That is why the effective number of bits (ENOB) of an ADC is such an importantparameter and represents the noise-free bits. ENOB is a measure of the ADCsaccuracy at a specific input frequency. It is calculated using Equation 4.9[11]. Asseen in the equation the value of SNDR is needed for the calculation of ENOB.SNDR is signal-to-noise-and-distortion ratio and is defined similarly as SNR exceptit also includes distortion. See Equation 4.8[11]

SNDR = 10 log P signal

P noise + P distortion(4.8)

ENOB = SNDR − 1, 76

6.02 (4.9)

4.7 Oversampling in Analog-to-DigitalConverters

As mentioned earlier in Section 3.3, in order to reconstruct a signal from its digitalsamples it must be sampled at a frequency that is greater than twice the bandwidth


39/103

4.7 Oversampling in Analog-to-DigitalConverters 19

i.e. Nyquist’s criterion. If f s/2 is higher than the Nyquist frequency the ADC isconsidered to be oversampled. By oversampling the ADC(s) the overall SNR isincreased. The reason of this is explained below.

Quantization noise is introduced in the ADC when the continuous analog signal

is quantized to discrete values[11]. This quantization noise is a fixed power and isindependent of the input signal, as shown in eq 4.11[21] This noise is spread outover the Nyquist bandwidth, which is dc up to f s/2. If the ADC is oversampledthe noise is spread out over a wider range of frequencies. So the wider f s the lowernoise floor, i.e. higer SNR. This improvement of the SNR is called oversamplinggain or process gain, see Equation 4.12.

Vlsb = V p− p

2N (4.10)

Pqn = Vlsb

2

12R (4.11)

process gain = 10 log

f s/2

BW

(4.12)


40/103



41/103

Chapter 5

Requirements

Several requirements regarding the receiver’s performance are set up for thisproject. These requirements will be presented in this chapter. Also some ba-sic RF receiver concepts will be explained in order to make the understanding of the requirements easier.

5.1 Bandwidth

The bandwidth (BW) of the receiver in this project is desired to be between 112-174 MHz. This wide BW of 62 MHz sets major requirements on the analog filtersin the receiver. The filter requirements and problems caused by the wide BW areexplained in Section 6.2.3.

5.2 Sensitivity

Receiver sensitivity is the lowest signal level that is detectable by the receiver.The requirements regarding sensitivity in this project is that the receiver must beable to decode a modulated message at 162 MHz with a signal level of -107 dBm.A packet error rate (PER) of 20% is allowed. The modulation type of the signalis discussed in Chapter 7.

The highest detectable signal is required to be -7 dBm. The number of un-correctly received messages at this level should not differ by more than 10 fromthose received at -77 dBm. These boundary values of the signal level give a span

of 100 dB. It should be kept under consideration that all the components usedin the analog front-end must have proper performance at all levels of the 100 dBinterval.

21


42/103

22 Requirements

5.3 Intermodulation Response Rejection and

Blocking

Intermodulation response rejection is the receivers ability to supress IMD products

caused by two or more undesired signals. The frequencies of these signals have aspecific relationship to the desired signal frequency. A blocker on the other handis a strong out-of-band interferer that sets requirement on the receivers DR. Theblocker signal sets limitation on the maximum allowed receiver gain.

In this project the receiver must be able to decode messages with 20% PER ata level of -101 dBm in presence of two IMD products at -27 dBm and a blockersignal at -15 dBm. One of the IMD products is adjusted 500 kHz below or abovethe wanted frequency and the other is adjusted 1000 kHz below or above it. Theblocker signal is adjusted 5MHz below the wanted frequency. The input desiredsignal is adjusted to the same frequency as the previous test. This test is considered

to simulate the worst case scenario.

5.4 Adjacent Channel Selectivity

The adjacent channel selectivity is the receivers ability to receive desired signals inpresence of an undesired interfering signal at the frequency of the channel directlyabove that of the desired signal. The requirment on the adjacent channel selectivityof the receiver is that it shall not be less than 70 dB.

5.5 Signal-to-Noise Ratio

As mentioned in Section 5.3 the receiver must be able to operate despite theexistence of a blocker signal and two IMD products. In this worst case scenarioit is possible that the mentioned signals interfere with each other, hence theiramplitudes will be added together, creating an amplitude even higher than theamplitude of the blocker signal alone. This amplitude is calculated by using theequations below.

A =

50 · 10−3 · 10P dBm/10, conversion of dBm to V (5.1)P =

A2

R (5.2)

Atot = Asig + Ablocker + AIMD1 + AIMD2 (5.3)

Ptot,dBm = 10 log

A2tot

R · 10−3

(5.4)

DR = Ptot,dBm − Psignal (5.5)

The resistor value R in Equation 5.2 is 50 Ω and is the antennas load resistance.In this case the signal caused by the mentioned interference is at a level of -11.5dBm. The difference between this level and the desired signal level at -101 dB


43/103

5.5 Signal-to-Noise Ratio 23

gives a DR of 89.5 dB. The decoder that is used for decoding the received messagesrequires an SNR of 12 dB. This means that the receiver need an overall SNR of atleast 89.5 + 12 = 101.5 dBFS to be able to decode a received message. dBFS is arepresentaion of the ratio between a signal and the full-scale signal of a system.

For the sensitivity test the required SNR is different from above due to thereceiver gain which is decided by the gain in the amplifiers and possibly the filters.Thus the SNR of this test will be presented after the components has been chosen,see Chapter 6.


44/103

24 Requirements


45/103

Chapter 6

Analog Front-End

This chapter covers the chosen architecture of the analog front-end and motivatesthe choice of components for both PCB versions. Also both PCB designs arepresented together with the measures taken to prevent EMC problems.

6.1 Front-End Architecture

As mentioned earlier the main goal of this project is to build an RF receiver for therequired frequency band containing as few analog parts as possible. This achieve-

ment is possible due to the concept of SDR together with SP Devices technology.As was mentioned in Section 3.3 this technology makes it possible to build a socalled direct sampling receiver witout using mixer circuits and local oscillators forfrequency down-conversion. Despite this fact the ADCs can not be directly at-tached to the antenna due to a couple of reasons. One reason is that without someattenuating bandpass filters strong undesired signals could saturate the ADCs.Another reason is that without amplification the weakest signals would never getstrong enough to get sampled properly by the ADC. The closer a signal is to theADC’s input voltage range the more bits of the ADC are used. Figure 6.1 showsthe chosen architecture for the analog front-end.

BPF1 BPF2LNA AGC

ADC1

ADC2

DAC FPGA

Figure 6.1. The architecture of the analog front-end.

The first bandpass filter (BPF1) is intended to attenuate undesired out-of-bandfrequencies. The signal is then differentiated passing through a 1:1 transformer.

25


46/103

26 Analog Front-End

The reason for differentiating the signal path is to reduce the sensitivity of distur-bance in the transmission lines. This is further explained in Section 6.4.

After the first filter the signal is amplified in a low noise amplifier (LNA), whichis the most crucial part of this design due to the noise and IMD requirements

depending on it, see Section 6.2.2. The second bandpass filter (BPF2) is meantto filter out the wanted signal further before its amplitude is adjusted by thevariable gain amplifier (VGA). The VGA is controlled to either amplify the signalor attenuate it, depending on the signal level. This is called automatic gain control(AGC) and is intended to push the signal amplitude as close as possible to theADC:s input voltage range.

The last stage of the front-end is the A/D-conversion. Here the two interleavedADCs digitalize the received signal and feeds it through to a field-programmablegate array (FPGA) where the data is processed. The data processing in the FPGAis explained in Chapter 8.

This front-end architecture is used on both PCB:s. The only difference is thatin the first case the FPGA is off-board and is placed on a development board. Onthe second PCB the FPGA is placed on-board.

6.2 Choise of Components

In this section the chosen components are presented together with the motivationof why they were chosen. Choosing and finding the right components for the analogfront-end is very challenging. The choice of the different parts of the receiver must

be done in parallel, because the properties of all parts depend on each other. Inthis project the ADC is chosen to be the starting point.The components used in the front-end alone do not differ between the two

boards. The major difference is that the FPGA is mounted on-board in the secondattempt while in the first case an external development board handled the signalprocessing.

6.2.1 ADC

The analog-to-digital conversion is usually the part that limits the performance

of the receiver. The most important parameters in choosing this component areresolution, sampling frequency, SNR and SFDR.

SNR and f s

Some calculations were done on the some of the ADC parameters, mentioned inChapter 4, at different sampling frequencies, see Equations 6.1 - 6.3. As it isshown, the channel bandwidth is chosen to be 25 kHz which is usually the case inthe VHF band[14]. The results of the calculations can be seen in table 6.1.

The ADC resolution is defined as the number of bits at its output, i.e. the size

of the binary word which represents the sampled analog signal. An alternativedefinition is the size of the least significant bit (LSB), Equation 4.10. It should benoted that it is not a measure of the conversion quality. There are different error


47/103

6.2 Choise of Components 27

sources in an ADC degrading its performance. When all sources are included, theresolution is usually lower than the specified number of bits of the converter[11].That is why the effective number of bits (ENOB) of an ADC is such an importantparameter and represents the noise-free bits.

Some calculations were done on the mentioned ADC parameters at differentsampling frequencies, see Equations 6.1 - 6.3. As it is shown, the channel band-width is chosen to be 25 kHz which is usually the case in the VHF band[14]. Theresults of the calculations can be seen in table 6.1.

SNRreq = 101.5dB (6.1)

BWch = 25kHz (6.2)

SNRideal = SNRreq − 10log f s/2

BWch

(6.3)

f s SNR

340 63.2105380 62.7274420 62.2928460 61.8977500 61.5356

Table 6.1. SNR requirement at different sampling frequencies.

The table above shows that the required values of SNR lessens with increasingf s, which is a good reason to choose a high f s. Besides, considering the advantagesof oversampling that were mentioned in Section 4.7, choosing f s high would helprelaxing the requirements on the analog filters and improve the overall SNR.

The chosen architecture includes two interleaved ADC:s, as mentioned earlier.After spending relatively short time searching among the leading manufaturers,it was noted that the 14-bit ADC called ADS5546 from Texas Instruments was

best suited for this applicaion. The maximum f s is 190 MHz which means a totalf s of 380 MHz after interleaving. The ideal SNR of this converter is 72.2 dBwhich is almost 10 dB higher than the required SNR for this f s, also shown inthe same table. Some calculations are done in Section 6.3 to show that this ADC,theoretically, fulfills the system requirements mentioned in the previous chapter.

6.2.2 LNA and VGA

When choosing amplifiers for this project the most important parameters are theNF and the OIP3. Due to the inefficient analog filtering in this project it is prefer-

able to have as linear components as possible to avoid intermodulation productsin the system. Because of this the OIP3 and the 1-dB compression point of theamplifiers must be as high as possible.


48/103

28 Analog Front-End

As mentioned in Section 4.2 it is extra important that the components nearestto the antenna have low NF because the noise contribution affects the overall noisemore in the early stages of the receiver chain. So it is of great importance thatthe LNA has low NF. As it was shown in Equation 4.5, it is also preferable to

have high gain in the LNA or the other parts in the begining of the receiver chain.This makes the noise contribution of the following parts less important due tothe division with the gain factor of the previous parts. Because of the differentialsignaling used in the design, the LNA should have differential input and output.

Finding an LNA with the mentioned characteristics is hard. After evaluatingthe data sheet of many LNA:s it was decided to use the ADL5330 from AnalogDevices. This amplifier is a VGA which gain can be fixed by attaching the controlpin to a fix voltage. The level of the fixed gain depends on the voltage level onthe control pin. The amplifier has an acceptable NF and a high OIP3. Someproperties of the circuit are presented in Table 6.2.

The same amplifier circuit is used for the AGC in this project. As it is presentedin Table 6.2 the gain can be adjusted between -34-22 dB. The control signal rangeis between 0-1.4V which means that if the control signal is 0V the gain of the VGAis -34 dB, and if the control signal is 1.4 V the gain is 22 dB.

Calculations in Section 6.3 shows that this amplifier fulfills the requirementstheoretically.

Gain -34 - 22 dBNF 7.8 dB

OIP3 38 dBm

1dB Compression point 22 dBm

Table 6.2. Properties for the VGA.

6.2.3 Analog Filters

BPF1 and BPF2 in Figure 6.1 are two analog BP-filters that are intended toselect out the desired band and attenuate the neighbouring undesired bands. The

frequency range of interest in this project is required to be 112-174 MHz, whichbelongs to the VHF-band. This means that the filters should have a passband of 62 MHz with a center frequency of 143 MHz. This passband should not attenuatethe test signal at 162 MHz mentined in the test sections. The absence of mixercircuits, i.e. frequency down-conversion, in the receiver makes it very hard to findhighly selective filters with such wide passband at such high frequencies with lowinsertion loss. Insertion loss in a filter is the ratio between the input power andthe output power. It is a measure of the power loss in the device. In other wordsthe passband attenuation in the filter.

However, a filter type commonly used in RF applications is surface acoustic

wave filter (SAW). Their main properties are that they can be designed physicallysmall providing good out-of-band rejection, broad pass-band and steep transitionedges. With these filter characteristics the SAW filter appears to be the right


49/103


choice for this application. But after spending hours and hours searching amongmanufacturers’ standard products, it was noted that finding a suitable SAW fil-ter is an impossible task due to their extremely high insertion loss. The chosenarchitecture can not afford this high level of insertion loss, hence with even zero

insertion loss in the filters it still is a challenge achieving the required sensitivity of -107 dBm. Some manufaturers have the possibility of building customized filtersbut for a cost that is over budget in this thesis project.

After considering the facts and the given options it was decided to build thefilters as passive bandpass filters with discrete components. A filter with thementioned characteristics require high filter order. The higher the filter orderthe more discrete components are required. So a decision was made to loosen therequirements to be able to build low-order filters with a few components. It shouldbe noted that with more time and higher budget the filters could be built muchbetter, but for now passive low-order filters will do.

The first bandpass filter is a second order LC-filter with only one inductorand one capacitor, see Figure 6.2. The second filter is a fourth order LC-filter, asshown in Figure 6.3. An advantage of the implemented filters are that they haveno insertion loss.

Zi=50 Ohm Ro=50 OhmC L

Figure 6.2. BPF1 - 1st order bandpass filter.

Zi=50 Ohm Ro=50 Ohm

C2L2

C1L1

Figure 6.3. BPF2 - 2nd order bandpass filter.

As it is shown in the figures above both analog filters have 50 Ω impedance onboth input and output. This depends on the output and input impedances of thecomponents attached before and after the filters. In order to get the impedances

matched it is necessary to choose the component values so that the resonancefrequency of the filter circuits is equal to the desired signal frequency. Impedancematching between components is very important in order to avoid reflections in


50/103

30 Analog Front-End

the signal path. The resonance frequncy is easily calculated in both these cases,see equations 6.4[16].

Zi = Ro + 1

jωC + jωL (6.4)

The impedance is matched if Zi = Ro. In order to make this happen thecomponent values must be chosen so that 1jωC + jωL = 0. This leads to equation6.6 which is used for calculating the resonance frequency of the filter, which in thiscase means the least filtered frequency.

The chosen component values, see table 6.3 give an overall bandwidth of about60 MHz with a center frequency around 160 MHz, which suits this project hencethe required test signal is situated at 162 MHz. A frequency analysis was done inProtel on the two filters, which frequency responce can be seen in Figure 6.4.

75.00MHz 100.0MHz 125.0MHz 150.0MHz 175.0MHz 200.0MHz 225.0MHz 250.0MHz 275.0MHz 300.0MHz

0.000 dB

-2.500 dB

-5.00 dB

-7.50 dB

-10.00 dB

-12.50 dB

-15.00 dB

A m p l i t u d e [ d B ]

Frequency [MHz]

Figure 6.4. BPF1 - 1st order bandpass filter.

ω = 1√ LC

(6.5)

f = 1

2π√ LC (6.6)


51/103


Filter Component Value

BPF1 C 100pFL 10nH

BPF2 C1 100pF

L1 10nHC2 100pFL2 10nH

Table 6.3. Component values for the analog bandpass filters.

6.2.4 FPGA

As shown in Figure 6.1 the digitalized signal from the ADC:s is fed through to an

FPGA where the data is processed. The first PCB does not include the FPGA.Instead the front-end PCB is attached to a development board which includes aVirtex 4 FPGA from Xilinx. On the second board the front-end and the FPGAare placed on the same PCB. This time the Virtex 5 from Xilinx was used. TheseFPGAs can be programmed in two ways. One way is to directly program it via aJTAG-connection from the PC. This way the program is erased when the poweris switched off and the FPGA must be reprogrammed at power on. The secondway is to use the flash memory placed on-board. By programming the flash theFPGA can reprogram itself everytime the power is switched on.

After the FPGA the processed data is sent to a PC where the data is de-

coded. For transmitting and receiving data to and from the PC a UART-interfacewas implemented in the FPGA. In the PC however the USB port was chosen ascommunication link. This means that a USB-to-UART converter is needed. Theconverter used is presented in the next section.

6.2.5 USB-to-UART Interface

For converting the FPGA:s UART-signals to the PC:s USB-signals and vice versaa converter from FTDI called FT232R was used. In the case of the first PCB this

converter is built-in in a cable that is used for the communication between thedevelopment board and a PC. In the second case the converter is built-in in a chipwhich is placed directly on the PCB between the FPGA and a type B USB-port.According to the data sheet of FT232R it can handle up to 3 Mbits/s.

6.2.6 DAC

As mentioned above the chosen VGA has an analog control signal input. So thedigital control signals from the FPGA must be converted to an analog signal witha digital-to-analog converter (DAC), as shown in figure 6.1. For this task a DAC

called AD7302 from Analog Devices was chosen. It has a parallel 8-bit input andan output voltage range of 5V, which means that the output changes by steps of 5/28 ≈ 0.0195 V. This step size gives the VGA 1.4/0.0195 ≈ 72 different gain


52/103

32 Analog Front-End

settings. So only 7 bits of the DAC are needed, thus 26 = 64 is too few and28 = 256 is too much.

6.2.7 Crystal Oscillator and Clock Buffer

The ADCs need to have a clock signal that determines the sampling frequency.As mentioned in the ADC section the decided sampling frequency in this projectis 380 MHz. This means that the interleaved ADCs have an f s of 190 MHz each.

On the first board the clock signal is provided from an external signal generator.The generator provides a 380 MHz signal which gets divided into two 190 MHzclock signals by a clock buffer called CDCP1803 from Texas Instruments. Thedivided clock signal is then distributed to the ADC:s.

On the second board the signal is generated from a crystal oscillator whichprovides a 380 MHz signal. The oscillator is a Si530 from SiLab. In the same way

as the first board the signal from the oscillator is divided into two 190 MHz signalsin a clock buffer.

6.2.8 Linear Voltage Regulators

There are two different supply levels used on the first board and four differentlevels on the second. The first board contains 3.3V digital, 3.3V analog and 5Vanalog supply. The second board contains 1V digital, 2.5V digital, 3.3V digital,3.3V analog and 5V analog supply.

The reason of why the digital and the analog supplys are split up will beexplaind in Section 6.4. For the supply management some linear voltage regulatorsfrom Texas Instruments and Maxim are used. See Table 6.4 for the first boardand Table 6.5 for the second. The TPS786xx is from Texas Instruments and hasa maximum output current of 1.5A and the MAX8869 has a maximum outputcurrent of 1A. As it can be seen in the Tables 6.4 and 6.5 the amount of currentthat needs to be supplied is kept under the maximum limit on all regulators.

Regulator Component Quantity Supply Current(mA)

TPS78601 DAC 1 5

(Analog, 5V) VGA 2 215Sum 435

TPS78633 ADC 2 300(Analog, 3.3V) Sum 600

TPS78633 ADC 2 51(Digital, 3.3V) Clk buffer 1 140

Sum 242

Sum(tot.) 1277

Table 6.4. Current consumption of the first PCB


53/103


Regulator Component Quantity Supply Current(mA)

TPS78601 DAC 1 5(Analog, 5V) VGA 2 215

Sum 435TPS78633 ADC 2 300(Analog, 3.3V) Sum 600

TPS78633 ADC 2 51(Digital, 3.3V) FPGA(I/O) 1 10

Crystal Osc. 1 100Clk buffer 1 140Flash 1 20FTDI 1 100

Linear reg.(1A) 1 0.5Sum 473

TPS78625 AFPGA(Aux) 1 73(Digital, 2.5V) FPGA(I/O) 1 325

Sum 398

MAX8869 FPGA(Core) 1 500(Digital, 1V) Sum 500

Sum(tot.) 2406

Table 6.5. Current consumption of the second PCB


54/103

34 Analog Front-End

6.3 Theoretical Calculations

In this section some theoretical calculations are done to show that the chosen com-ponents fulfill the SNR and the third-order intermodulation requirements, hencethese are the main requirements in this project.

6.3.1 SNR

In this section the two most crucial cases are studied, i.e. the sensitivity test andthe intermodulation/blocking test.

Calculating the overall SNR of the receiver in dBFS can be done as follows:

Vnoisetotal =

VnoiseADC2 + Vnoisein

2 (6.7)

SNRtot = 20 log

VFS ADCVnoisetotal

+ Process Gain (6.8)

Vnoisetotal [21]is the total noise voltage of the system including the noise voltageat the ADC input and the noise voltage contributed by the ADC itself. the noiseVFS ADC in the equation above is the rms value of the full-scale (FS) signal of theADC, which is derived by using Equation 6.9. The noise in the ADC is independentof the input signal and will be the same value in both tests. The rms value of theADC’s noise voltage is calculated as shown below[6]:

VFS ADC = V p− pADC

2√

2=

2

2√

2=

1√ 2

V (6.9)

VnoiseADC2 =

VFS ADC · 10

−SNRADC20

2

=

2

2√

2· 10−72.220

2≈ 3.013 · 10−8V2

This value is used in the secitons below for calculating the overall noise in thereceiver in both test environments.

Intermodulation and Blocking

As mentioned in the requirements, the receiver must be able to operate despiteinterference with unwanted signals. In section 5.5 it was explained that the levelcaused by the interference can get as high as -11.5 dBm. This level limits themaximum allowed amplification in the receiver. The ADCs have a specified inputvoltage range which sets the limit of the maximum allowed signal level. If theamplified signal passes this limit the ADC will be saturated. The chosen ADC hasan input voltage range of 2V which gives a full-scale signal at 10 dBm. This gives a

maximum allowed gain of 10 − (−11.5) = 21.5 dB for this test. By using equation4.5 together with the given maximum gain and the given amplifier NFs, the rmsvalue of the total noise voltage at the ADCs input can be calculated. The total


55/103

6.3 Theoretical Calculations 35

NF of the system includes only the specified noise contribution of the amplifiers.Other, unspecified, noise sources are hard to estimate. The SNR calculations aredone as follows:

Nin,dBm = 10 log Nin =

= −174 + 10 log(190MHz) + 20 log(107.820 + 107.820 − 1

1021.520

) + 21.5 =

= −61.4898dBmVnoisein

2 = 10−61.4898/10 · 10-3 · 50 = 3.548 · 10−8V2(6.10)

The calculations above give the total noise voltage for the system.

Vnoisetotal =

3.013 · 10−8 + 3.548 · 10−8 ≈ 2.5614 · 10−4V

Now the overall full-scale SNR of the system can be calculated using Equation6.8:

SNRtot = 20 log

0.70712.5614 · 10−4

+ 10 log

190MHz

25kHz

= 107.6282dBFS

This means that with the chosen components an SNR of 107.6 dBFS can beachieved theoretically, which is more than 6 dB greater than the required SNRof 101.5 dBFS in this test. Theoretically it would be possible to also fulfill thesensitivity requirement with the same amplification thus the required SNR wouldbe 107.5 dBFS. This would mean that the VGA is not needed. But in reality thiswill not be the case thus the noise contribution of the analog filters and other noise

sources are not included in this calculation. The 0.1dB margin is not enough tofulfill the requirement when all noise sources are included.

Sensitivity

In this test there are no other signals present but a weak signal of -107 dBm, thusmaximum possible gain can be used. Theoretically, the full-scale SNR needs tobe 10dBm - (-107dBm + 44dB) + 12dB = 85dBFS. This is the ratio between the

ADC’s full-scale signal and the amplified test signal plus the 12dB required bythe decoder. Here follows the SNR calculations that are done similairly as thecalculations above:


56/103

36 Analog Front-End

Nin,dBm = −174 + 10 log(190MHz) + 20 log(107.820 + 107.820 − 1

102220

) + 44 =

= −39.0129dBmVnoisein2 = 10−39.0129/10 · 10-3 · 50 = 6.2759 · 10−6V2Vnoisetotal =

3.013 · 10−8 + 6.2759 · 10−7 ≈ 0.0025V

SNRtot = 20 log

0.7071

0.0025

+ 10 log

190MHz

25kHz

= 87.8003dBFS

Also in this test the SNR requirement is fulfilled. The achieved SNR of 87.8dBFS is more than 2dB higher than the required 85 dBFS. Theoretically thismargin is more than enough, but in reality the actual SNR could differ from the

calculated SNR due to non-included noise sources. SNR measurements are doneon both PCBs in Chapter 10.

6.3.2 IMD3

As mentioned in Section 4.3, third-order intermodulation distortion can causemajor problems in the receiver if they fall inband in the desired signal bandwidth.In this section som theoretical calculations are done to confirm that the chosencomponents, in the chosen configuration, fulfill the requirements that are set up to

avoid this kind of problem. This is a theoretical measure of the so called two-tonetest that is commonly used for estimating the non-linearity of systems. The valueof parameters that are needed for this calculation are presented in Figure 6.5. Asit is shown, the first amplifier must be adjusted to 21.5 dB and the second to 0dB hence the maximum allowed gain in the IMD/blocking test is 21.5 dB, as wasmentioned earlier.

BPF2LNA AGC

Glna: 21.5 dBOIP3lna: 38 dBm

Gfilt: 0 dB Gagc: 0 dBOIP3agc: 38 dBm

Pin: -24 dBm Plna: -2.5 dBm Pagc: -2.5 dBm

Figure 6.5. The configuration for IMD measurements.

As it is shown in the figure, the test signal has a level of -24 dBm which is theaverage power of the two IMD tones of -27 dBm each. Together with the givenvalues, the calculations are done by using Equation 4.7:


57/103

6.4 PCB and EMC[13] 37

PIM LNA = 3 · Plna − 2 · OIP3LNA = 3 · (−2.5) − 2 · 38 = −83.5dBmPIM AGC = 3 · Plna − 2 · OIP3AGC = 3 · (−2.5) − 2 · 38 = −83.5dBm

Since the VGA is adjusted to 0 dB gain, the calculated IMD3 powers willremain the same at the input of the ADC. By using these results, a total IMD3power can be calculated:

PIM tot = 10 log(10−8.35 + 10−8.35) = −80.5dBm

The calculations result in a total IMD3 power of -80.5 dBm at the ADC input.In the mentioned IMD/blocker test, the desired signal has a level of -101dBm,which after amplification of 21.5 dB is brought up to -79.5 dBm. This value isonly 1 dB higher than the level of the IMD3. This could cause problems if the

IMD product falls inband. The decoding of the signal could be prevented hencethe decoder requires a 12 dB SNR/SFDR.Despite the result of the calculations above, it is decided to use the chosen

components anyway, hence finding amplifiers with higher OIP3 than 38 dBm withhigh gain is time consuming. With the tight time schedule of this work this couldnot be done.

6.4 PCB and EMC[13]

In order to design a PCB there are many factors to keep in mind. In this worksome actions were taken to avoid performance degradation due to, for example,EMC problems. A short list covers some of these actions:

• The analog and the digital supplies are split up to avoid transfering the noisydigital supply into the analog region.

• The clock signal paths to the ADCs have the same length to minimize clockskew.

• The impedance in components are matched to avoid reflections in the signalpath.

• Many decoupling capacitors were used in order to prevent unwanted energytransfer between high frequency devices and the power distribution network.

The first PCB has four layers including two interconnected ground layers. Thesecond PCB has six layers to make it easier to route the FPGAs BGA-package(Ball Grid Array). Also this board has two interconnected ground layers.

Ground layers are important in order to keep the noise generated from groundat a minimum. They create a good path for returning currents and make itconvinient to route ground pins of devices anywhere on the board, using vias.

It would have been preferable to have two separate ground layers, using onefor the digital parts and the other for the analog parts. This is hard to achieve inreality hence this was not at

Design and Implementation of an SDR receiver for the VHF band

Documents

Transcript of Design and Implementation of an SDR receiver for the VHF band