Design and Implementation of an SDR Receiver for the VHF Band Thesis

Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

Design and Implementation of an SDR receiver forthe VHF band

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan i Linköping

av

Emad Athari & Petter Lerenius

LITH-ISY-EX--07/3946--SE

Linköping 2007

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping

Design and Implementation of an SDR receiver forthe VHF band

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan i Linköping

av


LITH-ISY-EX--07/3946--SE

Handledare: Per LöwenborgISY, Linköpings universitet

Jonas NilssonSignal Processing Devices Sweden AB

Examinator: Per LöwenborgISY, Linköpings universitet

Linköping, 31 January, 2007

Avdelning, InstitutionDivision, Department

ElektroniksystemDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

DatumDate

2007-01-31

SpråkLanguage

Svenska/Swedish Engelska/English

RapporttypReport category

Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk versionhttp://www.es.isy.liu.sehttp://www.ep.liu.se/2007/3946

ISBN—

ISRNLITH-ISY-EX--07/3946--SE

Serietitel och serienummerTitle of series, numbering

ISSN—

TitelTitle

Design och implementation av en SDR-mottagare för VHF-bandetDesign and Implementation of an SDR receiver for the VHF band

FörfattareAuthor


SammanfattningAbstract

The purpose of this thesis work is to examine the possibility of building a software-defined radio (SDR) for the VHF-band. The goal is to accomplish this with as fewcomponents as possible, thus cutting down the size and the production cost.

An SDR solution means that the sampling of the signal is done as close to theantenna as possible. The wide bandwidth needed in such a product is achievedby using SP Devices algorithm for time-interleaved ADCs. Two hardware proto-types and two versions of the software were designed and implemented using thistechnology.

They were also analyzed within this thesis work. The results proved to be good,and the possibilities to produce a commercial software-defined radio receiver forthe VHF-band are good.

NyckelordKeywords SDR, software-defined radio, radio, GMSK, receiver, FPGA

AbstractThe purpose of this thesis work is to examine the possibility of building a software-defined radio (SDR) for the VHF-band. The goal is to accomplish this with as fewcomponents as possible, thus cutting down the size and the production cost.

An SDR solution means that the sampling of the signal is done as close to theantenna as possible. The wide bandwidth needed in such a product is achievedby using SP Devices algorithm for time-interleaved ADCs. Two hardware proto-types and two versions of the software were designed and implemented using thistechnology.

They were also analyzed within this thesis work. The results proved to be good,and the possibilities to produce a commercial software-defined radio receiver forthe VHF-band are good.

SammanfattningSyftet med det här examensarbetet är att utreda möjligheten att bygga en mjuk-varudefinierad radiomottagare (SDR) för VHF-bandet. Målet är att göra dettagenom att använda så få komponenter som möjligt, och därigenom minska stor-leken och produktionskostnaden.

En SDR lösning ger att samplingen kommer att ske så nära antennen sommöjligt. Den stora bandbredd som behövs för en sådan produkt uppnås genomatt använda SP Devices algoritm för att ”tidsinterleava” höghastighets ADC:er.Två hårdvaruprototyper och två versioner av mjukvaran har designats och imple-menterats.

Analyserna har visat bra resultat, och möjligheterna att bygga en komersiellmjukvarudefinierade radiomottagare för VHF-bandet ses som goda.

v

Acknowledgments

The completion of this thesis had not been possible without the help and supportthat we have received throughout this work. Therefore we would like to thank thepeople the persons that has made this possible.

Firstly we would like to thank our supervisors Per Löwenborg, at the Divisionof Electronics Systems at Linköping University, and Jonas Nilsson, at SP Devices,for their enormous support and for believing in us.

We would also like to thank all of the personnel at SP Devices and Peter,Christian, Marcus and Anders for great help and support.

Last but not least we would like to thank our families and friends for theirendless love and support.

vii

Abbreviations

ACK AcknowledgementAD Analog-to-DigitalADC Analog-to-Digital ConverterAGC Automatic Gain ControlBB BasebandBER Bit Error RateBPF Bandpass FilterBW BandwidthBWch Channel BandwidthDAC Digital-to-Analog ConverterdB DecibeldBc Decibel relative to the carrierdBFS Decibel relative to Full Scale RangedBm Decibel relative to 1 mWDC Direct CurrentDDS Direct Digital SythesisDSP Digital Signal ProcessingDR Dynamic RangeEMC Electromagnetic CompatibilityENOB Effective Number of BitsFFT Fast Fourier TransformFIR Finite length Impulse ResponseFPGA Field-Programmable Gate ArrayFSR Full Scale RangeGMSK Gaussian Minimum Shift KeyingHDLC High Level Data Link ControlIF Intermediate FrequencyIP3 Third-Order Intercept PointIIP3 Third-Order Input Intercept PointIMD Intermodulation DistortionIMD3 Third-Order Intermodulation DistortionIQ In phase and QuadratureIR Image RejectionLNA Low Noise AmplifierLO Local Oscillator

ix

x

LPF Lowpass FilterLSB Least Significant BitMAC Multiply and AccumulateNF Noise FigureNRZ Non Return to ZeroNRZI Non Return to Zero InvertedOIP3 Third-Order Output Intercept PointPER Packet Error RatePG Process GainRF Radio FrequencySAW Surface Acustic WaveSDR Software Defined RadioSFDR Spurious-Free Dynamic RangeSNDR Signal-to-Noise and Distortion RatioSNR Signal-to-Noise RationSNRreq SNR requiredv4 Xilinx virtex 4v5 Xilinx virtex 5VGA Variable Gain AmplifierVHF Very High Frequency

Contents

1 Introduction 11.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Purpose and Method . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.4.1 Protel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.2 Matlab and Simulink . . . . . . . . . . . . . . . . . . . . . . 21.4.3 Xilinx ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.4 Microsoft Visual Studio . . . . . . . . . . . . . . . . . . . . 2

1.5 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.6 Report Disposition . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.7 Reading Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Linearizer 52.1 Problems with Interleaved ADCs . . . . . . . . . . . . . . . . . . . 5

2.1.1 Gain Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . 62.1.2 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.3 Time-Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 The Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Superheterodyne vs. SDR 113.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2 Traditional Superheterodyne RF Receiver . . . . . . . . . . . . . . 11

3.2.1 Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2.2 Disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 Software-Defined Radio Receiver . . . . . . . . . . . . . . . . . . . 133.3.1 Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3.2 Disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Basic RF Receiver Concepts 154.1 Signal-to-Noise Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . 154.2 Receiver Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.3 Intermodulation Distortion & Intercept Point . . . . . . . . . . . . 164.4 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.5 Spurious-Free Dynamic Range . . . . . . . . . . . . . . . . . . . . . 18

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4.6 Effective Number of Bits . . . . . . . . . . . . . . . . . . . . . . . . 184.7 Oversampling in Analog-to-Digital

Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Requirements 215.1 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.2 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.3 Intermodulation Response Rejection and

Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.4 Adjacent Channel Selectivity . . . . . . . . . . . . . . . . . . . . . 225.5 Signal-to-Noise Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6 Analog Front-End 256.1 Front-End Architecture . . . . . . . . . . . . . . . . . . . . . . . . 256.2 Choise of Components . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.2.1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.2.2 LNA and VGA . . . . . . . . . . . . . . . . . . . . . . . . . 276.2.3 Analog Filters . . . . . . . . . . . . . . . . . . . . . . . . . 286.2.4 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.2.5 USB-to-UART Interface . . . . . . . . . . . . . . . . . . . . 316.2.6 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.2.7 Crystal Oscillator and Clock Buffer . . . . . . . . . . . . . . 326.2.8 Linear Voltage Regulators . . . . . . . . . . . . . . . . . . . 32

6.3 Theoretical Calculations . . . . . . . . . . . . . . . . . . . . . . . . 346.3.1 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.3.2 IMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.4 PCB and EMC[13] . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7 Data Packets 397.1 The Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1.1 Training Sequence . . . . . . . . . . . . . . . . . . . . . . . 407.1.2 Start Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.1.3 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.1.4 Frame Check Sequence . . . . . . . . . . . . . . . . . . . . . 41

7.2 Bit Stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417.3 NRZI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417.4 GMSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.4.1 Gaussian filter . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 FPGA 438.1 Hardware Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.1.1 DSP-slices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448.2 First Attempt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.2.1 Linearizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448.2.2 First Decimation . . . . . . . . . . . . . . . . . . . . . . . . 468.2.3 I - Q Modulation . . . . . . . . . . . . . . . . . . . . . . . . 468.2.4 Second Decimation . . . . . . . . . . . . . . . . . . . . . . . 47

Contents xiii

8.2.5 Third Decimation . . . . . . . . . . . . . . . . . . . . . . . 478.2.6 Phase Differentiator . . . . . . . . . . . . . . . . . . . . . . 488.2.7 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488.2.8 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 498.2.9 DAC Controller . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.3 Second attempt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498.3.1 Linearizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498.3.2 IQ-modulation . . . . . . . . . . . . . . . . . . . . . . . . . 498.3.3 Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . 518.3.4 Phase Differentiator . . . . . . . . . . . . . . . . . . . . . . 578.3.5 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.3.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 578.3.7 DAC Controller . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.4 Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.4.1 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.4.2 Word Length . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9 PC 619.1 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619.2 Matlab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.2.1 Symbol Syncronization . . . . . . . . . . . . . . . . . . . . . 619.2.2 Decode NRZI . . . . . . . . . . . . . . . . . . . . . . . . . . 639.2.3 Extraction of the Data . . . . . . . . . . . . . . . . . . . . . 63

10 Tests and Results 6510.1 Filter Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.1 Board 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6510.1.2 Board 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.2 External LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6610.3 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.3.1 Variable Gain - Fixed Signal Level . . . . . . . . . . . . . . 6710.3.2 Fixed Gain - Variable Signal Level . . . . . . . . . . . . . . 68

10.4 Sensitivity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910.4.1 Board 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7010.4.2 Board 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.5 Blocking Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7210.6 Intermodulation Test . . . . . . . . . . . . . . . . . . . . . . . . . . 7410.7 Adjacent Channel Selectivity . . . . . . . . . . . . . . . . . . . . . 7510.8 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11 Conclusions and Future Work 7711.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.1.1 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 7711.1.2 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7811.1.3 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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References 81

Contents xv

List of Figures2.1 Effect of problems that occur when interleaving ADCs. . . . . . . . 52.2 Result of a gain error in an ADC. . . . . . . . . . . . . . . . . . . . 72.3 Result of an offset error in an ADC. . . . . . . . . . . . . . . . . . 72.4 Result of time-skew in an ADC. . . . . . . . . . . . . . . . . . . . . 82.5 The block diagram of the linearizer . . . . . . . . . . . . . . . . . . 82.6 Interleaved sequencies with missmatch, before and after linearization. 9

3.1 Superheterodyne receiver architecture . . . . . . . . . . . . . . . . 11

4.1 Intercept Points/1-dB Compression Points . . . . . . . . . . . . . . 17

6.1 The architecture of the analog front-end. . . . . . . . . . . . . . . . 256.2 BPF1 - 1st order bandpass filter. . . . . . . . . . . . . . . . . . . . 296.3 BPF2 - 2nd order bandpass filter. . . . . . . . . . . . . . . . . . . . 296.4 BPF1 - 1st order bandpass filter. . . . . . . . . . . . . . . . . . . . 306.5 The configuration for IMD measurements. . . . . . . . . . . . . . . 36

7.1 Block schematic for the modulation. . . . . . . . . . . . . . . . . . 397.2 A packet’s different components. . . . . . . . . . . . . . . . . . . . 397.3 The training sequence before and after NRZI encoding. . . . . . . 407.4 An example bit stream which has been bit stuffed. . . . . . . . . . 417.5 An example bit stream encoded with NRZI . . . . . . . . . . . . . 41

8.1 DSP48-slice in virtex 4. . . . . . . . . . . . . . . . . . . . . . . . . 448.2 DSP48E-slice in virtex 5. . . . . . . . . . . . . . . . . . . . . . . . 458.3 System overview for the first attempt. . . . . . . . . . . . . . . . . 458.4 The frequency response for the first decimation filter. . . . . . . . . 468.5 Impulse response for the second decimation filter. . . . . . . . . . . 478.6 Impulse response for the third decimation filter. . . . . . . . . . . . 488.7 System overview for the second attempt. . . . . . . . . . . . . . . . 508.8 The difference between the two DDS blocks. . . . . . . . . . . . . . 518.9 The frequency response for the complete decimation filter. . . . . . 528.10 A zoomed in portion of the frequency response in Figure 8.9. . . . 528.11 Impulse response for the first decimation filter. . . . . . . . . . . . 538.12 Impulse response for the filter h2 . . . . . . . . . . . . . . . . . . . 538.13 Impulse response for the filter h3. . . . . . . . . . . . . . . . . . . . 548.14 Impulse response for the filter h4 . . . . . . . . . . . . . . . . . . . 548.15 Impulse response for the filter h5. . . . . . . . . . . . . . . . . . . . 558.16 Impulse response for the filter h6. . . . . . . . . . . . . . . . . . . . 558.17 Impulse response for the filter h7. . . . . . . . . . . . . . . . . . . . 568.18 Impulse response for the filter h8. . . . . . . . . . . . . . . . . . . . 56

9.1 The impulse response for the correlation filter. . . . . . . . . . . . 629.2 An example output from the correlation filter. . . . . . . . . . . . . 629.3 Zoomed in on the detected message. . . . . . . . . . . . . . . . . . 63

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9.4 An example bit stream decoded from NRZI. . . . . . . . . . . . . . 63

10.1 Frequency response for board 1. . . . . . . . . . . . . . . . . . . . . 6610.2 Frequency response for board 2. . . . . . . . . . . . . . . . . . . . . 6610.3 Setup for SNR test, without and with external LNA. . . . . . . . . 6710.4 The setup for the sensitivity test for board 1. . . . . . . . . . . . . 7010.5 The setup for the sensitivity test for board 1 with LNA. . . . . . . 7110.6 The setup for the sensitivity test for board 2. . . . . . . . . . . . . 7210.7 The setup for the sensitivity test for board 2 with LNA. . . . . . . 7210.8 The setup for the blocking test. . . . . . . . . . . . . . . . . . . . . 7310.9 Plot from the IMD3 test on board 2. . . . . . . . . . . . . . . . . . 74

List of Tables2.1 Time-interleaved ADC matching requirements at 180 MHz clock

frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.1 SNR requirement at different sampling frequencies. . . . . . . . . . 276.2 Properties for the VGA. . . . . . . . . . . . . . . . . . . . . . . . . 286.3 Component values for the analog bandpass filters. . . . . . . . . . . 316.4 Current consumption of the first PCB . . . . . . . . . . . . . . . . 326.5 Current consumption of the second PCB . . . . . . . . . . . . . . . 33

7.1 Packet components and their sizes. . . . . . . . . . . . . . . . . . . 40

8.1 L2-norm scaling of the decimation filters. . . . . . . . . . . . . . . 588.2 SNR for different word lengths. . . . . . . . . . . . . . . . . . . . . 59

10.1 Properties for the external LNA. . . . . . . . . . . . . . . . . . . . 6710.2 SNR for a -70dBm signal without and with external LNA on board 1. 6810.3 SNR for a -70dBm signal without and with external LNA on board 2. 6810.4 SNR for various signal levels without and with external LNA on

board 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910.5 SNR for various signal levels without and with external LNA on

board 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910.6 Sensitivity test using PCB 1. . . . . . . . . . . . . . . . . . . . . . 7010.7 Sensitivity test using PCB 1 with external LNA. . . . . . . . . . . 7110.8 Sensitivity test using PCB 2. . . . . . . . . . . . . . . . . . . . . . 7210.9 Sensitivity test using PCB 2 with external LNA. . . . . . . . . . . 7310.10IMD test performed on board 2. . . . . . . . . . . . . . . . . . . . 74

11.1 Results from the tests . . . . . . . . . . . . . . . . . . . . . . . . . 77

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Chapter 1

Introduction

1.1 BackgroundSignal Processing Devices Sweden AB (SP Devices) was started in 2003, withan algorithm that solves the problems that occur when time-interleaving highprecision ADCs. The algorithm was a result of research done by Håkan Johanssonand Per Löwenborg at Linköping University.

The possibility of time-interleaving ADCs opens up many new fields for digi-talization. For example, with two 14-bit time-interleaved ADCs, sampling speedsof above 400 MSps can be achieved. This means that the Nyquist criterion can bemet for a 200 MHz bandwidth.

The field of software-defined radios (SDR) is a big research area. The SDRcan revolutionize the market of radio receivers. They are much more flexible andin some cases cheaper to produce than todays receivers.

The goal with this thesis is to show that SP Devices’ algorithm applied ontwo ADCs can be used to build a software-defined radio receiver for the VHF-band (112-174 MHz) with as few components as possible. This thesis work wasconducted at SP Devices in Linköping.

1.2 Purpose and MethodThe purpose of this thesis is to design, implement and analyze a prototype ofa software-defined radio for the VHF frequencies 112-174 MHz from idea all theway to a working prototype. The SDR architechture will be compared with thesuperheterodyne receiver architechture, which is commonly used today.

During this work an incremental method of development will be used. Byimproving the design in small steps, the work will advance in steps that are easilycontrolled. This will be achieved by first building a model of the SDR in Matlaband then implement it as a prototype in two steps.

Two versions of both the hardware and the software will be completed duringthe thesis. This will make it possible to make an attempt and then refine it

1

2 Introduction

and correct possible errors. The two versions are analyzed and their performancemeasured and compared.

1.3 PrerequisitesTo grasp this thesis the reader should have some previous knowledge of electronicsand concepts like field-programmable gate arrays (FPGAs). Also some under-standing of digital signal processing and radio technology could be useful.

1.4 ToolsDuring the work of this thesis some software tools have been used to complete thetasks of building a prototype. Here follows a description of the programs used anda description of their purpose.

1.4.1 ProtelProtel is a CAD program for designing printed circuit boards (PCB) and it alsoprovides the possibility to do simulations on schematic level.

The schematic of the front-end architechture was drawn and simulated beforethe PCB was designed. The PCB was then routed by hand before it was sent formanufacturing at Elprint1.

1.4.2 Matlab and SimulinkMatlab and Simulink was used to make a model of the system and to predict itsbehavior. Matlab is convenient to use when dealing with simulations of digitalprocessing. For simulations of the analog parts it is better to use Protel.

Matlab was also used for the decoding process and to present the results duringthe performance tests.

1.4.3 Xilinx ISEXilinx ISE is an integrated development environment (IDE) for Xilinx FPGAs. Ittranslates, synthesizes and routes the Verilog or VHDL code onto the designatedFPGA. In this project only Verilog was used. ISE is easy to work with and allowscode modules to be in different files, which makes the development process mucheasier. It is free if developing for Xilinx Virtex 4 FPGAs, but needs a license whenusing a Xilinx Virtex 5.

1.4.4 Microsoft Visual StudioC code was written to produce a dynamically linked library (dll) file used bymatlab to fetch data from the usb port. It was written and compiled in the

1http://www.elprint.se

1.5 Restrictions 3

Microsoft Visual Studio environment. Visual Studio is Microsoft’s IDE for C,C++ and many more languages.

1.5 RestrictionsThis thesis work will produce a prototype for decoding a specific kind of digitalmessages that are modulated with GMSK. No other modulations will be treatedor discussed. This report analyzes the prototypes designed and it will not coverany other solutions.

1.6 Report DispositionThis report will present the work performed during this thesis and its results. Thefirst chapters cover the more theoretical parts while the later chapters describe thework and the results.

Chapter 2 explains the problems that come up when time-interleaving ADCs,and the solution that SP Devices has developed. Chapter 3 will explain moreabout how SDR works and what the advantages are compared to the commonsuperheterodyne receivers that are commonly used today. It is followed by Chapter4 that discusses the parameters of a receiver performance, while Chapter 5 presentsthe requirements for this project.

The work performed in this thesis will then be presented. It starts with thePCB and its analog front-end in Chapter 6. The data packages that are used fortesting the receivers’ performance is explained in Chapter 7. It is followed by thedescription of the digital signal processing performed in the FPGA in Chapter 8and the PC in Chapter 9.

The tests and their results are described in Chapter 10. Finally the conclusionsmade in this thesis are presented in Chapter 11 together with some ideas of howto continue with this work.

1.7 Reading InstructionsThose who have good knowledge in electronics and radio technologies could skipthe first theoretical chapters, except for Chapter 5 which could be good to haveread to understand the decisions made in Chapter 6.

The most interesting chapter is probably Chapter 10 where the results arepresented.

4 Introduction

Chapter 2

Linearizer

To achieve high speed analog-to-digital conversion, time-interleaving multiple ADCsseems to be a good solution. This has been used for low resolution ADCs since1980, but higher resolutions matching problems deteriorate the quality of the sig-nal.

An 8-bit system that provides a dynamic range of 50 dB can tolerate a gainmismatch of 0.25% and a clock-skew error of 5 ps. This accuracy can be met bytraditional methods like, matching the physical channel layouts, using commonADC reference voltages, prescreening devices, and active analog trimming, butthis is not enough for higher resolutions[10].

The problems that need to be considered when ADCs are interleaved are shownin figure 2.1 were four ADCs have been time interleaved.

In this chapter the problems caused by interleaving will be discussed and thenSP Devices’ algorithm for solving these problems will be presented.

Resulting digital signalDesired digital signal

Figure 2.1. Effect of problems that occur when interleaving ADCs.

2.1 Problems with Interleaved ADCsThere are three main categories of problems that arise when ADCs are interleaved.They all come from the fact that it is impossible to manufacture two silicon chips

5

6 Linearizer

that are identical. The surrounding environment also affects how well the ADCsmatch, e.g., if they have different temperature. This results in differences in gain,offset and timing, which affects the output in a way depicted by the Figure 2.1.For narrowband signals, there will be unwanted spurious frequencies in the outputsignal, called spurs.

ISgain(dB) = 20 log(ISgain) = 20 log(

Ge

2

)(2.1)

Ge = gain error ratio =∣∣∣∣1− VFSA

VFSB

∣∣∣∣ (2.2)

ISphase(dB) = 20 log(ISphase) = 20 log(

θep

2

)(2.3)

θep = ωa∆te(radians) (2.4)ωa = analog input frequency (2.5)

∆te = clock skew error (2.6)

IStot(dB) = 20 log(√

(ISgain)2 + (ISphase)2)

(2.7)

From equations 2.1 - 2.7 it is possible deduce that even very small divergencesbetween the ADCs will result in large spurs that will deteriorate the dynamic range.Table 2.1 shows the matching requirements for a time-interleaved system[10].

Number of bits SFDR Gain Matching Aperture Matching(dBc) (%) (fs)

12 74 0.04 012 74 0 35012 74 0.02 30014 86 0.01 014 86 0 8814 86 0.005 77

Table 2.1. Time-interleaved ADC matching requirements at 180 MHz clock frequency.

2.1.1 Gain Mismatch

The gain error cause the ADC to affect the output by changing the signal am-plitude. As seen in Figure 2.2, this would not affect the signal noticeably if onlyone ADC was used, but when two ADCs are interleaved it will result in aliasingdistortion. The differences in gain between two ADCs affects the output even if itis as small as 0.01%, as shown in equations 2.1 and 2.2. The spurs deteriorate thesignal quality, or destroy the wanted signal if they coincide.

2.1 Problems with Interleaved ADCs 7

Gain error

Figure 2.2. Result of a gain error in an ADC.

2.1.2 Offset Error

An ADC has a small DC offset in its output, and when using two ADCs they willhave different offsets. When two ADCs are time-interleaved different offsets willresult in a spur at π. The figure 2.3 shows an exaggerated offset error.

Offset error

Offset

Figure 2.3. Result of an offset error in an ADC.

2.1.3 Time-Skew

Time-skew errors, or phase errors, arise when the ADC’s samples are taken at thewrong instants in time. When more than one ADC samples the signal the time-skew will be experienced as a phase error. This will cause aliasing distortion thatcoincide with the gain error[10]. The time-skew is depicted in Figure 2.4, wherethe samples are taken with a delay in time.

8 Linearizer

Time skew

Figure 2.4. Result of time-skew in an ADC.

2.2 The SolutionSP Devices has developed a clever algorithm, called linearizer, that corrects theseerrors by filtering the digital result. Figure 2.5 shows a block diagram of thelinearizer.

ADC 1

ADC 2

Reconstructor

Estimator

Monitor&

Control

Linearizer

Figure 2.5. The block diagram of the linearizer

The linearizer is purely digital and uses advanced signal processing algorithmsto correct the errors mentioned in the previous section. Since the correction isdone digitally it can function with any ADC. The linearizer could also be used toincrease the resolution while maintaining the speed.

The estimator uses a batch of data to estimate the different errors. Theseestimates are used for calculating the filter coefficient values. The coefficients arethen passed on to the reconstructor. The reconstructor block consists of a filterthat corrects the errors from the differencies in the ADCs in real time.

By using the linearizer, as depicted in Figure 2.6 it is possible to construct veryfast ADCs with high performance, that opens up many new possibilities in fieldspreviously not conceivable. The software-defined radio developed in this thesis is

2.2 The Solution 9

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

Linearizer

Figure 2.6. Interleaved sequencies with missmatch, before and after linearization.

just one example made possible by the linearizer.

10 Linearizer

Chapter 3

Superheterodyne vs. SDR

3.1 IntroductionThis chapter will explain the pros and cons of the commonly used superheterodyneradio frequency (RF) receiver and a software-defined radio (SDR) receiver. It alsocovers the differences between the two types and why the SDR receiver togetherwith SP Devices’ technology is preferred in a broadband RF receiver where smallarea, low power consumption and low cost are the main requirements.

3.2 Traditional Superheterodyne RF ReceiverOne of the most common RF receiver architecture types used in radio applicationsfor the last century and today is the superheterodyne receiver. This receiver typeis often preferred because of its great performance regarding receiver character-istics such as sensitivity and selectivity. A simple description of the traditionalsuperheterodyne architecture can be seen in the block diagram in Figure 3.1.

RF

Filter

LNA

BPF

LO

IF Amp

BPF

AGC Amp

IQ-

demodulator

Rx

IQ

Figure 3.1. Superheterodyne receiver architecture

The first block after the antenna is an RF bandpass filter (BPF) which atten-uates the undesired out-of-band frequencies. The signal is then amplified in a lownoise amplifier (LNA) which amplifies the signal with relatively low noise contri-bution. This device is the most crucial part of the receiver chain because of themany system requirements depending on it. After the amplification and bandpassfiltering the signal is down-converted by a mixer. This process is the principle of

11

12 Superheterodyne vs. SDR

heterodyning which is the generation of an intermediate frequency by mixing (mul-tiplying) the incoming high frequency signal with another high frequency signalgenerated by a local oscillator (LO). The mixer circuit has significant requirementson linearity and noise and can cause severe DC-offset problems in the receiver.

The generated IF-signal is amplified in the IF-amplifier before selection of thedesired channel in the last BPF. In the last stage the signal amplitude is adjustedby the automatic gain control (AGC) to fit the dynamic range of the analog-to-digital converter(s) (ADC).

3.2.1 Advantages

• A major advantage of the superheterodyne receiver is that by mixing downthe signal to lower frequencies the cost of the components reduces. Gener-ally for RF components, such as filters and mixers, cost is proportional tofrequency[4]. This is due to the fact that low frequency components are lesscomplex and easier to find/build.

• The down-conversion to IF gives the receiver high selectivity i.e. high abilityof sorting out the desired signal by supressing the undesired signals. This isbecause the requirements on the filters are relaxed when operating at lowerfrequencies (IF), which makes it easier to build more effective selective filterswith much narrower passband.

3.2.2 Disadvantages

• One of the biggest cons of the superheterodyne receiver is the amount ofexternal components. The wider frequency spectrum the harder it is to findor build narrow-passband filters to a reasonable cost, if not impossible. Morecomponents means higher cost, higher power consumption, larger area andhigher architecture complexity.

• The complexity mentioned above leads to another problem which is the lowachievable level of integration. This also depends on the fact that the highperformance of discrete components is hard to achieve in an integrated so-lution.

• Another problem in this architecture is the mixer and local oscillator stages.One problem that is associated with mixer circuits, besides the cost, is theso called LO-leakage. This leakage can get mixed with the oscillator itselfand/or get picked up by the antenna and get amplified in the LNA producinga spur.

• The wanted channel is predefined by hardware. Each channel require aseparate receiver which increases the need of hardware if multiple channelsare desired.

3.3 Software-Defined Radio Receiver 13

3.3 Software-Defined Radio ReceiverOne of the newest and most interesting concepts in radio architecture developmentis software-defined radio (SDR). In this thesis project only the receiver part isdiscussed.

The basic idea of the SDR receiver is to digitalize the incoming analog RF signalas close to the antenna as possible and then do the signal processing digitally. In anideal SDR receiver the ADC(s) would be attached directly to the antenna sendingthe samples to some kind of processor (FPGA, DSP etc.) where the data would betransformed/shaped as desired by software. The sampling frequency (fs) wouldhave to be greater than twice the signal bandwidth to be able to reconstruct thesignal from the digital samples (Nyquist theorem)[11]. In practice this is hard toachieve due to the fact that todays ADC:s with the required resolution, are yettoo slow to receive radio signals at higher frequencies.

In current commercial software receivers the problem mentioned above is solvedby mixing down the radio signal to a lower frequency using local oscillators, asmentioned above in Section 3.2. This will not be the case here hence the main goalis to significantly reduce the use of analog hardware. Instead the problem is ap-proached by taking advantage of time-interleaving. As it was described in Chapter2, interleaving allows faster fs than the specified fs of the ADC. By interleaving NADCs the fs could be N times the fs of a single ADC. Also described in Chapter2 was that SP Devices algorithm makes it possible to interleave high-speed ADC:swithout degrading the resolution. This technology allows high enough samplingfrequency for sampling the signal without requiring down-conversion, i.e. no mix-ers or local oscillators are needed.

The hardware architecture used in this project is further explained in Chapter6.

3.3.1 Advantages• The SDR receiver has the ability to receive different modulation types while

using the same hardware platform.

• Its funcionality can be changed by downloading and running new softwarewhenever desired, without any change of hardware.

• Reduction/elimination of the use of analog hardware which means lowercost, lower power consumption, smaller area needed and lower architecturecomplexity.

• The channel is not predefined by hardware which means that any channelwithin the bandwidth can be chosen by software. It is even possible to receiveseveral channels in parallel.

3.3.2 Disadvantages• Finding the right components, such as amplifiers, for a flexible front-end can

be rather hard due to problems like linearity, dymanic range, noise figure.

14 Superheterodyne vs. SDR

• Filters are expensive and hard to design for such broadband applications.

• Writing software for different applications can be quite complex.

Chapter 4

Basic RF Receiver Concepts

4.1 Signal-to-Noise RatioSignal-to-noise ratio (SNR) is the ratio between the power of the desired signal andthe average power of the noise in the system. In other words, the higher SNR theless noise in the system and the clearer signal. SNR is calculated using Equation4.1[11].

SNR = 10 log(

Psignal

Pnoise

)(4.1)

In the process of choosing components for the receiver it must be consideredhow much a specific component affects the overall SNR, due to its noise contribu-tion. This means that in order to do an approximate calculation of the systemsSNR for a specific signal level the total receiver noise must be calculated. Thesection below shows the equations used for noise calculation. The SNR calulationsfor this system are done in Section 6.3.1.

4.2 Receiver NoiseIn order to do a calculation of the receiver noise the thermal noise at the antennamust be calculated by using Equation 4.3[21] is Boltzmann’s constant, T is ab-solute temperature in kelvins and B is the Nyquist bandwidth, fs/2. Usually inreceiver noise calculations T is chosen to be 290K and gives 10log kT = -174 dBm.dBm is a representation of a power level in dB relative to 1 mW. This representa-tion gives a clue of how much stronger the measured signal is in comparison with1 mW.

Nth = kTB (4.2)Nth(dBm) = 10 logkT + 10 logB =

= −174dBm + 10 log B (4.3)

15

16 Basic RF Receiver Concepts

After the calculation of the thermal noise the noise and gain contribution of allparts in the receiver are added, as shown in Equations 4.4 - 4.5. Nin is the totalnoise power of the receiver before the A/D-conversion.

Fi =Ni−1 + Ni

Ni−1= 1 +

Ni

Ni−1⇒

⇒ Ni

Ni−1= Fi − 1 (4.4)

Nin = G1G2kTB + G1G2[F1 - 1]kTB + G2[F2 - 1]kTB =

= G1G2[F1 +F2 − 1

G1]kTB =

= GsysFsyskTB[W] (4.5)

Equation 4.5 represents the noise in a system containing two gain and/or noisecontributing devices. Fi is the noise factor of the i:th device after the antennaand Gi is the gain factor of ditto. As shown in Equation 4.5, the noise factor ofa device is divided by the gain factor of all previous devices. This means thatdevices that are placed far from the antenna contributes less to the overall noisethan the ones closer to the antenna.

Notice that all noise and gain factors for the cascaded parts are linear valuesnot logarithmic. Usually in the devices’ data sheets the noise is represented asnoise figure (NF). NF is the common logarithm of the noise factor.

4.3 Intermodulation Distortion & Intercept PointIntermodulation distortion (IMD) occurs when two or more different input fre-quencies exist in a device, resulting in production of undesired output signals(intermodulation products) at other frequencies. This is a problem in all ampli-fiers and mixers but also in passive components. In this project only amplifiersand passives are taken into account because of the absence of mixers. These in-termodulation products (IMD products) are produced at the sum and differenceof integer multiples of the existing frequencies. Equation 4.6 expresses the outputfrequency components when two different input frequencies exist in the device,which results in two-tone intermodulation distortion.

IMD = m · f1± n · f2 (4.6)

The sum of the integers m and n in Equation 4.6 defines the order of the IMDproduct. Most of these products are either too weak to be detected or too far awayto interfere with the desired frequencies. Generally in RF systems, and in the caseof this project, the third-order products (IMD3: 2f1 + f2, 2f1 − f2, 2f2 − f1,2f2 + f1) are of great concern, since the probability of them falling inband andinterfere with the desired frequency is high[21]. Intermodulation rejection raitois the ratio between the desired signal and the highest IMD3 product. It is an

4.3 Intermodulation Distortion & Intercept Point 17

imortant parameter which describes the receivers ability to handle strong IMDproducts.

Commonly IMD3 products are specified in terms of third-order intercept point(IP3). This is a measure of the devices tolerance against interfering signals outsidethe desired passband. In Figure 4.1[7] the output power is plotted versus the inputpower, both in logarithmic scale. It is shown that both the output signal and theIMD3 product increase linearly with increased input signal. For every 1-dB ofsignal increase the IMD3 product amplitude increases 3 dB because of increaseddistortion in the device. At a certain level of input signal strength the wantedsignal and the IMD3 product will be equal. This point is called the IP3 whichusually is referenced to either the input or the output of the device. IIP3 is theinput power at the IP3 and OIP3 is the output power at the IP3. The relationshipbetween the two is OIP3 = IIP3 + system gain.

Figure 4.1. Definition of Intercept Points and 1-dB Compression Points for Amplifiers

Also seen in Figure 4.1 is the 1-dB compression point which shows the inputsignal level at which the receiver begins to get a non-linear amplitude response.This means that the device is linear up to a certain input signal level after whichthe output becomes saturerad and stop increasing with increased input signal.Both IP3 and 1-dB compression point are important parameters in the choice ofamplifiers and most often one or both these values are given in the devices datasheet.

The power of an intermodulation product is calculated using Equation 4.7[5].PIMout is the power of the IMD product at the output of the device and Pout isthe signal power at the output.

PIMout = 3 · Pout − 2 ·OIP3 (4.7)


This equation will be used in Section 6.3.2 to calculate a theoretical value ofthe total PIM generated in the chosen system configuration.

4.4 Dynamic RangeDynamic Range (DR) is the ratio between the maximum and the minimum signalthat a receiver is designed to handle simultaneously. This measure is used fordescribing the limits of receivers. DR is of great concern in SDR solutions becauseof the wide frequency band of interest where signal levels can differ significantly.

4.5 Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) measures the ratio between the root-mean-square (rms) level of the desired signal and the rms level of the highest spur in thespectrum. It is an important parameter in cases where harmonic distortion andspurious signals are undesirable. One example of these cases is analog-to-digitalconverters (ADCs) in which noise and harmonics limit the dynamic range.

4.6 Effective Number of BitsThe ADC resolution is defined as the number of bits at its output, i.e. the sizeof the binary word which represents the sampled analog signal. An alternativedefinition is the size of the least significant bit (LSB), Equation 4.10. It should benoted that it is not a measure of the conversion quality. There are different errorsources in an ADC degrading its performance. When all sources are included, theresolution is usually lower than the specified number of bits of the converter[11].That is why the effective number of bits (ENOB) of an ADC is such an importantparameter and represents the noise-free bits. ENOB is a measure of the ADCsaccuracy at a specific input frequency. It is calculated using Equation 4.9[11]. Asseen in the equation the value of SNDR is needed for the calculation of ENOB.SNDR is signal-to-noise-and-distortion ratio and is defined similarly as SNR exceptit also includes distortion. See Equation 4.8[11]

SNDR = 10 logPsignal

Pnoise + Pdistortion(4.8)

ENOB =SNDR− 1, 76

6.02(4.9)

4.7 Oversampling in Analog-to-DigitalConverters

As mentioned earlier in Section 3.3, in order to reconstruct a signal from its digitalsamples it must be sampled at a frequency that is greater than twice the bandwidth

4.7 Oversampling in Analog-to-DigitalConverters 19

i.e. Nyquist’s criterion. If fs/2 is higher than the Nyquist frequency the ADC isconsidered to be oversampled. By oversampling the ADC(s) the overall SNR isincreased. The reason of this is explained below.

Quantization noise is introduced in the ADC when the continuous analog signalis quantized to discrete values[11]. This quantization noise is a fixed power and isindependent of the input signal, as shown in eq 4.11[21] This noise is spread outover the Nyquist bandwidth, which is dc up to fs/2. If the ADC is oversampledthe noise is spread out over a wider range of frequencies. So the wider fs the lowernoise floor, i.e. higer SNR. This improvement of the SNR is called oversamplinggain or process gain, see Equation 4.12.

Vlsb =Vp−p

2N (4.10)

Pqn =Vlsb

2

12R(4.11)

process gain = 10 log(

fs/2BW

)(4.12)

Chapter 5

Requirements

Several requirements regarding the receiver’s performance are set up for thisproject. These requirements will be presented in this chapter. Also some ba-sic RF receiver concepts will be explained in order to make the understanding ofthe requirements easier.

5.1 Bandwidth

The bandwidth (BW) of the receiver in this project is desired to be between 112-174 MHz. This wide BW of 62 MHz sets major requirements on the analog filtersin the receiver. The filter requirements and problems caused by the wide BW areexplained in Section 6.2.3.

5.2 Sensitivity

Receiver sensitivity is the lowest signal level that is detectable by the receiver.The requirements regarding sensitivity in this project is that the receiver must beable to decode a modulated message at 162 MHz with a signal level of -107 dBm.A packet error rate (PER) of 20% is allowed. The modulation type of the signalis discussed in Chapter 7.

The highest detectable signal is required to be -7 dBm. The number of un-correctly received messages at this level should not differ by more than 10 fromthose received at -77 dBm. These boundary values of the signal level give a spanof 100 dB. It should be kept under consideration that all the components usedin the analog front-end must have proper performance at all levels of the 100 dBinterval.

21

22 Requirements

5.3 Intermodulation Response Rejection andBlocking

Intermodulation response rejection is the receivers ability to supress IMD productscaused by two or more undesired signals. The frequencies of these signals have aspecific relationship to the desired signal frequency. A blocker on the other handis a strong out-of-band interferer that sets requirement on the receivers DR. Theblocker signal sets limitation on the maximum allowed receiver gain.

In this project the receiver must be able to decode messages with 20% PER ata level of -101 dBm in presence of two IMD products at -27 dBm and a blockersignal at -15 dBm. One of the IMD products is adjusted 500 kHz below or abovethe wanted frequency and the other is adjusted 1000 kHz below or above it. Theblocker signal is adjusted 5MHz below the wanted frequency. The input desiredsignal is adjusted to the same frequency as the previous test. This test is consideredto simulate the worst case scenario.

5.4 Adjacent Channel SelectivityThe adjacent channel selectivity is the receivers ability to receive desired signals inpresence of an undesired interfering signal at the frequency of the channel directlyabove that of the desired signal. The requirment on the adjacent channel selectivityof the receiver is that it shall not be less than 70 dB.

5.5 Signal-to-Noise RatioAs mentioned in Section 5.3 the receiver must be able to operate despite theexistence of a blocker signal and two IMD products. In this worst case scenarioit is possible that the mentioned signals interfere with each other, hence theiramplitudes will be added together, creating an amplitude even higher than theamplitude of the blocker signal alone. This amplitude is calculated by using theequations below.

A =√

50 · 10−3 · 10PdBm/10, conversion of dBm to V (5.1)

P =A2

R(5.2)

Atot = Asig + Ablocker + AIMD1 + AIMD2 (5.3)

Ptot,dBm = 10 log(

A2tot

R · 10−3

)(5.4)

DR = Ptot,dBm − Psignal (5.5)

The resistor value R in Equation 5.2 is 50 Ω and is the antennas load resistance.In this case the signal caused by the mentioned interference is at a level of -11.5dBm. The difference between this level and the desired signal level at -101 dB

5.5 Signal-to-Noise Ratio 23

gives a DR of 89.5 dB. The decoder that is used for decoding the received messagesrequires an SNR of 12 dB. This means that the receiver need an overall SNR of atleast 89.5 + 12 = 101.5 dBFS to be able to decode a received message. dBFS is arepresentaion of the ratio between a signal and the full-scale signal of a system.

For the sensitivity test the required SNR is different from above due to thereceiver gain which is decided by the gain in the amplifiers and possibly the filters.Thus the SNR of this test will be presented after the components has been chosen,see Chapter 6.

24 Requirements

Chapter 6

Analog Front-End

This chapter covers the chosen architecture of the analog front-end and motivatesthe choice of components for both PCB versions. Also both PCB designs arepresented together with the measures taken to prevent EMC problems.

6.1 Front-End ArchitectureAs mentioned earlier the main goal of this project is to build an RF receiver for therequired frequency band containing as few analog parts as possible. This achieve-ment is possible due to the concept of SDR together with SP Devices technology.As was mentioned in Section 3.3 this technology makes it possible to build a socalled direct sampling receiver witout using mixer circuits and local oscillators forfrequency down-conversion. Despite this fact the ADCs can not be directly at-tached to the antenna due to a couple of reasons. One reason is that without someattenuating bandpass filters strong undesired signals could saturate the ADCs.Another reason is that without amplification the weakest signals would never getstrong enough to get sampled properly by the ADC. The closer a signal is to theADC’s input voltage range the more bits of the ADC are used. Figure 6.1 showsthe chosen architecture for the analog front-end.

BPF1 BPF2LNA AGC

ADC1

ADC2

DAC FPGA

Figure 6.1. The architecture of the analog front-end.

The first bandpass filter (BPF1) is intended to attenuate undesired out-of-bandfrequencies. The signal is then differentiated passing through a 1:1 transformer.

25

26 Analog Front-End

The reason for differentiating the signal path is to reduce the sensitivity of distur-bance in the transmission lines. This is further explained in Section 6.4.

After the first filter the signal is amplified in a low noise amplifier (LNA), whichis the most crucial part of this design due to the noise and IMD requirementsdepending on it, see Section 6.2.2. The second bandpass filter (BPF2) is meantto filter out the wanted signal further before its amplitude is adjusted by thevariable gain amplifier (VGA). The VGA is controlled to either amplify the signalor attenuate it, depending on the signal level. This is called automatic gain control(AGC) and is intended to push the signal amplitude as close as possible to theADC:s input voltage range.

The last stage of the front-end is the A/D-conversion. Here the two interleavedADCs digitalize the received signal and feeds it through to a field-programmablegate array (FPGA) where the data is processed. The data processing in the FPGAis explained in Chapter 8.

This front-end architecture is used on both PCB:s. The only difference is thatin the first case the FPGA is off-board and is placed on a development board. Onthe second PCB the FPGA is placed on-board.

6.2 Choise of ComponentsIn this section the chosen components are presented together with the motivationof why they were chosen. Choosing and finding the right components for the analogfront-end is very challenging. The choice of the different parts of the receiver mustbe done in parallel, because the properties of all parts depend on each other. Inthis project the ADC is chosen to be the starting point.

The components used in the front-end alone do not differ between the twoboards. The major difference is that the FPGA is mounted on-board in the secondattempt while in the first case an external development board handled the signalprocessing.

6.2.1 ADCThe analog-to-digital conversion is usually the part that limits the performanceof the receiver. The most important parameters in choosing this component areresolution, sampling frequency, SNR and SFDR.

SNR and fs

Some calculations were done on the some of the ADC parameters, mentioned inChapter 4, at different sampling frequencies, see Equations 6.1 - 6.3. As it isshown, the channel bandwidth is chosen to be 25 kHz which is usually the case inthe VHF band[14]. The results of the calculations can be seen in table 6.1.

The ADC resolution is defined as the number of bits at its output, i.e. the sizeof the binary word which represents the sampled analog signal. An alternativedefinition is the size of the least significant bit (LSB), Equation 4.10. It should benoted that it is not a measure of the conversion quality. There are different error

6.2 Choise of Components 27

sources in an ADC degrading its performance. When all sources are included, theresolution is usually lower than the specified number of bits of the converter[11].That is why the effective number of bits (ENOB) of an ADC is such an importantparameter and represents the noise-free bits.

Some calculations were done on the mentioned ADC parameters at differentsampling frequencies, see Equations 6.1 - 6.3. As it is shown, the channel band-width is chosen to be 25 kHz which is usually the case in the VHF band[14]. Theresults of the calculations can be seen in table 6.1.

SNRreq = 101.5dB (6.1)BWch = 25kHz (6.2)

SNRideal = SNRreq − 10 log(

fs/2BWch

)(6.3)

fs SNR340 63.2105380 62.7274420 62.2928460 61.8977500 61.5356

Table 6.1. SNR requirement at different sampling frequencies.

The table above shows that the required values of SNR lessens with increasingfs, which is a good reason to choose a high fs. Besides, considering the advantagesof oversampling that were mentioned in Section 4.7, choosing fs high would helprelaxing the requirements on the analog filters and improve the overall SNR.

The chosen architecture includes two interleaved ADC:s, as mentioned earlier.After spending relatively short time searching among the leading manufaturers,it was noted that the 14-bit ADC called ADS5546 from Texas Instruments wasbest suited for this applicaion. The maximum fs is 190 MHz which means a totalfs of 380 MHz after interleaving. The ideal SNR of this converter is 72.2 dBwhich is almost 10 dB higher than the required SNR for this fs, also shown inthe same table. Some calculations are done in Section 6.3 to show that this ADC,theoretically, fulfills the system requirements mentioned in the previous chapter.

6.2.2 LNA and VGAWhen choosing amplifiers for this project the most important parameters are theNF and the OIP3. Due to the inefficient analog filtering in this project it is prefer-able to have as linear components as possible to avoid intermodulation productsin the system. Because of this the OIP3 and the 1-dB compression point of theamplifiers must be as high as possible.

28 Analog Front-End

As mentioned in Section 4.2 it is extra important that the components nearestto the antenna have low NF because the noise contribution affects the overall noisemore in the early stages of the receiver chain. So it is of great importance thatthe LNA has low NF. As it was shown in Equation 4.5, it is also preferable tohave high gain in the LNA or the other parts in the begining of the receiver chain.This makes the noise contribution of the following parts less important due tothe division with the gain factor of the previous parts. Because of the differentialsignaling used in the design, the LNA should have differential input and output.

Finding an LNA with the mentioned characteristics is hard. After evaluatingthe data sheet of many LNA:s it was decided to use the ADL5330 from AnalogDevices. This amplifier is a VGA which gain can be fixed by attaching the controlpin to a fix voltage. The level of the fixed gain depends on the voltage level onthe control pin. The amplifier has an acceptable NF and a high OIP3. Someproperties of the circuit are presented in Table 6.2.

The same amplifier circuit is used for the AGC in this project. As it is presentedin Table 6.2 the gain can be adjusted between -34-22 dB. The control signal rangeis between 0-1.4V which means that if the control signal is 0V the gain of the VGAis -34 dB, and if the control signal is 1.4 V the gain is 22 dB.

Calculations in Section 6.3 shows that this amplifier fulfills the requirementstheoretically.

Gain -34 - 22 dBNF 7.8 dB

OIP3 38 dBm1dB Compression point 22 dBm

Table 6.2. Properties for the VGA.

6.2.3 Analog FiltersBPF1 and BPF2 in Figure 6.1 are two analog BP-filters that are intended toselect out the desired band and attenuate the neighbouring undesired bands. Thefrequency range of interest in this project is required to be 112-174 MHz, whichbelongs to the VHF-band. This means that the filters should have a passband of62 MHz with a center frequency of 143 MHz. This passband should not attenuatethe test signal at 162 MHz mentined in the test sections. The absence of mixercircuits, i.e. frequency down-conversion, in the receiver makes it very hard to findhighly selective filters with such wide passband at such high frequencies with lowinsertion loss. Insertion loss in a filter is the ratio between the input power andthe output power. It is a measure of the power loss in the device. In other wordsthe passband attenuation in the filter.

However, a filter type commonly used in RF applications is surface acousticwave filter (SAW). Their main properties are that they can be designed physicallysmall providing good out-of-band rejection, broad pass-band and steep transitionedges. With these filter characteristics the SAW filter appears to be the right


choice for this application. But after spending hours and hours searching amongmanufacturers’ standard products, it was noted that finding a suitable SAW fil-ter is an impossible task due to their extremely high insertion loss. The chosenarchitecture can not afford this high level of insertion loss, hence with even zeroinsertion loss in the filters it still is a challenge achieving the required sensitivity of-107 dBm. Some manufaturers have the possibility of building customized filtersbut for a cost that is over budget in this thesis project.

After considering the facts and the given options it was decided to build thefilters as passive bandpass filters with discrete components. A filter with thementioned characteristics require high filter order. The higher the filter orderthe more discrete components are required. So a decision was made to loosen therequirements to be able to build low-order filters with a few components. It shouldbe noted that with more time and higher budget the filters could be built muchbetter, but for now passive low-order filters will do.

The first bandpass filter is a second order LC-filter with only one inductorand one capacitor, see Figure 6.2. The second filter is a fourth order LC-filter, asshown in Figure 6.3. An advantage of the implemented filters are that they haveno insertion loss.

Zi=50 Ohm Ro=50 OhmC L

Figure 6.2. BPF1 - 1st order bandpass filter.

Zi=50 Ohm Ro=50 Ohm

C2L2

C1L1

Figure 6.3. BPF2 - 2nd order bandpass filter.

As it is shown in the figures above both analog filters have 50 Ω impedance onboth input and output. This depends on the output and input impedances of thecomponents attached before and after the filters. In order to get the impedancesmatched it is necessary to choose the component values so that the resonancefrequency of the filter circuits is equal to the desired signal frequency. Impedancematching between components is very important in order to avoid reflections in

30 Analog Front-End

the signal path. The resonance frequncy is easily calculated in both these cases,see equations 6.4[16].

Zi = Ro +1

jωC+ jωL (6.4)

The impedance is matched if Zi = Ro. In order to make this happen thecomponent values must be chosen so that 1

jωC + jωL = 0. This leads to equation6.6 which is used for calculating the resonance frequency of the filter, which in thiscase means the least filtered frequency.

The chosen component values, see table 6.3 give an overall bandwidth of about60 MHz with a center frequency around 160 MHz, which suits this project hencethe required test signal is situated at 162 MHz. A frequency analysis was done inProtel on the two filters, which frequency responce can be seen in Figure 6.4.

75.00MHz 100.0MHz 125.0MHz 150.0MHz 175.0MHz 200.0MHz 225.0MHz 250.0MHz 275.0MHz 300.0MHz

0.000 dB

-2.500 dB

-5.00 dB

-7.50 dB

-10.00 dB

-12.50 dB

-15.00 dB

Am

plit

ud

e [d

B]

Frequency [MHz]

Figure 6.4. BPF1 - 1st order bandpass filter.

ω =1√LC

(6.5)

f =1

2π√

LC(6.6)


Filter Component ValueBPF1 C 100pF

L 10nHBPF2 C1 100pF

L1 10nHC2 100pFL2 10nH

Table 6.3. Component values for the analog bandpass filters.

6.2.4 FPGAAs shown in Figure 6.1 the digitalized signal from the ADC:s is fed through to anFPGA where the data is processed. The first PCB does not include the FPGA.Instead the front-end PCB is attached to a development board which includes aVirtex 4 FPGA from Xilinx. On the second board the front-end and the FPGAare placed on the same PCB. This time the Virtex 5 from Xilinx was used. TheseFPGAs can be programmed in two ways. One way is to directly program it via aJTAG-connection from the PC. This way the program is erased when the poweris switched off and the FPGA must be reprogrammed at power on. The secondway is to use the flash memory placed on-board. By programming the flash theFPGA can reprogram itself everytime the power is switched on.

After the FPGA the processed data is sent to a PC where the data is de-coded. For transmitting and receiving data to and from the PC a UART-interfacewas implemented in the FPGA. In the PC however the USB port was chosen ascommunication link. This means that a USB-to-UART converter is needed. Theconverter used is presented in the next section.

6.2.5 USB-to-UART InterfaceFor converting the FPGA:s UART-signals to the PC:s USB-signals and vice versaa converter from FTDI called FT232R was used. In the case of the first PCB thisconverter is built-in in a cable that is used for the communication between thedevelopment board and a PC. In the second case the converter is built-in in a chipwhich is placed directly on the PCB between the FPGA and a type B USB-port.According to the data sheet of FT232R it can handle up to 3 Mbits/s.

6.2.6 DACAs mentioned above the chosen VGA has an analog control signal input. So thedigital control signals from the FPGA must be converted to an analog signal witha digital-to-analog converter (DAC), as shown in figure 6.1. For this task a DACcalled AD7302 from Analog Devices was chosen. It has a parallel 8-bit input andan output voltage range of 5V, which means that the output changes by steps of5/28 ≈ 0.0195 V. This step size gives the VGA 1.4/0.0195 ≈ 72 different gain

32 Analog Front-End

settings. So only 7 bits of the DAC are needed, thus 26 = 64 is too few and28 = 256 is too much.

6.2.7 Crystal Oscillator and Clock BufferThe ADCs need to have a clock signal that determines the sampling frequency.As mentioned in the ADC section the decided sampling frequency in this projectis 380 MHz. This means that the interleaved ADCs have an fs of 190 MHz each.

On the first board the clock signal is provided from an external signal generator.The generator provides a 380 MHz signal which gets divided into two 190 MHzclock signals by a clock buffer called CDCP1803 from Texas Instruments. Thedivided clock signal is then distributed to the ADC:s.

On the second board the signal is generated from a crystal oscillator whichprovides a 380 MHz signal. The oscillator is a Si530 from SiLab. In the same wayas the first board the signal from the oscillator is divided into two 190 MHz signalsin a clock buffer.

6.2.8 Linear Voltage RegulatorsThere are two different supply levels used on the first board and four differentlevels on the second. The first board contains 3.3V digital, 3.3V analog and 5Vanalog supply. The second board contains 1V digital, 2.5V digital, 3.3V digital,3.3V analog and 5V analog supply.

The reason of why the digital and the analog supplys are split up will beexplaind in Section 6.4. For the supply management some linear voltage regulatorsfrom Texas Instruments and Maxim are used. See Table 6.4 for the first boardand Table 6.5 for the second. The TPS786xx is from Texas Instruments and hasa maximum output current of 1.5A and the MAX8869 has a maximum outputcurrent of 1A. As it can be seen in the Tables 6.4 and 6.5 the amount of currentthat needs to be supplied is kept under the maximum limit on all regulators.

Regulator Component Quantity Supply Current(mA)TPS78601 DAC 1 5(Analog, 5V) VGA 2 215

Sum 435TPS78633 ADC 2 300(Analog, 3.3V) Sum 600TPS78633 ADC 2 51(Digital, 3.3V) Clk buffer 1 140

Sum 242Sum(tot.) 1277

Table 6.4. Current consumption of the first PCB


Regulator Component Quantity Supply Current(mA)TPS78601 DAC 1 5(Analog, 5V) VGA 2 215

Sum 435TPS78633 ADC 2 300(Analog, 3.3V) Sum 600TPS78633 ADC 2 51(Digital, 3.3V) FPGA(I/O) 1 10

Crystal Osc. 1 100Clk buffer 1 140Flash 1 20FTDI 1 100Linear reg.(1A) 1 0.5Sum 473

TPS78625 AFPGA(Aux) 1 73(Digital, 2.5V) FPGA(I/O) 1 325

Sum 398MAX8869 FPGA(Core) 1 500(Digital, 1V) Sum 500Sum(tot.) 2406

Table 6.5. Current consumption of the second PCB

34 Analog Front-End

6.3 Theoretical CalculationsIn this section some theoretical calculations are done to show that the chosen com-ponents fulfill the SNR and the third-order intermodulation requirements, hencethese are the main requirements in this project.

6.3.1 SNRIn this section the two most crucial cases are studied, i.e. the sensitivity test andthe intermodulation/blocking test.

Calculating the overall SNR of the receiver in dBFS can be done as follows:

Vnoisetotal=

√VnoiseADC

2 + Vnoisein

2 (6.7)

SNRtot = 20 log(

VFSADC

Vnoisetotal

)+ Process Gain (6.8)

Vnoisetotal[21]is the total noise voltage of the system including the noise voltage

at the ADC input and the noise voltage contributed by the ADC itself. the noiseVFSADC in the equation above is the rms value of the full-scale (FS) signal of theADC, which is derived by using Equation 6.9. The noise in the ADC is independentof the input signal and will be the same value in both tests. The rms value of theADC’s noise voltage is calculated as shown below[6]:

VFSADC =Vp−pADC

2√

2=

22√

2=

1√2

V (6.9)

VnoiseADC

2 =(

VFSADC · 10−SNRADC

20

)2

=(

22√

2· 10

−72.220

)2

≈ 3.013 · 10−8V2

This value is used in the secitons below for calculating the overall noise in thereceiver in both test environments.

Intermodulation and Blocking

As mentioned in the requirements, the receiver must be able to operate despiteinterference with unwanted signals. In section 5.5 it was explained that the levelcaused by the interference can get as high as -11.5 dBm. This level limits themaximum allowed amplification in the receiver. The ADCs have a specified inputvoltage range which sets the limit of the maximum allowed signal level. If theamplified signal passes this limit the ADC will be saturated. The chosen ADC hasan input voltage range of 2V which gives a full-scale signal at 10 dBm. This gives amaximum allowed gain of 10− (−11.5) = 21.5 dB for this test. By using equation4.5 together with the given maximum gain and the given amplifier NFs, the rmsvalue of the total noise voltage at the ADCs input can be calculated. The total

6.3 Theoretical Calculations 35

NF of the system includes only the specified noise contribution of the amplifiers.Other, unspecified, noise sources are hard to estimate. The SNR calculations aredone as follows:

Nin,dBm = 10 log Nin =

= −174 + 10 log(190MHz) + 20 log(107.820 +

107.820 − 1

1021.520

) + 21.5 =

= −61.4898dBmVnoisein

2 = 10−61.4898/10 · 10-3 · 50 = 3.548 · 10−8V2

(6.10)

The calculations above give the total noise voltage for the system.

Vnoisetotal=

√3.013 · 10−8 + 3.548 · 10−8 ≈ 2.5614 · 10−4V

Now the overall full-scale SNR of the system can be calculated using Equation6.8:

SNRtot = 20 log(

0.70712.5614 · 10−4

)+ 10 log

(190MHz25kHz

)= 107.6282dBFS

This means that with the chosen components an SNR of 107.6 dBFS can beachieved theoretically, which is more than 6 dB greater than the required SNRof 101.5 dBFS in this test. Theoretically it would be possible to also fulfill thesensitivity requirement with the same amplification thus the required SNR wouldbe 107.5 dBFS. This would mean that the VGA is not needed. But in reality thiswill not be the case thus the noise contribution of the analog filters and other noisesources are not included in this calculation. The 0.1dB margin is not enough tofulfill the requirement when all noise sources are included.

Sensitivity

In this test there are no other signals present but a weak signal of -107 dBm, thusmaximum possible gain can be used. Theoretically, the full-scale SNR needs tobe 10dBm - (-107dBm + 44dB) + 12dB = 85dBFS. This is the ratio between theADC’s full-scale signal and the amplified test signal plus the 12dB required bythe decoder. Here follows the SNR calculations that are done similairly as thecalculations above:

36 Analog Front-End

Nin,dBm = −174 + 10 log(190MHz) + 20 log(107.820 +

107.820 − 110

2220

) + 44 =

= −39.0129dBmVnoisein

2 = 10−39.0129/10 · 10-3 · 50 = 6.2759 · 10−6V2

Vnoisetotal=

√3.013 · 10−8 + 6.2759 · 10−7 ≈ 0.0025V

SNRtot = 20 log(

0.70710.0025

)+ 10 log

(190MHz25kHz

)= 87.8003dBFS

Also in this test the SNR requirement is fulfilled. The achieved SNR of 87.8dBFS is more than 2dB higher than the required 85 dBFS. Theoretically thismargin is more than enough, but in reality the actual SNR could differ from thecalculated SNR due to non-included noise sources. SNR measurements are doneon both PCBs in Chapter 10.

6.3.2 IMD3

As mentioned in Section 4.3, third-order intermodulation distortion can causemajor problems in the receiver if they fall inband in the desired signal bandwidth.In this section som theoretical calculations are done to confirm that the chosencomponents, in the chosen configuration, fulfill the requirements that are set up toavoid this kind of problem. This is a theoretical measure of the so called two-tonetest that is commonly used for estimating the non-linearity of systems. The valueof parameters that are needed for this calculation are presented in Figure 6.5. Asit is shown, the first amplifier must be adjusted to 21.5 dB and the second to 0dB hence the maximum allowed gain in the IMD/blocking test is 21.5 dB, as wasmentioned earlier.

BPF2LNA AGC

Glna: 21.5 dBOIP3lna: 38 dBm

Gfilt: 0 dB Gagc: 0 dBOIP3agc: 38 dBm

Pin: -24 dBm Plna: -2.5 dBm Pagc: -2.5 dBm

Figure 6.5. The configuration for IMD measurements.

As it is shown in the figure, the test signal has a level of -24 dBm which is theaverage power of the two IMD tones of -27 dBm each. Together with the givenvalues, the calculations are done by using Equation 4.7:

6.4 PCB and EMC[13] 37

PIMLNA = 3 · Plna − 2 ·OIP3LNA = 3 · (−2.5)− 2 · 38 = −83.5dBmPIMAGC = 3 · Plna − 2 ·OIP3AGC = 3 · (−2.5)− 2 · 38 = −83.5dBm

Since the VGA is adjusted to 0 dB gain, the calculated IMD3 powers willremain the same at the input of the ADC. By using these results, a total IMD3power can be calculated:

PIMtot = 10 log(10−8.35 + 10−8.35) = −80.5dBmThe calculations result in a total IMD3 power of -80.5 dBm at the ADC input.

In the mentioned IMD/blocker test, the desired signal has a level of -101dBm,which after amplification of 21.5 dB is brought up to -79.5 dBm. This value isonly 1 dB higher than the level of the IMD3. This could cause problems if theIMD product falls inband. The decoding of the signal could be prevented hencethe decoder requires a 12 dB SNR/SFDR.

Despite the result of the calculations above, it is decided to use the chosencomponents anyway, hence finding amplifiers with higher OIP3 than 38 dBm withhigh gain is time consuming. With the tight time schedule of this work this couldnot be done.

6.4 PCB and EMC[13]In order to design a PCB there are many factors to keep in mind. In this worksome actions were taken to avoid performance degradation due to, for example,EMC problems. A short list covers some of these actions:

• The analog and the digital supplies are split up to avoid transfering the noisydigital supply into the analog region.

• The clock signal paths to the ADCs have the same length to minimize clockskew.

• The impedance in components are matched to avoid reflections in the signalpath.

• Many decoupling capacitors were used in order to prevent unwanted energytransfer between high frequency devices and the power distribution network.

The first PCB has four layers including two interconnected ground layers. Thesecond PCB has six layers to make it easier to route the FPGAs BGA-package(Ball Grid Array). Also this board has two interconnected ground layers.

Ground layers are important in order to keep the noise generated from groundat a minimum. They create a good path for returning currents and make itconvinient to route ground pins of devices anywhere on the board, using vias.

It would have been preferable to have two separate ground layers, using onefor the digital parts and the other for the analog parts. This is hard to achieve inreality hence this was not attempted in this project.

38 Analog Front-End

Chapter 7

Data Packets

To be able to measure the performance of the system, data packets are transmittedto the receiver. To be able to decode the packet, the packets’ appearance haveto be known. The packet and how they are processed before transmission will bedescribed in this chapter. The modulation of the test packet according to GMSKfollows the block schematic depicted in Figure 7.1.

DataCalc.CRC

Bitstuffing

AddPreamble

NRZIGaussianfilter

Modulatecarrier

Modulatedsignal

Figure 7.1. Block schematic for the modulation.

7.1 The PacketThe data is transmitted in a packet, which may contain different amount of data.The components that build up the packet and their lengths are shown in Table7.1 and in Figure 7.2. They will be described in the following sections.

The packet shown in figure 7.2 is transmitted from left to right.

StopbyteFCSDataStartbyteTraining-sequence

Figure 7.2. A packet’s different components.

39

40 Data Packets

Name No. of bitsTraining Sequence 24Start pattern 8Data 168-1008FCS 16Stop pattern 8

Table 7.1. Packet components and their sizes.

7.1.1 Training SequenceThe training sequence can be used by the receiver to synchronize itself to thetransmitter. It consists of a 24-bit long alternating 0 and 1 bit pattern. When thepacket is coded with NRZI encoding it changes its pattern as shown in Figure 7.3.The NRZI encoding is explained in Section 7.3.

Figure 7.3. The training sequence before and after NRZI encoding.

7.1.2 Start FlagThe start flag consists of a standard high level data link control (HDLC) start flag,which is an eight bit pattern, 01111110 (7Eh)[2]. The start flag is not bit stuffed(see Section 7.2) even though it consists of six consecutive ones.

7.1.3 DataThe data part of the packet is of variable length, but the default length of the testpackages are 168 bits. The data is bit stuffed together with the FCS before it isbroadcast, this is explained in Section 7.2.

7.2 Bit Stuffing 41

7.1.4 Frame Check Sequence

The frame check sequence (FCS) is created by a cyclic redundancy check (CRC).The CRC is preformed by a 16-bit polynomial that calculates a checksum as de-fined in ISO/IEC 3309:1993. The CRC bits are set to one at the beginning of acalculation. The FCS is only used to verify the correctness of the data portion ofthe packet, consequently the packet has no built in error correction.

End Flag

The end flag is identical to the start flag as described in Section 7.1.2 above.

7.2 Bit Stuffing

The start and the stop pattern has six consecutive ones, and since the receiverdoes not know how long the message will be it can only determine this by thestart and stop pattern. In order for the packet to only contain one stop patternthe message has to be bit stuffed to prevent the stop pattern to occur in the dataand FCS. This is done by inserting a zero after every group of five consecutiveones that occur, even if the sixth bit is not a one, this is illustrated in Figure 7.4.

Original message: 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 . . .Bit stuffed message: 1 0 0 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 . . .

Figure 7.4. An example bit stream which has been bit stuffed.

It is only the data and the FCS that are subject to the bit stuffing. After thebit stuffing the message is NRZI encoded.

7.3 NRZI

Before the message is broadcast the bit stream is encoded by the Non Return toZero Inverted (NRZI) algorithm[20]. NRZI encoding is done by starting with a 1and every time there is a 0 in the bit stream the resulting bit stream changes sign.An example can be seen in Figure 7.5.

1 0 0 1 0 1 0 0 1 11 1 -1 1 1 -1 -1 1 -1 -1 -1

Figure 7.5. An example bit stream encoded with NRZI

42 Data Packets

7.4 GMSKThe packet is then modulated with Gaussian Minimum Shift Keying (GMSK)[20]before it modulates the carrier wave. GMSK is a phase modulation method thathas continuous phase in order to lessen its bandwidth.

7.4.1 Gaussian filterThe signal is passed through a Gaussian low pass filter to eliminate the disconti-nuities in the NRZI endoded bit stream. The gaussian low pass filter is defined byEquations 7.1-7.3.

g(t) =1

2T

[Q

(2πBb

t− T/2√ln 2

)−Q

(2πBb

t + T/2√ln 2

)](7.1)

0 ≤ BbT ≤ ∞ (7.2)

Q(t) =∫t

1√2e(−x2/2)dx (7.3)

The filter is truncated and scaled to represent a π/2 phase change for a singlesymbol. This is done by choosing K to fulfill equation 7.4

T∫−T

Kg(t)dt =π

2(7.4)

Chapter 8

FPGA

This chapter will explain the digital signal processing executed by the FPGA.There are two different versions of the code which will be explained in the followingsections. Both attempts were run on the first hardware platform, but with slightalterations to fit the different FPGA:s used. Only the second attempt was run onthe second hardware platform.

The FPGA has a very important role in lessen the amount of data that needsto be processed by the PC. To do this the FPGA performs several tasks:

• Merge the signals from the two ADCs

• Filter and decimate the signal

• Produce I and Q signals

• Detect the angle between two consecutive symbols

• Transfer the data to a PC for decoding

• Control the VGA

Since the system has a very high sampling rate it is crucial that it is decimatedbefore transferring. The sampling is done at 380 Msps producing 14 bits at eachsample, that is a bit rate of about 5.3 Gbps. The data link to the PC on the otherhand can only handle a maximum bit-rate of 3 Mbps, which gives a decimationfactor of at least 1770. How this is done will be explained in the following sections,which starts with the first attempt and will be followed by the second attempt.

8.1 Hardware PrerequisitesThe two different hardware platforms use different FPGA:s as explained in Chapter6. The Xilinx FPGA:s Virtex 4 (v4) and Virtex 5 (v5) has somewhat differentarchitectures. Most of these design differences are handled by the synthesis tooland does not need any alterations of the code, but one major difference is theDSP-slices.

43

44 FPGA

8.1.1 DSP-slicesThe DSP-slice is a hardware accelerator that can do multiplications, additions andsubtractions at very high speed, up to 550 MHz[19]. They are very useful in theFIR filters used in this project. The high required speed in the first decimationfilters makes it difficult to create a multiplier with only logic, without using manysteps of pipelining. Therefore the DSP-slices have been used to accomplish thesehigh speed FIR filters, but they differ a bit between the v4 and the v5.

Xilinx Virtex 4

The v4 DSP-slice has a 18 x 18 bits multiplier with a 48 bit long accumulator,which can be seen in Figure 8.1. The first attempt therefore had 18 bits in thesignal path. The word lengths will be discussed in Section 8.4.2.

A

B

C

P

x

+

18 bits

18 bits

48 bits

48 bits

Truncatedoutput

DSP48

Figure 8.1. DSP48-slice in virtex 4.

Xilinx Virtex 5

The v5 has an improved DSP-slice called DSP48E. It has a 25 x 18 bits multiplierinstead and a 48 bit long accumulator, depicted in Figure 8.2. It can also runfaster than its predecessor, up to 550 MHz. This means that the quantizationerror will not become as big, since the signal can have 25 bits in the signal bus.

8.2 First AttemptThis is the first attempt in decoding the encoded message. The overall blockschematic can be seen below in figure 8.3. Each block will be described in detailin the following sections.

8.2.1 LinearizerThis block corrects the errors produced by the differences in the two ADCs. Itsfunction is described in chapter 2.

8.2 First Attempt 45

A

B

C

P

x

+

25 bits

18 bits

48 bits

48 bits

Truncatedoutput

DSP48E

Figure 8.2. DSP48E-slice in virtex 5.

Linearizer

h2

h2 h3

h3

h1

x

x

Phase-diff

FIFOSerial-interface

ADC 1

ADC 2

PC

cosDDS

sinDDS

Figure 8.3. System overview for the first attempt.

46 FPGA

8.2.2 First DecimationThis stage decimates the signal with a factor 8, from 380 MHz to 47.5 MHz. Theanti-aliasing filter is made by a 161 tap FIR filter, which is run on 22 parallelDSP-slices. Half of the DSP-slices work on one of the ADCs and the other half onthe other ADC.

The filter’s frequency response can be seen in Figure 8.4. It was difficult toachieve a good filter with narrow passband and high stop band attenuation dueto its high cost in hardware. This was one of the reasons causing the decision tomake a second attempt, which is explained in Section 8.3. The implemented filterhas a stop band attenuation of 41 dB and a passband of 3 MHz.

0 20 40 60 80 100 120 140 160 18050

45

40

35

30

25

20

15

10

5

0

MHz

dB

Figure 8.4. The frequency response for the first decimation filter.

8.2.3 I - Q ModulationTo be able to detect the I and Q the signal is multiplied by a sine and a cosinesignal of the same frequency as the carrier. By doing this the modulated signal ismoved down to DC, where it can be demodulated.

The multiplications are done by two DSP-slices that multiply the input with thesine value and the cosine value respectively. This is now implemented in parallel,but if there is a restriction on hardware it could be done on only one DSP-slice inseries instead, since a new output is only produced every other clock cycle.

The sine and cosine waves were implemented as two Direct Digital Synthesis(DDS) blocks[3]. These are built up by 512 values of the waveform that are storedin a memory that are stepped through by a phase accumulator. The 16-bit phaseaccumulator counts with a step length that corresponds to a wave with the wantedfrequency. Only the 9 most significant bits (msb) of the phase accumulator areused to access the right value in the memory. This way of producing a sine andcosine waveform is not perfect and therefore will add noise to the signal. Thissolution turned out to add too much noise which is shown in Equation 8.1. Inthe second attempt a more advanced DDS was used, which is explained in Section

8.2 First Attempt 47

8.3.2

SNR = 10 log(Ps

Pn) = 50.3dB (8.1)

8.2.4 Second DecimationThe second decimation filter decimates the signal with 15, from 47.5 MHz to 3.17MHz. The FIR filter has 60 taps and its impulse response can be seen in Figure8.5. It uses one DSP-slice for the I channel and one for the Q channel. The shiftregister for the FIR filter is implemented as a ring buffer in a RAM-block on theFPGA. The values are added to the buffer by one port as the other port reads thevalues to the DSP-slice.

0 10 20 30 40 50 600

0.005

0.01

0.015

0.02

0.025

0.03

0.035

Figure 8.5. Impulse response for the second decimation filter.

8.2.5 Third DecimationThe third decimation filter decimates the signal with 33, from 3.17 MHz to 96 kHz.The FIR filter has 496 taps and its impulse response can be seen in Figure 8.6. Italso uses a ring buffer to store the values while a ROM contains the coefficients.One DSP-slice on the FPGA is used to perform one multiplication on every clockcycle and then accumulating the result until all the taps have been calculated.This takes 496 clock cycles, but a new output is performed every 1980 clock cycle,so it is paused for almost 1500 clock cycles. If the control logic is altered it wouldbe possible to run the I and Q channel in series and thus save one DSP-slice, butthis was not necessary in this implementation.

48 FPGA

0 50 100 150 200 250 300 350 400 450 500−0.005

0

0.005

0.01

0.015

0.02

0.025

Figure 8.6. Impulse response for the third decimation filter.

8.2.6 Phase DifferentiatorTo be able to demodulate the signal one needs to find the angular differencebetween two following symbols. This was implemented by doing a cross productas described in Equation 8.2.

z1 × z2 =[

ab

]×

[cd

]= ad− bc = |z1| |z2| sin(arg(z1)− arg(z2)) (8.2)

By using this equation the sign of the angular difference can be found, theactual value is of less importance since it depends on the length of the vectors.The angle between two following symbols can be either −π/2 or +π/2, as explainedin Section 7.4. Thus by checking the sign of Equation 8.2, the signal becomes theoriginal NRZI encoded message because of the fact of Equations 8.3 and 8.4. Thisis the last step of the decoding done in the FPGA.

sin(π/2) = 1 (8.3)sin(−π/2) = −1 (8.4)

8.2.7 FIFOTo ensure that no data would be lost between transfers to the PC a fifo wasimplemented to collect the data. With this design the transfers could be madein bursts to the PC, and the decoding algorithm run on the PC can be made onbatches of data.

8.3 Second attempt 49

8.2.8 Data Transfer

A serial interface is used on the FPGA to be able to communicate with the PC,while the PC has a USB interface. To convert the serial interface to the USBinterface a chip from FTDI was used. The serial/USB link gives a theoreticallimit of 3 Mbits/s, but would probably be more like 1 Mbit/s in reality. Sincedecimation is used and only the sign of the angular difference is transfered thetransfer rate will be 96 kbits/s, which means that the PC will have enough timeto process the data between collecting batches of data.

8.2.9 DAC Controller

The second amplifier used in the analog receiver is a VGA, which amplificationlevel is controlled by an analog input. To adjust the level of amplification 7 dip-switches on the developmentbord is used to control a DAC, while the DAC controlsthe VGA. The signals from the dip-switches are routed via the FPGA to the DAC.

A problem is that the DAC also needs a write signal to take in a new value.This write signal is produced by the FPGA that continuosly sends out the writepulse.

The initial plan was to make a digital AGC, that would automatically adjustto the incoming signal level. It was decided not to do so since such a function wasnot needed for the tests.

8.3 Second attemptUpon completion of the first attempt there were a few points that called for asecond attempt. The most important reason was the decimation filters. The firstfilter in the first attempt was difficult to make with sharp transition bands andwith the attenuation in the stop band that was needed for a good sensitivity. Theblock schematic for the second attempt can be seen in Figure 8.7. One advantagethat can be seen instantly is that noise from the DDS blocks will be filtered further.Each block will be described one by one in the following sections.

8.3.1 Linearizer

This block is the same as described in Section 8.2.1.

8.3.2 IQ-modulation

The IQ-modulation block has the same functionality as in the first attempt, butsince the IQ-modulation block is the first block in the decoding chain it will haveto run at 380 MHz. Because the FPGA is clocked at 190 MHz the 2 multiplicationsare performed by 4 dsp-slices that work in parallel.

50 FPGA

ADC 1

ADC 2

Linearizer

x

x

x

DDSsin(2n+1)sin(2n)

DDS

cos(2n+1)cos(2n)

h1 h2-h8

h1 h2-h8

Phase-diff

x

FIFOSerial-inter-face

PC

Figure 8.7. System overview for the second attempt.

DDS

The DDS blocks in the first attempt generated to much noise and were improved inthis attempt. In the previous version the least significant bits (lsb) were discarded,but in this version they are used to enhance the output.

x = mem(address(msb)) (8.5)y = mem(address(msb) + 1) (8.6)

diff = y − x (8.7)corr = diff ∗ address(lsb) (8.8)sin = x + corr (8.9)

As described by Equations 8.5-8.9, the msb fetches the addressed value andthe next value from the ram, that contains only 256 values now. The lsb are thenmultiplied with the difference between the two fetched values and then added tothe first. This achieves a linear approximation between the two points on thewave, thus reduces the error and the noise generated by the DDS. The differencecan be seen in Figure 8.8.

The new DDS has a significant improvement in performance which affects thesystem as a whole. The SNR Equations 8.10 and 8.11 shows how much better thenew DDS is.

SNRDDS1 = 50.3dB (8.10)SNRDDS2 = 91.1dB (8.11)


1 1.2 1.4 1.6 1.8 2 2.2

x 104

2.7

2.8

2.9

3

3.1

3.2

x 104

Figure 8.8. The difference between the two DDS blocks.

8.3.3 Decimation

Now the signal is moved down to DC, which means that the decimation filters canall be lowpass filters. This is a great improvement since a good low pass filter chainrequires less hardware to design, than the band pass filter used in the first attempt.Another improvement is that the noise from the sine and cosine generator will befiltered through more filters.

The decimation factor was also changed in this attempt so that the resultingsignal will have a sampling frequency of 105.6 kHz instead of 96 kHz. The differentsteps to make the decimation from 380 MHz down to 105.6 kHz was divided intofactors of 2, 5, 5, 3, 3, 2, 2. This will give an output of 11 bits per symbol.

The frequency response for the whole decimation is shown in Figure 8.9, andin Figure 8.10 the passband is zoomed in.

First Decimation

The first decimation filter gets two inputs every clock cycle and decimates it by afactor two, which means it produces a new output every clock cycle. The 7 tapFIR filter is realized with two DSP-slices. Its impulse response can be seen inFigure 8.11.

Second Decimation

The second filter has 21 taps and is realized with 5 DSP-slices to be able to producean output every 5th clock cycle. Its impulse response is depicted in Figure 8.12.

52 FPGA

0 20 40 60 80 100 120 140 160 180800

700

600

500

400

300

200

100

0

MHz

dB

Figure 8.9. The frequency response for the complete decimation filter.

0 20 40 60 80 100140

120

100

80

60

40

20

0

kHz

dB

Figure 8.10. A zoomed in portion of the frequency response in Figure 8.9.


0 1 2 3 4 5 6 7 80. 1

0

0.1

0.2

0.3

0.4

0.5

0.6

Figure 8.11. Impulse response for the first decimation filter.

0 5 10 15 20

0

0.05

0.1

0.15

Figure 8.12. Impulse response for the filter h2

54 FPGA

Third Decimation

The impulse response of the third filter can be seen in Figure 8.13, which alsoshows that it has 25 taps. This stage decimates the signal with a factor of 5,which means that it gives a new output every 25th clock cycle. It consists of oneDSP-slice that accumulates the result, which is then truncated.

0 5 10 15 20 25

0

0.05

0.1

0.15

0.2

Figure 8.13. Impulse response for the filter h3.

Fourth Decimation

With 21 taps and one DSP-slice the fourth filter decimates the signal with a factorof 3. Its impulse response is seen in Figure 8.14.

0 5 10 15 200.05

0

0.05

0.1

0.15

0.2

0.25

0.3

Figure 8.14. Impulse response for the filter h4


Fifth Decimation

The fifth filter has 19 taps and decimates the signal with a factor 3. After thisstep the data speed is about 844 ksps.

0 5 10 15 200.05

0

0.05

0.1

0.15

0.2

0.25

0.3


Sixth Decimation

The sixth decimation filter has 19 taps and it decimates the signal with a factor2.

0 5 10 15 200.05

0

0.05

0.1

0.15

0.2

0.25

0.3


56 FPGA

Seventh Decimation

The seventh filter has 29 taps and decimates the signal with a factor 2.

0 5 10 15 20 25 300. 1

0

0.1

0.2

0.3

0.4

0.5


Eighth Decimation

This decimation filter is the last one and it decimates the signal with a factor 2.Since the speed is very low at this point, this filter has the most taps. It has 257taps, but it will only need one DSP-slice since the data speed after this step isonly 105.6 ksps, which gives the filter 1800 clockcycles to complete one output. Itis this filter that decides the channel bandwith, which is 25 kHz.

0 50 100 150 200 250

0.05

0

0.05

0.1

0.15

0.2

0.25


8.4 Calculations 57

8.3.4 Phase DifferentiatorThe phase differentiator is almost identical to the one described in Section 8.2.6,except the alteration for coping with 11 bits per symbol which is a result of thechanged decimation factors.

8.3.5 FIFOThis function is still the same as in Section 8.2.7.

8.3.6 Serial InterfaceThe serial interface also has the same functionality as the previous version de-scribed in Section 8.2.8.

8.3.7 DAC ControllerThe DAC controller is almost identidak to the one described in section 8.2.9, exceptthat the second board only has 5 available dip-switches. Because of this two zeroswere added to the end to produce a seven bit wide controll signal. The write signalis still produced as a repeated pulse.

8.4 Calculations8.4.1 ScalingWhen using two’s complement representation it is very important not to get over-flow in the calculations. The FIR filters are sensitive blocks where overflow caneasily occur if they are not scaled properly. There are several ways of scaling afilter. The L2-norm[9] (see equation 8.12) was used in this case.

||X ||2 =

√√√√√ 12π

π∫−π

|X(ejωT )|2dωT =

√√√√ ∞∑n=−∞

|x(n)|2 (8.12)

When scaling a multistage decimator the following algorithm can be used[12]:

1. F1(z)← H1(z)

2. c1 ← 1||F1||2

3. F2(z)← F1(z)H2(zM1)

4. for i← 2 to 8

5. Calculate ||Fi||2

6. ci ←∏ i−1

j=1(1/ci)

||Fi||2

58 FPGA

7. if i = 8

8. then

9. stop

10. else

11. M ′i ←

∏i +1j=1Mj

12. Fi+1(z)← Fi(z)Hi+1(zM ′i )

Table 8.1 shows the result from the algorithm above. The third column showsthe chosen scaling factor, which was used in the algorithm on row 5 instead of thecalculated ci. For the first filter safe scaling was used instead, since it has few tapsand therefore could overflow more easily. As can be seen in the table there shouldbe no overflow problems in the decimation filters.

Filter L2-norm Scale Chosen Scaleh1 1.56 0.5h2 9.02 2h3 8.33 1h4 13.78 1h5 23.37 1h6 31.90 1h7 44.15 1h8 85.59 1

Table 8.1. L2-norm scaling of the decimation filters.

8.4.2 Word LengthIt is important that the signal keeps or improves its SNR through out the process-ing in the FPGA, hence the importance of the word lengths in the system. TheDSP-slices contains a large accumulator but smaller input ports to the multipliers,which implies that the results from each filter must be truncated. When a resultis truncated quantization noise is added. How the SNR of the quantization noisecan be calculated can be seen in Equation 8.13 - 8.16[9].

y(n) = 2N−1Q sin(ωnT ) (8.13)

Ps =(2N−1Q)2

2= 22N−3Q2 (8.14)

Ps

Pn=

22N−3Q2

Q2

12

=3222N (8.15)

SNR = 10 log(

Ps

Pn

)= 6.02N + 1.76 (8.16)

8.4 Calculations 59

The system should not add any more noise than the ADC has already con-tributed, so that the ADC is the limiting component. To achieve this the numberof bits needs to be calculated, which is done in Equations 8.17 - 8.18.

SNRtot = SNRADC + 10 log(

fs/2BWch

)= 72.2 + 38.8 = 111.0 (8.17)

SNR = 6.02N + 1.76SNRtot = 111.0

⇒ N =

111.0− 1.766.02

= 18.15 bits (8.18)

The Equations 8.17 - 8.18 assumes that the quantization noise from the filterdepends only on the last truncation. In order to do a more thorough examinationthe following algorithm for quantization noise in multistage decimation filters canbe used[12]:

1. G8(z)← 1

2. σ28 ← σ2

8

3. for i← 7 downto 1

4. Gi(z)← Gi−1(zMi)ciHi(z)

5. σ2i ← σ2

i ||Gi||226. σ2

tot =∑8

i=1 σ2i

ci is the scaling factor, which was treated in section 8.4.1.

This algorithm is applied on the decimation filter in the second attempt. Theresult, with the scaling used in Section 8.4.1 and with different word lengths, canbe seen in Table 8.2.

No. of bits SNR (dB)16 95.5317 101.5518 107.5719 113.5920 119.6221 125.6422 131.6623 137.6824 143.7025 149.72

Table 8.2. SNR for different word lengths.

60 FPGA

According to the result in Table 8.2 the v4 with only 18 bits in the signal pathadds more noise during the decimation filtering than the ADC, but it is still belowthe required SNR mentioned in Section 6.3.1. Thus the v5 version is better, sinceit adds significantly less noise than the rest of the system and can be neglected.

Chapter 9

PC

To be able to measure the performance of the prototype, some signal processing isneeded. All processing was made on the PC at first and then one block at a timewas moved to the FPGA, though all blocks were not moved. The tasks that areperformed by the PC at the final version of the decoding are:

• Communicate with FPGA

• Symbol Synchronizing

• NRZI-decoding

• Decode Packets

• Verify the Data

9.1 CommunicationThe PC communicates via USB with the FPGA. As mentioned earlier in Section8.2.8 it uses a chip from FTDI to convert the serial interface to the USB. A programwas written in C to collect the data on the USB port and pass it on to Matlab forfurther processing.

9.2 MatlabMatlab was used to do the remaining demodulation and decoding of the packets.This made it possible to take advantage of Matlab’s good mathematical functions.Some statistical tests were also performed, which can be found in chapter 10.

9.2.1 Symbol SyncronizationWhen a batch of data is received it is first put through a correlation filter. Thedata stream consists of ten or eleven samples per symbol depending on FPGA

61

62 PC

version, which leads to the problem of finding the symbol boundary. By observingthe result from the correlation filter it is possible to find out if there is a messageand where the correct symbol boundaries are. This is possible since the preambleof the message is known, which was explained in Chapter 7. The correlation filter,depicted in Figure 9.1, has the same form as a perfect packet preamble would havefrom right to left, but the coefficents are weighted after how close to the boundrarythey are.

0 50 100 150 200 250 300 350

1

0. 8

0. 6

0. 4

0. 2

0

0.2

0.4

0.6

0.8

1

Figure 9.1. The impulse response for the correlation filter.

When the bit stream corresponds to the preamble the correlation is high, butwhen there is only noise the correlation is low. This is depicted in Figure 9.2 whichis a plot from the correlation filter. It is easy to see when there is a message inthe bit stream. Figure 9.3 displays a zoomed in part of the peak in Figure 9.2.

The maximum value of the peak indicates the beginning of a message. Whenthe starting point is found the message can be conceived. This was implementedin two ways. The first implemented version was to choose only the center sample,and in the second version the surrounding samples were taken into considerationby different weight. The output from this stage is either one or negative one.

9.2.2 Decode NRZI

The message has to be decoded before the data is extracted since the messagewas encoded with NRZI before transmission. The NRZI encoding is explainedin Section 7.3. The decoding is done by checking the sign of the bits in the bitstream. If there is a change in sign the output is a zero otherwise a one. Anexample is shown in Figure 9.4. The sign of the bit stream is of no importance,since it will result in the same output. This is a necessity since the sign dependson what phase the sine and cosine waves in the IQ-demodulation had when thepacket was received.

9.2 Matlab 63

0 1 2 3 4 5 6

x 104

0

50

100

150

200

250

300

350Correlation

Figure 9.2. An example output from the correlation filter.

1.071 1.0715 1.072 1.0725 1.073 1.0735 1.074 1.0745 1.075 1.0755 1.076

x 105

0

50

100

150

200

250

300

Correlation

Sample

Figure 9.3. Zoomed in on the detected message.

64 PC

Bit stream 1 -1 -1 1 -1 -1 1 1 -1 1 1 1Bit stream 2 1 1 -1 1 1 -1 -1 1 -1 -1 -1Output 1 0 0 1 0 1 0 0 1 1

Figure 9.4. An example bit stream decoded from NRZI.

9.2.3 Extraction of the DataNow the message consists of zeros and ones and the data can be extracted fromthe package. By finding the start flag and the stop flag the data is extracted. Thiswas done with the find(bitstream==pattern) function in Matlab, which returnsthe indexes of the positions where the patterns were found.

Now that the data has been extracted it is possible to see what the datacontains and compare it with the same as the transmitted data.

Chapter 10

Tests and Results

In this chapter the test environments will be described and the test results will bepresented. Some tests had to be somewhat modified due to the lab material, e.g.there were only two signal generators available. It will be explained how the testwas performed in each section.

10.1 Filter BandwidthsThe expected filter bandwidths were presented in Chapter 6, but are they thesame in reality? A frequency sweep was made on both boards to establish thefrequency characteristics of the bandpass filters in the front-end.

10.1.1 Board 1As can be seen in Figure 10.1, the passband center frequency is shifted to theleft compared to the simulations. This could depend on property variations inthe passive components. This is difficult to affect other than using better qualitycomponents or testing their value before mounting. The filter components werereplaced after the board was delivered, since some components had inaccuratevalues.

The filter passband of the first filter is 137-157 MHz, which is not what wasstrived for. 162 MHz, which is the frequency of the test signal, is attenuated withabout 5 dB, which is more than aimed for. The filter has a good attenuation offrequencies in the FM-band, e.g. it attenuates 100 MHz with 28 dB. This is goodsince FM-transmitters usually have high output power.

10.1.2 Board 2The frequency response for the front-end on board 2 is worse than for board1, which can be seen in Figure 10.2. This could depend on the fact that thecomponents on board 1 was replaced with the right components. Some componentvalues on the second board could be wrong, but they have not been examined as

65

66 Tests and Results

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 108

120

100

80

60

40

20

0

Hz

dB

Figure 10.1. Frequency response for board 1.

the filter functioned properly in the lab. Much better filters would have to bedesigned for use in the real world. The passband of the filter is 112-147 MHz,while 162 MHz is attenuated with 9 dB. If the components were replaced it couldbe expected to have about the same characteristics as for board 1.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 108

100

90

80

70

60

50

40

30

20

10

0

Hz

dB

Figure 10.2. Frequency response for board 2.

10.2 External LNAAs it turned out during the time in the lab, non of the boards passed the sensitivitytest, although the theoretical calculations in Section 6.3 showed that they should.It was decided to use an external ultra-low-noise amplifier to see if the problemlies within the LNA used on the boards.

Table 10.1 shows some characteristics of this external amplifier. As it is shownin the table, the noise figure of this amplifer is very low which suits the purposeof these tests perfectly.

10.3 SNR 67

The test results with and without the external LNA are presented later in thischapter.

Gain 17 dBNF < 1.2 dB

OIP3 >37 dBm1dB Compression point > 20 dBm

Table 10.1. Properties for the external LNA.

10.3 SNRThe SNR for the system is very important, since a good decoder needs the modu-lated signal to have a 12 dB SNR for correct decoding. In this section some testsare done to measure the SNR performance of the front-end alone by studyingthe sampled data directly after the ADC. The setup for these tests is depicted inFigure 10.3.

Signal-generator-70 dBm

ExternalLNA

SDR-prototype

Matlab

Signal-generator-70 dBm

SDR-prototype

Matlab

Figure 10.3. Setup for SNR test, without and with external LNA.

10.3.1 Variable Gain - Fixed Signal LevelAs explained in Chapter 6, the SNR depends on the gain of the amplifiers. Sometests were run to confirm that the best SNR was achieved while having maximumreceiver gain. This test was done by varying the gain of the VGA while receivingan unmodulated sine wave at a constant level.

The SNR was calculated using Matlab by cutting out the points in the fastfourier transform (FFT) that corresponded to the signal’s frequency, in order toget the signal power. The noise power was calculated in a similar way, by takingmany surrounding points of the signal in the FFT and calculate the average to getan approximation of the noise power in the channel.

Tables 10.2 and 10.3 show the test results of both boards with and withoutthe external LNA. The SNR is given for a -70 dBm input signal at a frequencyof 162 MHz with a channel width of 25 kHz. The same input signal is used on


both boards. The second column presents the results using the external LNA,mentioned in Section 10.2.

Without the external LNA the performance of the first board turned out tobe slightly better than for the second. The difference was bigger than expected.This could depend on the fact that the second board contains more components,e.g. FPGA which emits a lot of noise into the ground plane. The differences inthe analog filters could also be a part of the reson, but the attenuation differencewas only 4 dB and thus does not explain the whole difference.

Gain (dB) SNR (dB) SNR LNA (dB)0 38.8 46.96 40.8 49.112 41.9 51.018 42.1 51.322 42.8 51.6

Table 10.2. SNR for a -70dBm signal without and with external LNA on board 1.

As it is shown in the tables, the SNR value for both systems are relativelyequal when using the external LNA. This result was expected since the signal isamplified with the same low noise amplifier stage before it enters the differentboards. The difference in added noise of the two boards becomes less noticeablewhen the external LNA is used because of the changed noise figure, see Equation4.5.

Gain (dB) SNR (dB) SNR LNA (dB)0 27.5 46.76 30.5 49.712 31.7 50.618 32.5 51.122 32.4 51.0

Table 10.3. SNR for a -70dBm signal without and with external LNA on board 2.

10.3.2 Fixed Gain - Variable Signal LevelAn SNR test with the gain fixed at a maximum was also conducted. The inputsignal level was adjusted to see at what level the input signal had a lower SNRthan that of 12 dB required by the decoder. The result of this test is shown inTable 10.4 for board 1 and Table 10.5 for board 2. The test is also done with andwithout the external LNA. In both cases the results turned out to be as expected.Using the LNA, the test results are similar. Without it, the first board has betterSNR performance. This depends on the same reason as in the previous test, thatit is the slightly more noisy signal path on the second board caused by the FPGA.

10.4 Sensitivity Test 69

Gain (dB) SNR (dB) SNR LNA (dB)-70 42.8 51.3-75 37.9 46.9-80 31.9 41.3-85 27.6 36.2-90 23.2 31.4-95 17.6 25.8-100 13.0 20.8-105 9.2 16.7-110 6.3 12.3-115 4.7 8.8

Table 10.4. SNR for various signal levels without and with external LNA on board 1.

The results in Table 10.4, show that it should be possible to decode a -100 dBmwithout th external LNA, and -110 dBm with. This agrees well with the result inthe sensitivity tests in the following section.

Signal power SNR (dB) SNR LNA (dB)-70 32.06 51.0-75 26.82 46.1-80 21.61 41.2-85 16.86 36.0-90 12.93 31.1-95 9.34 25.6-100 6.97 20.7-105 6.89 16.7-110 5.74 12.7-115 5.65 9.7

Table 10.5. SNR for various signal levels without and with external LNA on board 2.

The result for the second board in Table 10.5 also agrees with the sensitivitytests. With the external LNA a -110 dBm signal should be possible to decode,and without a -90 dBm signal.

10.4 Sensitivity TestThe sensitivity test is performed to find the lowest signal power at which thesystem is able to correctly decode a message. The requirement says that it mustbe able to decode at least 80% of the packts correct, or with 20% packet error rate(PER). The packets described in Chapter 7 with 168 data bits were used to testthe system. The signal generator was modulated by a sound file that was played


by a computer. The Matlab program then fetched 100 batches of data that eachcontained at least one packet. The packet was decoded and verified against theknown data that had been sent. After 100 messages the result was printed out onthe screen.

The PER values in the following sections are not statistically verified, since itis based on only 100 packets. Only 100 packets were used because of the testswere time consuming. The small amount of data can make it seem like the valuesare unstable. It is still possible to see were the PER value passes 20%, since thebreaking point is very sharp.

10.4.1 Board 1The setup for the sensitivity test of board 1 is shown in Figure 10.4. The testwas performed with a coaxial cable connecting the signal generator and the board,thus the noise added there is negligible.

Clock-generator

Signal-generator

SDR-receiver PC

Figure 10.4. The setup for the sensitivity test for board 1.

When testing the sensitivity for board 1 only the second code version will beused. This is because only this version can be run on both boards and thus beused for comparison and evaluation. The test gave the results in Table 10.6.

Level PER (%)-85 8-88 5-90 2-92 5-94 8-95 15-96 22

Table 10.6. Sensitivity test using PCB 1.

The system seemed to generate a lot of noise. As depicted in Figure 10.5, theexternal LNA, that has a much better noise figure, was attached before the boardand improved the results significantly. Table 10.7 shows the results from this test.

10.4 Sensitivity Test 71

Clock-generator

Signal-generator

SDR-receiver PCExternalLNA

Figure 10.5. The setup for the sensitivity test for board 1 with LNA.

Level PER (%)-95 3-97 5-99 6-101 2-103 3-105 8-107 3-109 3-110 12-111 21-112 41

Table 10.7. Sensitivity test using PCB 1 with external LNA.


10.4.2 Board 2The sensitivity test for the second card was performed in the same way as for thefirst board, except for the fact that the second board has an on board clock. Thesetup for this test can be seen in Figure 10.6.

Signal-generator

SDR-receiver PC

Figure 10.6. The setup for the sensitivity test for board 2.

The test results were not as good as expected by the theoretical calculations.

Level PER (%)-85 1-90 7-91 9-92 12-93 34

Table 10.8. Sensitivity test using PCB 2.

Also for the second board the results became a lot better when the externalLNA was used, which can be seen in Table 10.9.

Signal-generator


Figure 10.7. The setup for the sensitivity test for board 2 with LNA.

10.5 Blocking TestThe blocking test is performed to see how the system handles a strong signal on adifferent frequency than the wanted signal. This test is a good for measuring thesystems dynamic range. It is an important parameter for an SDR receiver, sincethere will almost always be a strong signal somewhere within the frequency bandof interest.

In this work the blocker will determine the maximum gain the system can have,which means that the wanted signal will not be fully amplified. The setup for thetest is shown in Figure 10.8. The blocker signal power should be -15 dBm andshould have a frequency of 5 MHz above or below the wanted signal.

10.5 Blocking Test 73

Level PER (%)-107 1-109 5-111 17-112 27-113 60

Table 10.9. Sensitivity test using PCB 2 with external LNA.

Signal-generator


Blocker-generator

Figure 10.8. The setup for the blocking test.

The amplification of the LNA on the board has to be adjusted since the externalLNA is used in front of the board. This was done by applying a variable voltageto the LNA. The gain was adjusted to make the combined signal full swing on theinput of the ADCs.

The critical component in this case will be the ADC, because if the wantedsignal is detectable after the ADCs it could be filtered out. For this the gain mustbe enough for the wanted signal to have sufficient SNR, as discussed in Section6.3.1.

To perform this test we needed a second signal source. The only signal genera-tor that was available turned out not to have good enough parameters to performthe test. The SFDR was too low and the noise it generated was higher than thewanted signal, which made it impossible to detect. The test that was performedwith the blocker switched on showed that the modulated signal had to have apower of -72 dBm to be correctly decoded.

A modified test was performed instead to make an estimation of the blockercase. The system’s amplification level was determined in order to make the blockersignal have full swing. Then the blocker was turned off and the test with themodulated signal was carried out.

The modified test suggests that it should be possible to decode signals with apower as low as -97 dBm as long as the blocking signal does not add more noisethan the system itself adds. The result could probably be improved if a betterdecoder was used. The requirement was -101 dBm, so the result is 4 dB below.


10.6 Intermodulation TestThe intermodulation test checks the linearity of the analog part of the receiver.The requirement for the intermodulation is a part of the blocking requirement, butdue to lack of equipment these tests had to be split up in two. There were onlytwo signal generators available for the tests, thus the test is performed to measurethe power of the IMD3 product.

1.6 1.605 1.61 1.615 1.62 1.625

x 108

90

80

70

60

50

40

30

20

10

0

MHz

dBFS

Figure 10.9. Plot from the IMD3 test on board 2.

The test was performed by applying two -27 dBm signals to board 2. This wasonly run on the second board since they have the same components. The signalswere 500 kHz apart, thus the IMD3 product appeared 500 kHz on either side ofthe signals. This can be seen at 160.5 and 162 MHz in Figure 10.9. The dashedline is the plot with a 2 dB gain on the VGA, and the solid line is with 1 dBattenuation on the VGA.

Gain (dB) IMD3 (dBFS)-1 -702 -676 -629 -59

Table 10.10. IMD test performed on board 2.

The result was difficult to interpret, due to the noise generated by the signalgenerators. According to the Equation 10.1 the IMD3 product should increasewith the increase in gain. It can be seen in Table 10.10 that this was also the casein our tests.

10.7 Adjacent Channel Selectivity 75

I3 = 3Po − 2OIP3 = 3(Pi + G)− 2(IIP3 + G) = 3Pi − 2IIP3 + G (10.1)

IMRR = I3 − Po = −67 (10.2)

The resulting IMD3 product gives an intermodulation rejection ratio of 67 dBcfor the system, calculated with Equation 10.2. This result is not good enoughsince a value of least 86 dBc is needed for the signal to have a 12 dB margin.

10.7 Adjacent Channel SelectivityThe digital filter implemented in the first version of the FPGA code attenuatesthe adjacent channel with 77 dB, which might not be enough. According to therequirement the receiver should handle an adjacent signal 70 dB stronger than thesignal. The decoder might be able to still decode the messages, but some extrasafety margin would be good.

The second version of the filter attenuates the adjacent channel with 100 dB.That will be more than enough to fullfill the requirements set for the adjacentchannel selectivity.

It is really the ADCs SNR that will be the limiting factor for this requirement,since it is possible to alter the digital filters so that an even higher attenuation isachieved.

10.8 Power ConsumptionThe second PCB turned out to become very hot during the tests. The reasonfor this was that the total power consumption on the board was relatively high.As can be seen in Equation 10.3, the PCB produces a significant amount of heat.The used current value for the second PCB are calculated in Section 6.2.8. Theheat problem was solved by using a fan during the tests, which was enough to cooldown the board. If designing a new PCB this fact should be taken into account.

Ptot = VinItot = 5 ∗ 2.4 = 12W (10.3)

Chapter 11

Conclusions and FutureWork

This chapter will finish the report with the conclusions on the work and some ideasfor future work.

11.1 ConclusionsThis thesis work has shown that it is possible to create a direct sampling SDRreceiver for the VHF-band. The requirements that were set up are difficult toachieve in an ordinary receiver design, but it becomes an even bigger challenge withan SDR design without sharp analog filters and down-conversion of the frequency.It has been shown that it should be possible to meet all the requirements, eventhough they were not fully met within this work.

11.1.1 Test ResultsThe main test results of the project are presented in Table 11.1. The blocker resultis just a performance estimate, which is explained in Section 10.5.

Requirement Required MesuredSNRsensitivity without LNA 85 dBFS 75 dBFSSNRsensitivity with LNA 68 dBFS 91 dBFSSNRblocker without LNA 101.5 dBFS 85 dBFSSNRblocker with LNA 107.5 dBFS 105 dBFSSensitivity test -107 dBm -111 dBmBlocker test -101 dBm -98 dBmThird-Order Intermodulation 86 dBc 67 dBc

Table 11.1. Results from the tests

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78 Conclusions and Future Work

11.1.2 HardwareThe second version of the PCB proved to have problems with heat. It was knownthat the components used on the PCB generated a lot of heat, but it turned outto be a bigger problem than predicted. If a cooling fan was applied to the FPGAthe heat was manageable, but without the fan the PCB was overheated after a fewminutes. The number of components, especially the FPGA, on the second boardincreased the amount of noise in the signal path compared to the noise on the firstboard. This caused a slight deterioration of the SNR on the second board.

The chosen LNA turned out to be the wrong choise for this application. Al-though the theoretical calculations showed the opposite, non of the boards man-aged to pass the sensitivity test. Considering this result, an external LNA, withvery low NF and good properties on linearity, was used to confirm that the prob-lem of the sensitivity lies within the LNA. This turned out to be right hence asensitivity of -111 dBm was achieved which is 3 dB under the required value.

The analog filters on both boards turned out to have different center frequenciesthan what was expected after simulations in Protel. This caused attenuation ofthe desired test signal on 162 MHz. This could depend on property variations inthe discrete components. By replacing the components with others which value ismeasured, this problem could be solved.

Theoretically, also the blocker test should be passed but this was not the caseduring testing hence the actual SNR was lower than the calculated value. A majorreason is that the signal generators that were used for these tests are too noisy.By using more accurate signal generators, this test could very well be passed.

11.1.3 FPGAThe choice of FPGA for the second version of the PCB, turned out to generate toomuch heat. Its full capacity was not needed in this project and therefore anotherFPGA could have been a better choice, but for future use the PCB has a lot ofpotential which is good for a prototype.

The second version of the FPGA code turned out to be much beter than thefirst code.

• Better filters

• Improved sine generator

• Wider word lengths (only v5)

The decimation filters had better characteristics in the second version. Thiswas due to the fact that the IQ-modulation was the first block, thus only lowpassfilters were used. It also required less hardware to implement.

The second version of the DDS generated a sine wave with a much better SNRfor a small increase of used logic. There are still optimazation that could be madeto improve it further but it fulfills the requirments.

The Virtex 5 makes it possible to have longer word lengths, which gives lessquantization noise.

11.2 Future Work 79

11.2 Future WorkThe electronics market is in constant change. This SDR solution is on the limit ofwhat is possible, but in the near future this will be a commonly used design. Thiswork could be used as a base for further development of a true SDR receiver.

The GMSK decoder in this work is very simple. It would be interesting tofurther enhance the decoder with a more advanced algorithm to see how thatcould improve the performance of the system. Another improvement would beto integrate it on the FPGA, so that the packets would be fully decoded whentransfered. That way a display could be attached and the data could be presenteddirectly on the display.

The SDR function could be used further by listening to several channels inparallel. An FM-demodulator could be implemented to listen to FM broadcasts.

80 Conclusions and Future Work

References

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[3] Analog Devices. A technical tutorial on digital signal synthesis.http://www.ieee.li/pdf/essay_dds.pdf.

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[5] R. Gharpurey. Design considerations in wireless receiver front-ends.http://engr.smu.edu/orgs/ssc/slides/20010130.pdf.

[6] W. Kester. Adc noise figure - an often misunderstood and misinterpretedspecification. www.analog.com/en/content/0,2886,760_1077_91253,00.html.

[7] W. Kester. Intermodulation distortion considerations for adcs.www.analog.com/en/content/0,2886,760_788_91329,00.html.

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[11] P. Löwenborg. Mixed-signal Processing. Linköping Univerity, 2 edition, 2006.

[12] H. Johansson M. Olsson, P. Löwenborg. Scaling and roundoff noise in multi-stage interpolators and decimators.

[13] M. Montrose. EMC and the PCB. IEEE, 1998. ISBN 0-7803-4703-X.

[14] PTS. Post- och telestyrelsens almänna råd om den svenska frekvensplanen.www.pts.se/Archive/Documents/SE/frekvensplanen2005_4.PDF.

[15] S. Ramos S. Lucas. Comparison of modern radio receiver architechtures.Master’s thesis, Linköping University, Sweden, 2005.

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82 References

[16] S. Söderkvist. Kretsteori & Elektronik. 3 edition, 1999.

[17] A. Svärdström. Modulation och teleteknik. Studentlitteratur, 1 edition, 1996.ISBN 0-13-348624-9.

[18] et al T. Padamanabhan. Design Through Verilog HDL. IEEE, 1 edition, 2004.ISBN 0-471-44148-1.

[19] Xilinx. Xilinx homepage. http://www.xilinx.com.

[20] F. Xiong. Digital Modulation Techniques. Artech House, 1 edition, 2000.ISBN 0-89006-970-0.

[21] P. Young. Electronic Communication Techniques. Prentice Hall Inc., 3 edi-tion, 1994. ISBN 0-13-348624-9.

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Design and Implementation of an SDR Receiver for the VHF Band Thesis

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