Design, Analysis, Fabrication, and Measurement of a

Wilkinson Power Divider

Matthew Watson, Department of Electrical & Computer Engineering, University of Arizona,

Tucson, AZ 85721

Abstract—A five-port Wilkinson power divider was first designed using known design

equations to achieve a desired power ratio between output ports. This power divider was

then modeled using Agilent Advanced Design System for ideal transmission lines, first by

modeling the individual three-port dividers and then by modeling the entire five-port

system. A three-port divider was then modeled and analyzed using microstrip simulations.

A layout for this microstrip power divider was then generated and the power divider was

fabricated on an RT Duroid 5870 substrate. This power divider was then subjected to tests

and the measurements were compared to simulated results.

Completed as part of course requirements for ECE 486 at the University of Arizona.

I. INTRODUCTION

The purpose of this paper is to present the process of analysis, simulation, and measurement for a

corporate feed unequal Wilkinson power divider, while exploring the agreements and

discrepancies between these three design approaches. The ideal power divider is shown in figure

1.

Fig. 1. Schematic concept of 5-port corporate feed unequal power divider. The numbers indicate relative power

distributions, with all of the input power applied to the bottom port and output power coming out of the top 4 ports.

The divider was first designed on paper using equations given in [1] and was then modeled using

Agilent's Advanced Design System (ADS) software. The S parameters determined by this

simulation using ideal transmission lines were then compared to expected results. Once

agreement between this simulation and the analysis was confirmed, the power divider was then

modeled in ADS using its built-in microstrip simulation capability. Practical modifications to

the basic power divider were added to allow the microstrip power divider to be fabricated and

used on a pre-existing test fixture. Finally, a vector network analyzer (VNA) was used to

measure the S-parameters of the fabricated device. The measured results were finally compared

to the simulated and analytical results.

II. ANALYTICAL DESIGN OF THE 5-PORT POWER DIVIDER

One can observe that the desired power division scheme in figure 1 can be viewed as an equal

Wilkinson power divider (power divider A) feeding two equivalent unequal Wilkinson power

dividers (power dividers B). First, an analytical design of the equal power divider will be

presented, followed by an analytical design of the unequal power divider. Section 7.3 in [1]

contains a discussion of both unequal and equal Wilkinson power divider design and this

discussion forms the basis for the analysis in this section.

A. Design of Power Divider A

The design of power divider A will be presented first. A microstrip schematic of an equal

Wilkinson power divider can be viewed in figure 2 (taken from section 7.3 in [1]). It can be seen

that if one knows Z0 at the input and outputs of the power divider as well as the operating

frequency, one could easily calculate all of the parameters of the power divider.

Fig. 2. Microstrip schematic of an equal Wilkinson power divider

The center frequency for the circuit was given to be 2.5GHz and all of the input ports and output

ports were to be matched to 50Ω, so the impedance of the quarter-wavelength sections were

determined to have an impedance of and a length of 1.965cm on RT Duroid

5870 (calculated using equation 1).

(1)

In addition to this, the resistor could also be determined to be 100Ω, based on the expression in

figure 2.

B. Design of Power Divider B

The design of power divider B will now be presented. Figure 3 (taken from section 7.3 in [1])

shows a schematic of an unequal Wilkinson power divider, and the following equations (also

from section 7.3 in [1]) are used to determine the parameters of the power divider.

(2)

(3)

(4)

(5)

Fig. 3. Schematic of an unequal power divider, with port 1 as the input and ports 2 and 3 as the outputs. Although it

is not indicated on this schematic, the branches must have length λ/4.

Since the output of power divider A has an impedance of 50Ω, we know that Z0 for power

divider B is also 50Ω. Z02, Z03, and R may be determined by equations 4, 3, and 5, respectively.

The value of K must be computed first, however, using equation 2. In equation 2, the values P3

and P2 refer to the relative power split between ports 3 and 2, respectively. The desired power

split is given in figure 1 as 0.3 and 0.2, so the value of K may be calculated to be approximately

1.2247. Now that the value of K has been obtained, the value of Z03 may be calculated to be

58.327Ω. Z02 is now calculated using equation 4 as 87.49Ω. Finally, R may be calculated using

equation 5 to be 102.06Ω.

The reader may also note that the output impedance at ports 2 and 3 is no longer equal to 50Ω,

but rather Z0K = 61.235Ω at port 2 and Z0/K = 40.826Ω at port 3. Since the outputs of the power

divider must be matched to 50Ω, a quarter-wavelength transformer will be used to transform the

impedance. A quarter-wavelength transformer's impedance may be calculated using equation 6

with ZL = 50Ω and Zin equal to the output impedance of the port obtain Ztrans2 = 55.334Ω at port 2

and Ztrans3 = 45.18Ω at port 3.

(6)

C. Complete Uneven Corporate Feed Power Divider

A schematic of the complete power divider can be viewed in figure 4 and a table of the

associated values can be viewed in figure 5. The reader should note that all angled (non-

horizontal) sections of line in the schematic as well as the sections labeled Ztrans2 and Ztrans3 have

length λ/4 = 1.965cm. In addition to this, the reader should note that all ports have an impedance

of 50Ω.

Fig. 4. Schematic of the ideal complete corporate feed uneven Wilkinson power divider

Fig. 5. Table of values associated with figure 4

III. SIMULATION OF WILKINSON POWER DIVIDER USING ADS

Agilent Advanced Design System (ADS) was used to simulate the individual power dividers

separately as well as the complete corporate feed power divider to make sure that their S-

parameters matched what was expected based on the analytical design. After this was complete,

the B power divider was simulated using the ADS microstrip simulation capability. These steps

will be outlined in this section.

A. Simulation of Power Divider A Using Ideal Transmission Lines

Power divider A (the equal power divider) was modeled in ADS using ideal transmission lines,

and an S-Parameter sweep was performed to determine the value of all S-parameters for the 3-

port circuit at various frequencies between 1GHz and 4GHz. A screenshot of the ADS model for

power divider A may be viewed in figure 6. Note that port 1 refers to the input port on the left,

port 2 refers to the upper right output, and port 3 refers to the lower right output. The S

parameters may be viewed in the following figure 7. The reader may see from these plots that

the simulation shows the ports being well-matched to the 50Ω terminations with return loss equal

to -100dB at 2.5GHz. Additionally, good isolation between ports 2 and 3 was achieved due to

S23=S32= -105dB at 2.5GHz. Finally, the reader may notice that the insertion loss is -3.02dB at

both ports 2 and 3, which when converted to the equivalent power ratio using equation 7 gives

0.7063 (a voltage ratio). Squaring to obtain the power ratio we obtain 0.499, which is very close

to the desired power split of .5 on each port.

(7)

The reader may also notice that while optimum performance is obtained at 2.5GHz, and may on

first impression appear to sharply drop off as the frequency moves from the center frequency,

good performance is also obtained over a wider band when one considers the scale of the plots in

figure 7.

Symbol Impedance (Ω)

Z0 50

Z02 87.49

Z03 58.327

Ztrans2 55.334

Ztrans3 45.18

Fig. 6. ADS schematic of power divider A. The termination numbers indicate the port number.

Fig. 7. ADS sweep of S-parameters between 1GHz and 4GHz for the ideal power divider A (y axis in dB)

B. Simulation of Power Divider B Using Ideal Transmission Lines

Power divider B (the unequal power divider) was modeled in ADS using ideal transmission

lines, and an S-Parameter sweep was performed to determine the value of all S-parameters for

the 3-port circuit at various frequencies between 1GHz and 4GHz. A screenshot of the ADS

model for power divider B may be viewed in figure 8. The reader should observe that the

resistor value in the schematic is 100Ω, rather than the 102.06Ω that was calculated for the power

divider. This is due to the fact that fabrication is made easier and more practical by only having

to stock one value of resistor in addition to the fact that 100Ω resistors are a much more common

value. This makes little difference in the S-parameters, which the reader can determine through

observation of figures 9 and 10.

From figures 9 and 10, we see that the return loss is below -40dB at all ports for both

simulations, indicating a good match to the 50Ω port impedances in either case. The reader

should also notice that the insertion loss at port 2 is -3.98dB and at port 3 is -2.22dB in both the

ideal and non-ideal simulations, which when converted from dB yields a voltage ratio of .6324 at

port 2 and .7745 at port 3. Converting to power ratios by squaring, we obtain .3999 at port 2 and

.5999 at port 3. This is almost exactly the desired ratio of .4 at port 2 and .6 at port 3, which

indicates that the desired power division performance was achieved even with a small change to

the resistance.

Fig. 8. ADS schematic of power divider B. The termination numbers indicate the port number.

Fig. 9. ADS sweep of S-parameters between 1GHz and 4GHz for the ideal power divider B (y axis in dB)

Fig. 10. ADS sweep of S-parameters between 1GHz and 4GHz for the ideal power divider B, but with resistance

changed to 100Ω (y axis in dB)

C. Simulation of Complete Corporate Feed 5-Port Power Divider Using Ideal Transmission

Lines

The complete corporate feed power divider shown in figure 4 was then modeled in ADS by

combining power divider A with two copies of divider B so that an S-parameter sweep could be

performed to verify the performance of the overall system. A screenshot of the ADS schematic

may be viewed in figure 11 below. The ports for the simulation are numbered in the same way

as they are in figure 4.

A frequency sweep was again performed to determine the value of all S-parameters between

1GHz and 4GHz, and the results of that sweep may be viewed in figures 12 and 13.

The reader may observe from figure 12 that the maximum return loss at 2.5GHz is about -45dB,

and the maximum return loss over the spectrum is about -15dB, indicating acceptable matching

performance. One additional detail to note is that the high matching quality at port 1 is relatively

narrowband compared to the matching at the output ports.

For the insertion loss, the desired power division at the output ports was 0.2 at ports 2 and 5 and

0.3 at ports 3 and 4 (refer to figure 1). The results of the simulation shown in figure 13 show that

the insertion loss at ports 2 and 5 at 2.5GHz is about -6.99dB and at ports 3 and 4 is -5.23dB.

These correspond to a power ratio of .19999 at ports 2 and 5 and .29992 at ports 3 and 4, which

are incredibly close to the desired ratios. Additionally, considering the scale of the graphs in

figure 13, this performance remains fairly constant over a wide band.

Fig. 11. ADS schematic of corporate feed power divider. The termination numbers indicate the port number.

Fig. 12. Return loss at all ports of the corporate feed power divider

Fig. 13. Insertion loss at all ports of the corporate feed power divider

D. Simulation of B Power Divider Using Microstrip

The ultimate goal of the project was to fabricate and measure the B power divider using

microstrip on RT Duroid 5870, so the next step was to model power divider B in ADS using its

built-in microstrip simulation capability. A screenshot of the ADS schematic can be viewed in

figure 14.

Fig. 14. ADS schematic of the microstrip layout seen in figure 15

One can see that this schematic is considerably more complex than the ideal transmission line

schematic for power divider B. This is due to a variety of factors. This includes the fact that the

microstrip realization must include a T-shape section to split the line into two portions, curves to

route the line in the correct direction, and steps in line width to allow the impedance of the line to

be changed. Additional transmission line length and curves also had to be added so the layout

seen in figure 16 would fit properly on the measurement fixture seen in figure 17.

All of these additions considerably affected the performance of the power divider in terms of its

center frequency as well as off the center frequency. The table in figure 15 shows the width and

length that were determined using the ADS LineCalc functionality. The final column, L Actual,

shows the lengths that were qualitatively determined to provide the best performance after using

the ADS tuning functionality to account for the changes caused by the additional features added

to the ideal simulation.

Section Impedance (Ω) W (mils) L Calculated (mils) L Actual (mils)

Port 1 connection 50 87.7 Port 2 divider 87.49 32.469213 839.6 696

Port 3 divider 58.327 68.744 839.6 630

Port 2 transformer 55.334 74.86 839.6 1159

Port 3 transformer 45.18 102.076 839.6 651 Fig. 15. Calculated and actual dimensions of various microstrip sections for the B power divider

Fig. 16. Microstrip layout of the B power divider

Fig. 17. Layout of measurement fixture showing location of measurement ports. All dimensions in mils.

It should be observed that L Actual differs quite a bit from L Calculated, which can be attributed

to the fact that the waves behave differently in the microstrip curves, tees, and steps that were

added to the design.

The S-parameters of the final design after all tuning was complete can be seen in the next two

figures. Figure 18 shows the return loss at each port, and the reader should notice that while

matching performance is good around the center frequency of 2.5 GHz, matching performance is

fairly poor especially towards the upper end of the test spectrum.

Fig. 18. Return loss at all ports for the microstrip B power divider between 1GHz and 4GHz

The return loss at 2.5GHz is between about -25dB and -30dB, depending on the port, for this

simulation. Compared to the ideal B power divider simulation (figure 10), where the return loss

is between -100dB and -45dB, depending on the port, this performance has been degraded but is

still acceptable, corresponding to return power losses of less than 1% at any given port. The

performance over the entire spectrum is more comparable to the ideal divider simulation

however, with worst case return losses around -10dB to -15dB in both instances.

The insertion loss at each port and the output port isolation vs. frequency is shown in figure 19.

At 2.5 GHz, it can be observed that the insertion loss at port 2 is -4.05dB and at port 3 is -2.35

dB. This corresponds to a power ratio of .394 at port 2 and .582 at port 3, which is not far off of

the desired ratios of .4 and .6, respectively. This performance remains acceptable towards the

lower end of the spectrum, but experiences a more drastic falloff towards the higher end of the

spectrum. The output port isolation is about -30dB at 2.5GHz, which is fairly good performance.

Where the output port isolation suffers, however, is over the wider band. The output isolation

experiences relatively narrowband performance, as it approaches -10dB at both 1GHz and 4GHz.

Fig. 19. Insertion loss and output port isolation for B power divider microstrip simulation

Compared to the ideal simulation of the B power divider, the insertion loss is only slightly worse

on the microstrip version, with power ratios of .394 and .582 as compared to ratios of .3999 and

.5999 for the ideal line. The output isolation is very comparable on both the microstrip and ideal

power dividers, with maximum isolation on the ideal version being at -45dB as compared to -38

dB on the microstrip version and minimum isolation at about -10dB for both versions. One note

to be made is that the maximum isolation for the microstrip version had to be placed slightly

below 2.5GHz while tuning to allow for better performance of other parameters.

IV. FABRICATION AND MEASUREMENT OF MICROSTRIP POWER DIVIDER B

The layout in figure 16 was used to create a photomask that could be applied to a substrate made

of RT Duroid 5870 in order to fabricate power divider B. A picture of the finished power

divider, with a dime for scale, can be seen in figure 20.

Fig. 20. Photograph of the fabricated Wilkinson power divider B

The power divider was then clamped onto the test fixture and 50Ω connectors were soldered onto

each port of the power divider. After this all was complete, each possible combination of ports

was connected to a vector network analyzer (VNA) to perform an S-parameter sweep. The

results of this measurement are presented in figures 21, 22, and 23.

The reader should notice from figure 21 that the return loss center frequency appears to be

shifted to about 2.7GHz, but the return loss at each port at that shifted center frequency is at

between -25dB and -37dB, which is right in line with what was predicted by the simulation. If

we consider the intended center frequency, 2.5GHz, the maximum return loss is about -18dB,

which corresponds to a power loss of about 1.5% due to reflections at the port.

Fig. 21. Measured return loss at each port of the fabricated microstrip power divider B

Observing figure 22, the measured insertion loss at ports 2 and 3 was about -4.25dB and -2.65

dB, respectively. This corresponds to a power ratio of .376 at port 2 and .543 at port 3, as

compared to a simulated power ratio of .394 and .582, and a desired ideal power ratio of .4 and

.6. This comparative loss in power from what was simulated is likely due to a combination of

imperfections during fabrication as well as poor solder connections (too much solder used which

radiates power away).

Fig. 22. Measured insertion loss at each output port of the fabricated microstrip power divider B

Figure 23 shows that the output port isolation center frequency also appeared to be shifted to

about 2.7GHz where it is about -21dB. This decrease in output port isolation as compared to the

simulated value of -30dB is likely due to the fact that the output ports were placed very close

together where they could electromagnetically interfere with each other. A wiser placement of

the output ports would have likely been able to improve the output port isolation.

Fig. 23. Measured output port isolation of the fabricated microstrip power divider B

The shift in center frequency that was observed across all measured S-parameters to about

2.7GHz rather than the designed frequency of 2.5GHz was probably due to placement of the

resistor. In simulation, the resistor is attached at an infinitesimally small portion of the

microstrip at the beginning of the quarter-wavelength transformer. Because the resistor spanned

a considerable portion of the microstrip due to its width along with the fact that the resistor may

not have been placed exactly at the start of the quarter-wavelength transformers, the center

frequency would have been shifted.

V. CONCLUSIONS

The 5-port unequal corporate feed Wilkinson power divider was first derived analytically,

simulated using ADS, and finally fabricated and measured using a VNA. The ADS simulation

using ideal transmission line elements provided results that were almost exactly as expected

based on the analytical results.

Once microstrip elements were used for the simulation, however, the results were no longer a

perfect match to the analytical expectations. This was due to the introduction of a variety of

circuit elements, such as a microstrip tee, microstrip bends, and additional sections of microstrip

line to make the circuit fit into the physical constraints of the measurement setup. At this point

the tuning capability of ADS was used to modify the lengths of the quarter-wavelength

transformers and the quarter-wavelength power divider sections to provide adequate S-

parameters for the system.

This microstrip layout was then fabricated onto RT Duroid 5870 and the S-parameters were

measured using a VNA. The results from this measurement differed slightly from those

predicted by the simulation— most notably the center frequency was shifted from 2.5GHz to

about 2.7GHz, more power was lost at the ports than expected, and the isolation between the two

output ports was worse than expected.

These differences could have been due to a variety of factors, such as imperfections during the

fabrication process, placement of the resistor, solder connection quality, measurement

connection quality, and the fact that the two branches of the power divider ended up being very

close to each other near the output. Among these, the three that were likely most detrimental to

the performance are the imperfect placement and finite extent of the resistor, excess solder being

used at most of the soldered connections that would have radiated electromagnetic energy away,

and the two branches of the divider being very close to each other near the output.

On a future iteration, these problems could be amended by the creation of a microstrip pad for

the resistor that extends away from the main power divider lines to allow the resistance to be

applied exactly where intended, careful solder technique to create more efficient solder joints,

and a careful layout of the divider branches to allow them to branch away rather than towards

each other as they move towards the output.

REFERENCES

[1] Pozar, David M. "7.3 The Wilkinson Power Divider." Microwave Engineering. 4th ed.

Hoboken, NJ: J. Wiley, 2012. 328-32. Print.