DE1 FPGA board andDE1 FPGA board andQuartusQuartus

CPU ArchitectureCPU Architecture

ObjectivesObjectives

The FPGA boardThe FPGA boardUsing QuartusUsing Quartus CodingCoding CompilingCompiling SimulatingSimulating Pin AssignmentPin Assignment Configuring the boardConfiguring the board DebuggingDebugging PLLs and TemplatesPLLs and Templates

Altera DE1 FPGA BoardAltera DE1 FPGA Board

Cyclone II EP2C20F484C6 FPGACyclone II EP2C20F484C6 FPGA512KB SRAM , 8MB SDRAM ,4MB Flash512KB SRAM , 8MB SDRAM ,4MB Flash50MHz,27MHz and 24MHz oscillators for clock sources50MHz,27MHz and 24MHz oscillators for clock sourcesSD Card socket SD Card socket 4 pushbutton switches 4 pushbutton switches 10 toggle switches 10 toggle switches 10 red and 8 Green LEDs 10 red and 8 Green LEDs 24-bit audio CODEC 24-bit audio CODEC VGA DACVGA DACRS-232 interface RS-232 interface PS/2 mouse/keyboard Interface PS/2 mouse/keyboard Interface Two 40-pin Expansion HeadersTwo 40-pin Expansion Headers

DE1 board descriptionDE1 board description

Quartus IIQuartus II

Synthesis tool Synthesis tool

Place and RoutePlace and Route

SimulatorSimulator

DebuggerDebugger

ProgrammerProgrammer

And much moreAnd much more

Example applicationExample application

32bit behavioral counter with enable32bit behavioral counter with enable

8 MSB connected to green LEDs 8 MSB connected to green LEDs

Enable connected to switch Enable connected to switch

Clock to 50MHz onboard oscillatorClock to 50MHz onboard oscillator

Example CodeExample Codelibrary ieee;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_1164.all;use IEEE.std_logic_unsigned.all; use IEEE.std_logic_unsigned.all; entityentity counter counter is portis port ( (

clk,enable : clk,enable : in std_logicin std_logic;;q : q : out std_logic_vectorout std_logic_vector (7 (7 downtodownto 0)); 0));

end entityend entity;;

architecturearchitecture rtl rtl ofof counter counter isissignalsignal q_int : q_int : std_logic_vectorstd_logic_vector (31 (31 downtodownto 0); 0);

beginbeginprocessprocess (clk) (clk)beginbegin

ifif ( (rising_edgerising_edge(clk)) (clk)) thenthenifif enable = '1' enable = '1' thenthen

q_int <= q_int + 1;q_int <= q_int + 1;end ifend if;;

end ifend if;;end processend process;;q <= q_int(31 q <= q_int(31 downtodownto 24); 24); -- Output only 8MSB-- Output only 8MSB

endend rtl; rtl;

Project Files descriptionProject Files description

.qpf.qpf Project file Project file

.qsf.qsf Settings file (timing , constrains , pin) Settings file (timing , constrains , pin)

.vhd.vhd Design file , must be at least a top Design file , must be at least a top level design file , its ports are directly level design file , its ports are directly connected to physical pinsconnected to physical pins

.stp.stp Signal Tap file Signal Tap file

.vwf.vwf Simulation Waveform file Simulation Waveform file

.sof.sof FPGA programming file FPGA programming file

What is a Top LevelWhat is a Top Level

Serves as a top level hierarchyServes as a top level hierarchy

Connects to FPGA physical pinsConnects to FPGA physical pins

All the I/Os are routed through itAll the I/Os are routed through it

Top Level

Entity 1Entity 2

Entity 3

FPGA

FPGA Pins

Starting New ProjectStarting New Project

Open Quartus II (7.2)Open Quartus II (7.2)

Start Wizard Start Wizard File->New Project WizardFile->New Project Wizard

Click Next , Specify Name of Project and the Click Next , Specify Name of Project and the directory and click Nextdirectory and click Next

Specify files you want to add and click NextSpecify files you want to add and click Next

Specify FPGA and click Next , Next and Specify FPGA and click Next , Next and FinishFinish Cyclone II , EP2C20F484C6Cyclone II , EP2C20F484C6

Turn off Incremental CompilationTurn off Incremental Compilation

Assignments->Settings->Compilation Process Assignments->Settings->Compilation Process Settings -> Incremental Compilation Settings -> Incremental Compilation

Operating VHDL FilesOperating VHDL Files

Create new files Create new files File->NewFile->New

Add existing files and set compilation order Add existing files and set compilation order Assignments ->Settings->FilesAssignments ->Settings->Files

Changing Top level entity Changing Top level entity Assignments->General ->Top-level entityAssignments->General ->Top-level entity

Analyze the project : Push ButtonAnalyze the project : Push Button

View resource utilization at “View resource utilization at “Compilation ReportCompilation Report””

Viewing Synthesis resultsViewing Synthesis results

RTL SynthesisRTL Synthesis Tools -> Netlist Viewers -> RTL viewerTools -> Netlist Viewers -> RTL viewer

Technology SynthesisTechnology Synthesis Tools -> Netlist Viewers -> Technology map viewerTools -> Netlist Viewers -> Technology map viewer

A[31..0]

B[31..0]OUT[31..0]

ADDER

D QPRE

ENA

CLR

clk

enable

q[7..0]

Add0

32' h00000001 --

cnt[31..0]

Setting SimulationSetting SimulationAdd Vector file Add Vector file File->NewFile->New

Add signals Add signals Edit->Insert->Insert node or busEdit->Insert->Insert node or bus

Press the Press the ““Node FinderNode Finder”” and select signals and select signals

Change Simulation Time Change Simulation Time Edit->End Time,Edit->End Time, EditEdit-->Grid Size>Grid Size

Setting waveformsSetting waveformsUse the buttons on the left side to Use the buttons on the left side to generate input signalsgenerate input signals

Running simulationRunning simulationSave the Waveform file and go toSave the Waveform file and go to : : Assignments-> Settings->Simulator settingsAssignments-> Settings->Simulator settingsSet simulation mode toSet simulation mode to FunctionalFunctional and choose your file and choose your file asas simulation inputsimulation input

Ctrl+Shift+KCtrl+Shift+K – – Starts the simulationStarts the simulationLook on The simulation reportLook on The simulation report

Setting clock constrainsSetting clock constrainsOpen Settings : Open Settings : Assignments -> Settings->Timing Assignments -> Settings->Timing Analyzer Settings -> Classic timing analyzer settingsAnalyzer Settings -> Classic timing analyzer settings

Press “Press “Individual clocksIndividual clocks” button ” button

Setting clock constrainsSetting clock constrains

Click NewClick New

At the end press OKAt the end press OK

Specify Some Name

Select Input

Set Frequency

Manual Pin AssignmentsManual Pin AssignmentsOpen Pin Planner (Open Pin Planner (Assignments -> PinsAssignments -> Pins))

Specify Pin Numbers according to DE1 Data book with PIN_ prefix

Automatic CSV pin AssignmentAutomatic CSV pin Assignment

Uses CSV file from manufacturerUses CSV file from manufacturer

Top level names must be according to CSV fileTop level names must be according to CSV file

Open : Open : Assignments -> Import AssignmentsAssignments -> Import Assignments

Select CSV File

Press OK

Full compilationFull compilationPress ButtonPress Button

After compilation open timing analyzer in After compilation open timing analyzer in compilation report and see that all timings are OK.compilation report and see that all timings are OK.

Programming the FPGAProgramming the FPGA

Connect the DE1 board to powerConnect the DE1 board to power

Connect DE1 board to PC using USB cableConnect DE1 board to PC using USB cable

Power on the board using RED buttonPower on the board using RED button

Push the programmer button in QuartusPush the programmer button in Quartus

Programming the FPGA - contProgramming the FPGA - contPush Push Hardware SetupHardware Setup and and Select USB-BlasterSelect USB-Blaster

Push the Push the Auto DetectAuto Detect button button

Then double click the Then double click the <none><none> and select and select sofsof

Check the “Check the “Program configureProgram configure” box” box

Push Push StartStart button button

SignalTAP logic analyzerSignalTAP logic analyzer

A SignalTAP logic analyzer is used for A SignalTAP logic analyzer is used for debugging of FPGA logic.debugging of FPGA logic.

Do not require huge and expensive Do not require huge and expensive equipmentequipment

No massive external connections neededNo massive external connections needed

Captures internal FPGA signals Captures internal FPGA signals using a using a defined clock signaldefined clock signal

Uses FPGA resources Uses FPGA resources

Logic Analyzer - How it worksLogic Analyzer - How it works

Like a Pipe with water with faucet (trigger)Like a Pipe with water with faucet (trigger)Water are getting in all the time (data)Water are getting in all the time (data)

When trigger occurs faucet closes (capture stops), When trigger occurs faucet closes (capture stops), and you can see what is in the pipeand you can see what is in the pipeTrigger OptionsTrigger Options Pre TriggerPre Trigger Center TriggerCenter Trigger Post TriggerPost Trigger

TIME

Old Samples New Samples

triggerSamples CapturedSamples Captured

Signal TAP - How it WorksSignal TAP - How it Works

Signal Tap “Wastes” FPGA LogicSignal Tap “Wastes” FPGA Logic

User Signals

Trigger LogicMemory

FPGA

Signal Tap Logic

JTAG Interface

Quartus II

USB

Activating STP in Web EdditionActivating STP in Web Eddition

Go to : Go to : Options -> Internet Connectivity -> Options -> Internet Connectivity -> TalkBack OptionsTalkBack Options

Signal TAP UsageSignal TAP Usage

Create .STP FileCreate .STP File Assign Sample ClockAssign Sample Clock Specify Sample DepthSpecify Sample Depth Assign Signals to STP FileAssign Signals to STP File Specify TriggeringSpecify Triggering Setup JTAGSetup JTAG

Save .STP File & Compile with DesignSave .STP File & Compile with DesignProgram DeviceProgram DeviceAcquire DataAcquire Data

Create new STP FileCreate new STP File

Method 1Method 1 Select the in Quartus IISelect the in Quartus II

Method 2Method 2 Select New (File Menu) Select New (File Menu) Other Files Other Files SignalTap II FileSignalTap II File

STP ComponnentsSTP Componnents

Signal Configuration

JTAG Chain Configuration

Waveform Viewer

Instance Manager

STP Setup STP Setup Select USB-BlasterSelect USB-Blaster In JTAG ConfigurationIn JTAG Configuration

Set Sample ClockSet Sample Clock Use Global ClockUse Global Clock Every Sample taken at Clock Rising EdgeEvery Sample taken at Clock Rising Edge Cannot Be Monitored as DataCannot Be Monitored as Data

Specify Sample DepthSpecify Sample DepthSet Trigger modeSet Trigger mode

SequentialSequential Specify Trigger PositionSpecify Trigger Position

Pre , Center , PostPre , Center , Post Select Number of trigger conditionsSelect Number of trigger conditions

Adding SignalsAdding Signals

Select “Setup” tab and add signals (double click)Select “Setup” tab and add signals (double click)

Setting TriggersSetting Triggers

Right-Click to Set Value

All signals must satisfy trigger condition to cause All signals must satisfy trigger condition to cause data capturedata capture

STP CompilationSTP CompilationSave The STP fileSave The STP file

Open Assignments Open Assignments Settings Settings Specify the STP File to Compile with ProjectSpecify the STP File to Compile with Project

Run Full Project Compilation and reprogram Run Full Project Compilation and reprogram FPGAFPGA

Acquiring DataAcquiring Data

Signal Tap II Toolbar & STP File ControlsSignal Tap II Toolbar & STP File Controls

RunRun AutorunAutorun StopStop

TemplatesTemplates

While in VHD file push button on the leftWhile in VHD file push button on the leftIn a template window select the needed logic In a template window select the needed logic templatetemplate

PLLPLLOpen MegaWisard Open MegaWisard Tools->MegaWisard Plug in manager Tools->MegaWisard Plug in manager

and click and click NextNext

Select VHDL

Set NameOpen I/O

Select ALTPLL

Click Next

PracticePractice

Build a 8 bit circular Shift Register with Build a 8 bit circular Shift Register with enableenable

Make all the Quartus process as with Make all the Quartus process as with countercounter

Working At HomeWorking At Home

You can download a Quartus Web edition You can download a Quartus Web edition version from version from 

https://www.altera.com/support/software/downloadhttps://www.altera.com/support/software/download/sof-download_center.html/sof-download_center.html

ReferencesReferences

Quartus user manualQuartus user manual

DE1 board data sheetDE1 board data sheet

Altera web site.Altera web site.

Cyclone II Data sheetCyclone II Data sheet

Any questions?