Data Readout for AGATA using Future Electronics (STARE)Hardware and Firmware

IFIC/MILANO/CSNSM/IPHC Collaboration

AGATA18-09-2019

X. Lafay, N. Karkour, D. Linget and G. Vinther-Jørgensen

The STARE Concept

• Decoupling the custom hardware from the server farm

• Input through FMC• 4 Transceivers • 20 LVDS Pairs

• Ethernet output• 4 SFP+ links• UDP Transport

• IPBus slow control

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 2

Current firmware functionality

Recent firmware developments• Status in February 2019

• The parts where there (IPBus and 10 Gbps Network Stack)

• Conflicts between the IPBus and the Network Stack• Unnecessary features• Obsolete hardware

• Progress• Removed TCP implementation from the Network Stack

• External memory• Ported the Network Stack from Virtex 7 to Kintex Ultrascale• Merged the IPBus and Network Stack projects• Tested protocols for data input• Managed to transfer custom data from the Kintex Ultrascale to server via Ethernet

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 3

Current Firmware Status• Working prototype on KCU105 with VC709 as data

generator.• Based on code provided by David Sidler

(ETH Zurich) and IPBus firmware from CERN• Event splicing/reconstruction• UDP transmission• Package loss• IPBus implemented• Successfully tested with pre-processing

prototype from University of Valencia• Simple server application checking data integrity

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 4

Next Steps• Ensuring data reaches the

server• Overlaying protocol is

needed to guarantee delivery

• Needs external memory on the KCU105 board

• Improving usability• Using the features of

IPBus• Documentation

• Testing• Improved server side

program• More complex network

structure

https://www.geeksforgeeks.org/sliding-window-protocol-set-3-selective-repeat/

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 5

• What has been done:

• Bought a VC709 Xilinx evaluation board to qualify the initial code.

• Interface the evaluation board with the CSNSM 10 Gbps network data flow and validate the UDP for AGATA DAQ.

• Bought a KCU105 Xilinx evaluation board to simulate the pre-processing module.

• The firmware was initially tested with the VC709 evaluation board.

• During Firmware development issues and hardware constraints were discovered on the VC709 FPGA (old FPGA technology, less development library tools, less clock distribution facilities, no SOM modules in the market etc...).

• Since the KCU105 uses a recent KU040 FPGA (more flexibility in clock management, more development tools options, more high speed TX/RX, SOM modules are available etc…)

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 6

STARE HARDWARE

• What was done (cont.):

• A decision was taken to port the code from the VC709 to the KCU105.• Done (see Gustav Presentation).• The KCU105 became the STARE and the VC709 the pre-processing module simulator.• As decided by the FEE WG, the future AGATA electronics will be based on the SOM

technology plus dedicated carrier boards.• STARE will be composed of a KU040 SOM module plus an FMC based dedicated carrier

board.

• What was needed: MANPOWER : – 2018, 3 months engineering student Melissa: integration of the IPBUS interface on the VC709

and partial integration of the network stack code with IPBUS.– Feb 2019, 9 months student from Denmark (Gustav): (see his presentation)– June 2019, 3 months intern student (Nicolas): design, schematics and requirement documents.

Component selection and tests for the STARE carrier board (validation of the Mux, DC-DC converter, Pinouts definition between SOM and the carrier). 3 Weeks Proof of Concept participation

– starting September 2019: 3 years half time engineer student specialized in embedded electronics.

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 7

STARE HARDWARE

• Network Band Width : 10 Gbps = 640 M words of 16 bits. • Full FPGA online Monitoring (Chipscope on Ethernet)• It is important to have spy eyes on all the data processing from Preamplifier to

Data Flow

• But but but.• After the first tests with the firmware 10 Gbps was not possible to achieve

completely.– Any other activity on the server causes package loss.

• To achieve continuous and comfortable 10 Gbps with monitoring and online analysis, multiple 10 Gbps Tx/Rx is needed.

• New STARE architecture is under design.

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 8

AGATA readout Requirements

Readout interface control bus

10 GbpsData Readoutinterface

Stare Data Readout FPGA

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 9

STARE Initial Block Diagram

UDP External Memory Histogram and Scope External Memory (option)

10 Gb Transceiver

1 Gb Transceiver

Readout data

Slow Control Interface

Readout interface control bus

10 GbpsData Readoutinterface

Stare Data Readout FPGA

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 10

UDP External Memory Histogram and Scope External Memory (option)

10 Gb Transceiver

1 Gb Transceiver

Readout data

Slow Control Interface

STARE Initial Block Diagram

• Input data rate from pre-processing : 4 x 10 Gbps (2 for data 1 for monitoring 1 spare).• 2 Power supply sources (Internal and external PSU using hot swap mux) • Spare LVDS I/O with the pre-processing for future use• Full clock management inside the SOM and the FMC carrier.• Network Bandwidth up to 4 x 10 Gbps in parallel. • 1 Gbps IPBus for slow control.• Some on board facilities to make local comparisons with the DAQ (raw data storage,

local Histograms etc...) .• With this configuration it is absolutely easy to achieve continuous and comfortable 10

Gbps with monitoring and online analysis using multiple 10 Gbps Tx/Rx.• Only the Hardware side is presented. Nothing on the software side yet (on-going

discussion with computer team).

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 11

STARE Characteristics

4 x 10 Gbps Tx/Rx Stare Data Readout FPGA

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 12

STARE New Block Diagram

UDP External Memory

Histogram and Scope External Memory (option)

10 Gb Transceiver

1 Gb phy

1 Gb Transceiver

Readout data

IPBUS Slow Control Interface

4 x 10 Gbps Tx/Rx

Monitoringdata

Futur usedata flow

SOM MODULE

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 13

12V POWER SUPPLY

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NICOLAS TESSIER

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SOM LSHM CONNECTORS

NICOLAS TESSIER 4/9

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STARE Carrier Board Schematics ongoing

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STARE Carrier Board Schematics ongoing

FMC HPC CONNECTOR5/9

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I9

I8

I7

I6

I5 I3

I2

I1

FMC_HPC_CONNCON_FMC_HPC_SBGA10X40_FCON_FMC_HPC_SBGA10X40_F

FMC_HPC_CONNFMC_HPC_CONNCON_FMC_HPC_SBGA10X40_F

FMC_HPC_CONNCON_FMC_HPC_SBGA10X40_F

FMC_HPC_CONNCON_FMC_HPC_SBGA10X40_F

FMC_HPC_CONNCON_FMC_HPC_SBGA10X40_F

FMC_HPC_CONN

4.7KS32MW1%

I4 FMC_HPC_CONNCON_FMC_HPC_SBGA10X40_FCON_FMC_HPC_SBGA10X40_F

I12I17

FMC_HPC_CONN

S32MW1%4.7K

S32MW1%4.7KI22

I23

I10

J3 J3 J3

J3 J3

J3

J3 J3 J3

J3

RESET_BTN

LVDS17_N

LVDS15_P

LVDS17_P

LVDS05_P

FMC_CHECK

3V3_FMC

FPGA_TDO_FMC_TDI_BUFFMC_TCK_BUF

FMC_TDO_SW3P3VAUX_FMCFMC_TMS_BUFTRST_LGA13V3_FMC

3V3_FMC

LVDS13_P

GA012V_FMC

LVDS09_NLVDS10_N

LVDS03_PLVDS03_N

LVDS07_PLVDS07_N

LVDS11_PLVDS11_N

LVDS19_P

SI5328_OUT2_NSI5328_OUT2_P

LVDS12_N

LVDS13_N

LVDS02_NLVDS02_P

LVDS15_N

12V_FMC

LVDS01_PLVDS01_N

LVDS10_P

LVDS14_PLVDS14_N

LVDS16_P

LVDS18_PLVDS18_N

LVDS16_N

FMC_TRAN1_RX_N

FMC_TRAN3_RX_P

FMC_TRAN2_RX_P

FMC_TRAN1_RX_P

FMC_TRAN3_RX_N

FMC_TRAN2_RX_N

FMC_TRAN1_TX_PFMC_TRAN1_TX_N

FMC_TRAN2_TX_PFMC_TRAN2_TX_N

FMC_TRAN3_TX_PFMC_TRAN3_TX_N

3V3_VADJ_FMC

LVDS06_PLVDS06_N

LVDS19_N

3V3_FMC

LVDS12_P

FMC_TRAN0_TX_NFMC_TRAN0_TX_P

LVDS00_NLVDS00_P

3V3_VADJ_FMC

LVDS09_P

LVDS05_N

LVDS08_NLVDS08_P

LVDS04_NLVDS04_P

FMC_TRAN0_RX_NFMC_TRAN0_RX_P

FMC_SCL

PRSNT_C2M_L

FMC_SDA3V3_FMC

F26 H26

H29H28H27

H30H31

H39

H37

H34

G1

C40C39

J20

J40J39J38

J36J37

J32J31J30J29

J27J26J25J24J23J22J21

J19J18J17J16J15J14J13J12J11J10J9J8J7J6J5J4J3J2J1

K7

K15

K24K23

K3K4K5K6

K11K12K13K14

K16K17K18K19K20K21K22

K25

K27K28K29K30K31K32K33K34

K38K39K40

K2

K9K8

K10

C38C37C36C35C34C33C32C31

C29C28C27C26C25

C20

C18C17C16

C14C13C12C11C10C9C8C7C6C5C4C3C2C1

D40D39

D37D38

D36D35D34D33D32D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1

F40F39F38F37F36F35F34F33F32F31F30F29F28F27

F25F24F23F22F21F20F19F18F17F16F15F14F13F12F11F10F9F8F7F6F5F4F3F2F1

G4

G6G7

G2G3

G5

G8G9G10G11G12G13G14G15G16G17G18G19G20G21G22G23G24G25G26G27G28G29G30G31G32G33G34G35G36G37G38G39G40

A2

A25

A3

A5A6A7A8

A10A11A12A13A14A15

A17A16

A18A19A20A21A22

A24A23

A26

A28A29

A31A32A33

A35A36A37A38

A40

A4

A9

A27

A30

A34

A39

A1

B38B37B36B35B34B33B32

B39

B31

B28B27B26B25B24

B30B29

B17

B13

B18B19

B7

B5B4B3B2B1

B9

B16B15B14

B11B12

B40

B6

B20

B10

B8

H40

H36H35

H23H22H21H20H19H18H17H16H15H14

H11

H9H8H7H6H5H4

H2H1

E40E39E38E37E36E35E34E33E32E31E30E29E28E27E26E25E24E23E22E21E20E19E18E17E16E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1

H24H25

J28

H3

C21

C19

C15

C22

C24

H13H12

H10

J33J34J35

H38

K1

B21B22B23 C23

C30

H32H33

K26

K35K36K37

FMC_HPC_CONN

G4

G6G7

G1G2G3

G5

G8G9G10G11G12G13G14G15G16G17G18G19G20G21G22G23G24G25G26G27G28G29G30G31G32G33G34G35G36G37G38G39G40

GND

FMC_HPC_CONN

F40F39F38F37F36F35F34F33F32F31F30F29F28F27F26F25F24F23F22F21F20F19F18F17F16F15F14F13F12F11F10F9F8F7F6F5F4F3F2F1

FMC_HPC_CONN

E40E39E38E37E36E35E34E33E32E31E30E29E28E27E26E25E24E23E22E21E20E19E18E17E16E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1

GNDGND

FMC_HPC_CONN

H40H39H38H37H36H35H34H33H32H31H30H29H28H27H26H25H24H23H22H21H20H19H18H17H16H15H14H13H12H11H10H9H8H7H6H5H4H3H2H1

FMC_HPC_CONN

B38B37B36B35B34B33B32

B39

B31

B28B27B26B25B24B23B22

B30B29

B21

B17

B13

B18B19

B7

B5B4B3B2B1

B9

B16B15B14

B11B12

B40

B6

B20

B10

B8

GND

FMC_HPC_CONN

A2

A25

A3

A5A6A7A8

A10A11A12A13A14A15

A17A16

A18A19A20A21A22

A24A23

A26

A28A29

A31A32A33

A35A36A37A38

A40

A4

A9

A27

A30

A34

A39

A1

GND

GND

GND

*

*

*

FMC_HPC_CONN

D40D39

D37D38

D36D35D34D33D32D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1

GND

FMC_HPC_CONN

C40C39C38C37C36C35C34C33C32C31C30C29C28C27C26C25C24C23C22C21C20C19C18C17C16

C14C15

C13C12C11C10C9C8C7C6C5C4C3C2C1

GND FMC_HPC_CONN

K7

K15

K24K23

K3K4K5K6

K11K12K13K14

K16K17K18K19K20K21K22

K25K26K27K28K29K30K31K32K33K34K35K36K37K38K39K40

K1K2

K9K8

K10

GND

FMC_HPC_CONN

J20

J40J39J38

J36J37

J35J34J33J32J31J30J29J28J27J26J25J24J23J22J21

J19J18J17J16J15J14J13J12J11J10J9J8J7J6J5J4J3J2J1

PAGE:

DATE:TITLE:

ENGINEER:

A A

B B

C C

DD

1

12

23

34

45

56

67

78

8

6/9

05/09/2019

NICOLAS TESSIER

CLOCK

SI5328

I2

I5

I1

I3

L25V20%10UF

MPZ1608S221ATA00I90.1UFK25V10%K25V10%

I8

K25V10%

I101UF

I11

ABM8-166CRYSTALI6

0.1UFK25V10%

K25V10%0.1UFI12

I7 K25V10%

I140.1UF

K25V10%0.1UFI15

I16100S100MW1%

0.1UF

I4

I13

M1

C1

L1

U9

SI5328_VCC 3V3_0

SI5328_OUT2_NSI5328_OUT2_P

SI5328_SDASI5328_SCL

REC_CLOCK_P

SI5328_INT_ALM

REC_CLOCK_N

SI5328_VCC

SI5328_RST

4 3

1 2

2 1

10

67

1617

13

34

1115181920

21

32

5 29143033

2928

3534

3627232224

26

8131

25

12

GND

*

GND

GND

SI5328B-C-GMRJITTER ATTENUATING CLOCK

A1

GND2RST_B GND1

A2_SS

A0SCL

SDA_SDOSDI

CMODE

CKOUT2_NCKOUT2_P

CKOUT1_PCKOUT1_N

NC5NC4NC3NC2NC1VDD1

VDD3

CS_CA

NC7NC6LOLRATE1RATE0C2BINT_C1B

CKIN2_NCKIN2_P

CKIN2_NCKIN1_P

XBXA

VDD2

ABM8-166 114.285MHZ

4 3

1 2

GND

PAGE:

DATE:TITLE:

ENGINEER:

A A

B B

C C

DD

1

12

23

34

45

56

67

78

8

NICOLAS TESSIER

SFP+ CONNECTORS

7/9

05/09/2019

I65

I56

I57

I58100S100MW1%

S100MW1%100

I28

I29100S100MW1%

100S100MW1%

I30 I25

I37R25V20%22UF 0.1UF

I62S100MW1%

10K

IHLP2020BZER4R7M11

IHLP2020BZER4R7M11

I60S100MW1%

I68 I67

I66

I63

I55 I54

0.1UFK25V10%

22UFR25V20%

100S100MW1%

10KS100MW1%10K

0.1UFK25V10%

22UFR25V20%

R25V20%22UF

K25V10%0.1UF

10KS100MW1%

10KS100MW1% S100MW1%

10K

100S100MW1%

S100MW1%100

S100MW1%100

R25V20%22UF

K25V10%0.1UF

I43

I53 I52

I42

I40 I39 I38

I48

I47

I46

I50 I49

IHLP2020BZER4R7M11

0.1UF

I34R25V20%

R25V20%22UF

K25V10%0.1UF

R25V20%22UF

K25V10%0.1UF

I6 I8 I7 I9

100S100MW1%

S100MW1%100

S100MW1%100

I20

IHLP2020BZER4R7M11

I5

I4

CAGE-2198241-3

CAGE-2198241-3

I2

I3

I22I23

10KS100MW1%

10KS100MW1%S100MW1%

10K

100S100MW1%

IHLP2020BZER4R7M11

K25V10%22UF

K25V10%I33

I35

I36

I32

S100MW1%10K

S100MW1%10K

I69IHLP2020BZER4R7M11

IHLP2020BZER4R7M11

IHLP2020BZER4R7M11

I51I11

I19

I18

I1

I21

I14I13I1210KS100MW1%

I45

0402GREEN

I440402GREEN

I410402GREEN

I16

0402GREEN

I15

0402GREEN

I240402GREEN

I26

0402GREEN

I27

0402GREEN

I610402GREEN

I64

0402GREEN

I590402GREEN

I17

0402GREEN

I31?

??

?

?

?

?

?

J2

J2

SFP3_RN

FPGA_SDA

SFP3_RP

VCC_R_SFP3VCC_T_SFP3

VCC_T_SFP3VCC_R_SFP3

SFP3_TN

SFP1_RN

3V3_1

3V3_1

3V3_1

FPGA_SCL

FPGA_SDAFPGA_SCL

SFP1_RP

SFP1_TPSFP1_TN

VCC_T_SFP1VCC_R_SFP1

VCC_R_SFP1

3V3_1

3V3_1

3V3_1

VCC_T_SFP1

SFP2_TNSFP2_TP

VCC_T_SFP2VCC_R_SFP2

VCC_R_SFP0

SFP0_TN

VCC_R_SFP0 VCC_T_SFP0

3V3_1

FPGA_SDA

3V3_1

SFP0_RNSFP0_RP

VCC_T_SFP0

SFP0_TP

FPGA_SCL

3V3_1

3V3_1

FPGA_SDAFPGA_SCL

3V3_1

VCC_R_SFP2 VCC_T_SFP2

SFP2_RPSFP2_RN

SFP3_TP

3V3_1

1P11P2

2P9

1P5

1P10

1P12

1P14

1P11

2P1

2P142P152P16

2P20

1P15

2P7

1P91P81P7

1P171P16

1P13 2P13

2P2

2P192P182P17

1P31P4

1P181P191P20

1P6

2P112P12

2P10

2P62P52P42P3

2P8

4P9

4P11

4P204P194P184P174P164P154P144P134P12

4P8

4P1

3P203P193P183P173P163P153P143P133P123P113P103P93P83P73P63P53P43P3

3P13P2

4P4

4P6

4P10

4P24P3

4P7

4P5

2LOS

2TX_DIS2SDA2SCL

2MOD_ABS

2RX_GND1

2RD-2RX_GND2

1MOD_ABS

1TX_GND31TD-1TD+

1SDA1TX_DIS

2TX_GND22TD+2TD-

2TX_FAULT

2RD+1RD+

1VCC_T1TX_GND2

1RS01LOS1RS1

2RS0

1VCC_R

2TX_GND3

2VCC_T2VCC_R

2RX_GND3

2TX_GND1

1RX_GND2

1RX_GND3

1RD-

1RX_GND1

1SCL

2RS1

1TX_FAULT1TX_GND1

GND

* * *

*

*

4SCL

4RS0

4TX_DIS4TX_FAULT

4RX_GND1

4MOD_ABS

4SDA

3TX_FAULT3TX_GND1

3TX_DIS3SDA3SCL3MOD_ABS3RS03LOS3RS13RX_GND13RX_GND23RD-3RD+3RX_GND33VCC_R3VCC_T3TX_GND23TD+3TD-3TX_GND3

4TX_GND1

4LOS

4RD-4RD+

4RX_GND34VCC_R4VCC_T

4TX_GND24TD+4TD-

4TX_GND3

4RX_GND2

4RS1

*

***

*

*

GND

*

GND

GND

***

*

*

*

GND

*

*

*

***

GND

PAGE:

DATE:TITLE:

ENGINEER:

A A

B B

C C

DD

1

12

23

34

45

56

67

78

8

8/9

05/09/2019

NICOLAS TESSIER

JTAG CHAIN

I27 0.1UF

10KI35

S100MW1%10K

I29

K25V10%

I30

SN74AVC8T245PWR

I32

15S100MW1%

S100MW1%15I38

S100MW1%

NC7SZ66P5X

S100MW1%

I41

SN74AVC2T245RSWRI24

I2

K25V10%0.1UFI21

I22

S100MW1%10KI20

I25

0.1UFK25V10%I23

K25V10%

I40

15I39

I37

JTAG_SMT2I16

I28

I33

I310.1UF

K25V10%0.1UF

I34

CMSD2X7MI17 I36

I26

? ?

JTAG_TCK

JTAG_TMS

1V8

3V3_0

FMC_TDO_1V8FPGA_TDO_FMC_TDI_BUF

3V3_0

FMC_TCK_BUF

FMC_TDO

3V3_0

JTAG_TMS

FMC_TDO_1V8

PRSNT_C2M_L

3V3_0

FMC_TDO

FMC_TDO_SWJTAG_TDI

FMC_TDO_1V8

1V8

JTAG_TCK

FMC_TMS_BUF

JTAG_TCK

JTAG_TMS

FPGA_TDO_FMC_TDI

1V8

JTAG_TDI

1V8

1V8

SN74AVC8T245PWR

GND_3B8B7B6B5B4B3B2B1OE

VCCB_2VCCB

GND_2GNDA8A7A6A5A4A3A2A1DIRVCCA

SN74AVC2T245RSWR

VCCBVCCA

A1A2

DIR1OEGNDB2B1

DIR2

1110

123456789

141312

*

*

GND

USB-JTAG PROGRAMING MODULE

JTAG-SMT2

GND

TMS

TCK

GPI

O0

GPI

O1

GPI

O2TDO

VREFGNDVDD

TDI

SPST BUS SWITCH

NC7SZ66P5X

VCC

OE

A

GND

B

*

GND GND

GND

GNDGND

GND

GND

*

*

*

GND

PAGE:

DATE:TITLE:

ENGINEER:

A A

B B

C C

DD

1

12

23

34

45

56

67

78

8

NICOLAS TESSIER

MISC.9/9

05/09/2019

I20

I19

I17

NC7SZ66P5X

S32MW1%I15 I16

4.7KS32MW1%4.7K

4.7KS32MW1%

I13

4.7KI11

S32MW1%

CAT24C02YI_GT3I8I9

4.7KS32MW1%

I104.7KS32MW1%

I6PRISE-SMA_D

PRISE-SMA_DI5

PRISE-SMA_DI4

PRISE-SMA_DI3

PRISE-SMA_DI2

PRISE-SMA_DI1

I7CAT24C02YI_GT3

I12

I14

NC7SZ66P5X

I18

FMC_SCL 3V3_1

PRSNT_C2M_L

FMC_SDA

FPGA_SDA

PRSNT_C2M_L

3V3_1

FPGA_SCL

3V3AUX_FMC

FMC_SCLFMC_SDA

GA0 GA1

3V3_0

FPGA_SDA

3V3_0

SMA2_N

SMA2_P

SMA1_N

SMA1_P

SMA0_N

SMA0_P

FPGA_SCL

CAT24C02YI-GT3EEPROM 4KB IIC

VCCWPSCLSDA

A0

VSSA2A1

*

**

GND

GND

* *

SPST BUS SWITCH

NC7SZ66P5X

VCC

OE

A

GND

B

SPST BUS SWITCH

NC7SZ66P5X

VCC

OE

A

GND

B

GND

GND

CAT24C02YI-GT3EEPROM 4KB IIC

VCCWPSCLSDA

A0

VSSA2A1

*

PAGE:

DATE:TITLE:

ENGINEER:

A A

B B

C C

DD

1

12

23

34

45

56

67

78

8

• Schematics design finishing, CAD routing and manufacturing files (Q1 2020)

• Preseries production (Q2 2020)

• Preseries Tests with Valencia team (Q4 2020)

• Production (Q2 2021)

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 15

STARE Hardware Future Plans

• Firmware ongoing (See Gustav presentation)

• Slow Control Software to be defined and designed (6 months intern student TBD)

• Firmware Update (6 months intern TBD)

• Production test bench to be designed (6 months intern TBD).

• Built-in Self Test for 100 % assembly and design coverage (6 months intern TBD).

• Documentations (Q4 2020)

• Maintenance Contract

N. Karkour and G. Vinther-Jørgensen 20th Agata Week LNL Italy Sep. 2019 16

STARE Firmware Future Plans

• Thank you

N. Karkour G. Vinther-Jorgensen

20th Agata Week LNL Italy Sep. 2019 17