Data Exchange - 0312 - Prime Elettronica · The Valor Universal Viewer (VUV), a freely distributed...

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DATA EXCHANGE

Document 0312.0405Published April 2005

© 2005 Valor Computerized Systems, Ltd.All rights reserved.

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0312.0405 Data Exchange 2

Table of Contents

Chapter 1 OverviewIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ODB++ Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Intended Readers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 2 Getting Started

Chapter 3 CadenceAllegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Common Concepts for ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . 8Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Exporting ODB++/ODB++(X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Basic Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Description of Output Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Icon Description (Main Dialog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Advanced Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Direct Translation of Design into Enterprise 3000 . . . . . . . . . . . . . . . 18

Orcad-Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Common Concepts for ODB++ Output . . . . . . . . . . . . . . . . . . . . . . 19Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19File Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chapter 4 Mentor GraphicsBoard Station . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Common Concepts for ODB++ Output . . . . . . . . . . . . . . . . . . . . . . 22Post Processing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Basic Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Description of Output Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Description (Main Dialog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Direct Creation of ODB++/ODB++(X) . . . . . . . . . . . . . . . . . . . . . . 33Basic Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33


Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Description of Output Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Icon Description (Main Dialog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Advanced Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Direct Translation of Design into Enterprise 3000 . . . . . . . . . . . . . . . 41

PADS (formerly PowerPCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Common Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Define CAM Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Fill Copper Pour Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Create the ASCII File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Direct Translation of Design into Enterprise 3000 . . . . . . . . . . . . . . . 46

Expedition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Icon Description (Main Dialog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Supermax ECAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Chapter 5 ZukenVisula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Common Concepts for ODB++ Output . . . . . . . . . . . . . . . . . . . . . . 53Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Direct Creation of ODB++/ODB++(X) . . . . . . . . . . . . . . . . . . . . . . 55Basic Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Description of Output Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Icon Description (Main Dialog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Advanced Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Direct Translation of Design into Enterprise 3000 . . . . . . . . . . . . . . . 62

Board Designer (CR5000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Common Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Direct Translation of Design into Enterprise 3000 . . . . . . . . . . . . . . . 64

PWS (CR3000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Common Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Direct Translation of Design into Enterprise 3000 . . . . . . . . . . . . . . . 66

Cadstar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Direct Translation of Design into Enterprise 3000 . . . . . . . . . . . . . . . 68


Chapter 6 AltiumP-CAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Common Concepts for ODB++ Output . . . . . . . . . . . . . . . . . . . . . . 69Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Direct Translation of Design into Enterprise 3000 . . . . . . . . . . . . . . . 71

Protel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Common Concepts for ODB++ Output . . . . . . . . . . . . . . . . . . . . . . 72Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Direct Translation of Design into Enterprise 3000 . . . . . . . . . . . . . . . 79

Chapter 7 Number One SystemsEasy-PC for Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Chapter 8 PulsonixPulsonix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Chapter 9 ValorEnterprise 3000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Creation of ODB++ Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Description of Output Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Appendix A Thermal ModelStructure of a Thermal Model File . . . . . . . . . . . . . . . . . . . . . . . . 88BNF (Backus-Naur Form) of Rules . . . . . . . . . . . . . . . . . . . . . . . 88Sample Thermal Model File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Appendix B Extraction Files

Data Exchange

0312.0405 Last Update: April 7, 2005 12:48 pm Data Exchange 5

Chapter 1 Overview

IntroductionThis manual defines the requirements and procedures for translating PCB design data and producing ODB++ data files.

The ODB++ data format is a common language used for DFM and CAD/CAM data exchange. It overcomes data communication obstacles between design, manufacturing and assembly. Data in this powerful open database imparts an integrated and accurate physical model of all bareboard, component, and test related information.

The Valor Universal Viewer (VUV), a freely distributed software program, enables the ODB++ design data to be graphically viewed on Windows, Sun Solaris, or HP-UX workstations. Use the VUV to view Valor ODB++ data files in full detail.

Most PCB CAD design tools have the ability to output data in a variety of “low level” formats such as Gerber, Excellon, DXF, etc. Output to these formats is not covered by this manual.

ODB++ DescriptionODB++ is widely accepted as a practical de-facto standard within the electronics industry to efficiently move printed circuit bare-board, assembly and test data on the manufacturing-engineering level within design/manufacturing supply chains. It is designed as a simple yet comprehensive description of all entities needed in the manufacture of a printed circuit board. Originally defined by Valor, ODB++ is now in common use by 3rd-party tool providers within the industry. Valor is committed to a policy of openly supporting any and all organizations to successfully implement the ODB++ format.

ODB++ ODB++ uses a standard file system structure. A job in ODB++ is represented by a stand-alone directory tree that can be transferred between systems without any loss of data. The advantages of a directory tree compared to one large file are apparent when a job is being read from disk or saved to disk. The flexible tree structure allows only a small part of the job to be read/saved, avoiding the overhead of reading and writing a large file. When a job tree has to be transferred to another system, standard compression utilities can be used to convert a directory tree into one flat file.

ODB++ (X) ODB++(X), based on the emerging XML standard, was developed to simplify the data transfer between design and manufacturing. Based on the information stored in ODB++ and coupled with the needs expressed by end users, ODB++(X) extensively covers all aspects of a manufacturing job. By using XML as the


Chapter 1 Overview

definition language, ODB++(X) allows developers to use off-the-shelf tools to understand and process ODB++ jobs. Such files have extension .xml.

Intended ReadersThis manual is intended for users of PCB CAD design systems that are responsible for preparing and submitting designs to manufacturing departments (either in-house or sub-contract) that use Valor software tools.

It is assumed that the reader has knowledge of the PCB Design tools and their output procedures.

TerminologyThe term Windows in this manual refers to Windows NT/2000/XP Professional operating systems unless otherwise specified.




This document provides instructions for preparing an optimized design package from your CAD environment.

This document is divided into sections by CAD tool. Locate the section that corresponds to the CAD tools you use. For convenience, you can click on the page references and jump directly to the correct page.

CAD System Section Version(s) SupportedCadence “Allegro”

“Orcad-Layout” 11.0 and upwards6.4.2 and upwards

Mentor Graphics “Board Station” “PADS (formerly PowerPCB)” “Expedition” “Supermax ECAD”

B2 and upwards2.0 and upwardsWG20029.0 and upwards

Zuken “Visula” “Board Designer (CR5000)” “PWS (CR3000)” “Cadstar”

CADExpert 3.5 (Cadif 4) and upwards6.02 and upwards12.0 and upwardsCadstar 6 (Cadif 4) and upwards

Altium “P-CAD” “Protel”

2.2 (v12) and upwards99SE & DXP (ascii v3 & 4)

Number One Systems “Easy-PC for Windows” 8.0 and upwards

Pulsonix “Pulsonix” 3.0 and upwards

Valor “Enterprise 3000” All


Chapter 3 Cadence

Chapter 3 Cadence

Allegro

Common Concepts for ODB++ OutputA Cadence Allegro design is saved in one binary file with the suffix brd, usually referred to as the brd file. The brd file is generally independent, with the exception of references to library symbols used for displaying thermal relief pads.

Inside the brd file, the data is organized in logical layers called subclasses. Each subclass belongs to a class which represents a particular type of data.

The following classes are included in the brd file:

MostRelevant

etch describes copper routes and planes

via class describes via padstacks

pin describes toeprint padstacks

package geometry describes the physical components in the design board

geometry describes the physical outline of the design

manufacturing contains drill markers and various drawing data

ref des contains component reference designators

LessRelevant

package keepin package keepoutanalysisanti etchcomponent valuedevice typedrawing formatdrc error classroute keepinroute keepouttoleranceuser part numbervia keepout

Before generating ODB++ outputs, the Allegro film table must be completely defined so the physical layering and stackup of the PCB can be translated correctly.


Chapter 3 Cadence

Creation of ODB++ OutputThe Allegro to ODB++ translator and the Valor Universal Viewer (VUV) for viewing ODB++ files, are contained within the ODB++ Inside suite that forms part of the Allegro installation.

Use the following procedure to generate an ODB++ file:

• Start the Allegro application and load a design.

• Select the ODB++ icon from the Allegro toolbar to display the ODB++ dialog.

If you do not have the ODB++ translator installed, the following message appears:

Exporting ODB++/ODB++(X)

Windows The translator can be activated from:

• Start > Programs > Valor > ODB++ Inside. > ODB++ Inside

• Command line: %ALLEGRO_BRD2ODB%/brd2odb.exe -gui

UNIX Type the following command: $ALLEGRO_BRD2ODB/brd2odb -gui


Chapter 3 Cadence

After issuing one of the above commands, the ODB++ Inside window appears, as in the figure below. In this window, you set both basic and advanced Output Options.

Basic Options

General

Input Path Specifies the location directory of the input file. Press to navigate.

Output Path Specifies the destination directory of the generated ODB++ file. Press to navigate.

The default directory for both Input and Output Path is the path to the current working directory.

Output JobName

Specifies the name of the ODB++ file.

Log File Path Specifies the path to the log file. By default a new log file is created for each translation. If the ‘Append’ checkbox is marked, log messages will be appended to the most recent log file.

Output Options

Remove EDAdata

Removes Component/Package information from the ODB++ job.

NeutralizeNets

Renames nets numerically.


Chapter 3 Cadence

GZIP Specifies whether to compress the ODB++ job. The ODB++ job is made up of several files describing the output. If activated, compression creates a single ‘tar’ed and zipped file. The default is not to compress.

ODB++(X) ODB++(X) is a representation of the ODB++ format in XML (Extended Markup Language) format. The ODB++(X) Interface enables the user to determine the data that the ODB++(X) format holds. Check ‘ODB++(X)’ to export in this format.

ShowODB++(X)

Settings

Select <Show ODB++(X) Settings> to view/modify the export options.

There are three export modes:

FULL - All ODB++ job data is represented. Job layers exported to ODB++(X) are shaded green.

FAB - Fabrication data only is represented.

ASSY - Assembly data only is represented.

The Fabrication and Assembly modes have several levels of ODB++(X) output:

• Fabrication has 4 levels - 1 (maximum) to 4 (minimum).

• Assembly has 6 levels - 1 (maximum) to 6 (minimum).


Chapter 3 Cadence

The following table details the default output that is generated when selecting an export mode according to level:

Default Output Table

Description of Output TableOrig BOM/AVL files - Not functional in this translator.

BOM/AVL - Not functional in this translator.

Comp/Pkg + logical nets - Outputs components, packages and nets that represent a logical connection between component pins.

Outer layer copper pads - Outputs all outer signal layer pad data (not traces or surfaces).

Mask/Paste/Screen Layers - Outputs all data on solder mask, solder paste and silk screen layers.

Drill/Rout layers - Outputs all data on Drill and Rout layers.

Doc layers - Outputs all data on Documentation layers.

Phys Nets - Outputs netlist information.

Outer copper layers non-pads - Outputs all data from the outer layers (Pads, vias, traces, surfaces, etc.).

Inner layers - Outputs all data from the inner layers.

Non-Doc Misc layers - not applicable during translation.

Raw data files - not applicable during translation.

1 2 3 4 5 6 7 8 9 10 11 12

Mode Level Orig BOM/AVL Files

BOM/AVL

Comp/Pkg + logical nets

Outer layer copper pads

MaskPasteScreen layers

Drill/ Rout layers

Doc layers

Phys Nets

Outer copper layersnon-pads

Inner layers

Non-DocMisc layers

Raw data files

Full NA NA Y Y Y Y Y Y Y Y Y Y

FAB 1 NA NA Y Y Y Y Y Y Y Y Y Y

2 NA NA N Y Y Y Y Y Y Y Y Y

3 NA NA N Y Y Y Y Y Y Y Y N

4 NA NA N Y Y Y Y Y Y Y N N

ASSY 1 NA NA Y Y Y Y Y Y Y Y Y N

2 NA NA Y Y Y Y Y Y Y Y N N

3 NA NA Y Y Y Y Y Y Y N N N

4 NA NA Y Y Y Y Y Y N N N N

5 NA NA Y Y Y Y Y N N N N N

6 NA NA Y Y N N N N N N N N


Chapter 3 Cadence

Layers Mode Default - Layers are output according to the Default Output Table above.

All - All layers are output, overrides the default settings.

None - No layers are output, overrides the default settings.

Units Metric (mm) - millimeter

Imperial (mils) - 1/1000 of an inch

Set DefaultValues

Resets XML Export Settings to these defaults:

Export Mode - ASSY

Level - 6

Layers Mode - Default

Job’s Layers that will be exported to XML format - Components/Packages + logical nets Outer Layer copper pads

Icon Description (Main Dialog)

ShowOptions

Toggles between Show/Hide to display or hide the Advanced Options setting window. For information, see “Advanced Options” on page 15.

Help Opens the translator’s manual in PDF formatThe configuration parameter gns_pdf_viewing_prog is set with the path and command to run a PDF viewer.

For example:

gns_pdf_viewing_prog=/sw/bin/acroread -useFrontEndProgram

where /sw/bin/acroread is where the PDF viewer is stored.


Chapter 3 Cadence

Translate Shows the list of selected parameters that will be used in the translation process.

• Click <Accept> from the Selected Options Viewer to start the translation process.

• Click <Back> to close the above window and return to the main dialog window.

View Log Shows the translator log. All program messages are written to this file. From this window you can:

• Click <Clear Log> to clear the log file.

VUV After translation, press this icon to display the design in the Valor Universal Viewer (VUV). Turn on/off viewed layers by selecting the layer from the displayed list. It appears similar to the following window.


Chapter 3 Cadence

Quit Quits the translation program.

Advanced Options

Click to display Advanced Options.

Read DRCfeatures

Adds DRC features to physical DRC layers. DRC layers are added as BOARD document layers. Some can be merged into one physical layer depending on configuration parameter setting.

Suppress Enables Cadence suppression of unconnected pads.

Silk Fill Fills surfaces on Cadence silk screen layers.

Therm Error The translation process aborts with a message listing the padstack / thermal names that did not have a match in the models file.

DeleteExtracted

Files

Deletes all temporary extract files created during translation.

Note If you do not specify Delete Extracted Files and do specify Compress in the Basic tab, the files are compressed.

Allegro 14.0ThermalSymbols

Indicates whether the .brd file being translated uses Allegro 14.0 thermal symbols definition functionality.


Chapter 3 Cadence

Activate VUVafter

translation

Activates Valor Universal Viewer after successful translation. This enables the ODB++ job to be displayed.

EnableSequential

Stackup

Suppresses unconnected pads on electrical layers that are the start/end layers of blind drill layers.

Skip Refdeswith Asterisk

Skips a refdes whose name contains the character ‘*’.

Use thermalmodel file

Enables setting of the Thermal file and model to be used. If known, type the name

path and the name of the file and model in the text boxes or press to locate the thermal file.

When a thermal file is selected, you may choose the model names from the selected files displayed in the combo-box below. If you do not specify a thermal model file, a default model is used that uses direct connect and no thermals. For an explanation of the thermal model, see Appendix A.

SuppressShape Fill

Settings

Source can be User defined or Films. When set to User defined, select the options to be No, Yes, or Part.

No - disables suppression

Yes - enables suppression on all layer parts

Part - enables suppression on listed layers

If Part is chosen, enter the affected layer-list, where <layer-list> is “<lyr1>;<lyr2>;...<lyrn>” - a list of layers on which to enable suppression. This list must be enclosed in double-quotes (" ") and each layer name must be separated by a semi-colon (;). <lyr1>...<lyrn> are the names of the layers as defined in Cadence Allegro.

This parameter causes the translator to skip the creation of the laminate area (suppress shape-fill) for the specified layers. The laminate area is created for all negative layers by creating a single surface consisting of the board outline (filled) with all split plane areas subtracted from it. This parameter corresponds to the '-s' parameter in the Cadence artwork command. The default is ‘-s none’ (that is, Suppression disabled).

SuppressLayers

To specify layers (as named in the CAD data - copper layer names are the same both in CAD and in Enterprise.) to which to apply Suppress Shape Fill Settings parameters. Use semi-colons ‘;’ to separate layer names. This field appears in the window when Suppress Shape Fill Settings is specified as Part.

ComponentOutline

This determines the component outline according to the ASSEMBLY_TOP / ASSEMBLY_BOTTOM classes of package geometry or by the sub-classes, PLACE_BOUND_TOP / PLACE_BOUND_BOTTOM.


Chapter 3 Cadence

Place Bound - (recommended) when place bound shapes are available they will be used for the component outline, otherwise the limits of the assembly features will be used.

Assembly - When this option is chosen, the application activates a heuristic algorithm, which tries to determine the actual component outline from the collection of data on the ASSEMBLY_TOP(BOTTOM) class. Note that using this option might result in an unexpected component outline, since the data defining it is expected to be complete in terms of ODB++, that is a well defined closed polygon.

Padflash Allegro Pad definitions can have Padflash codes which effectively override the pad size information for the pad stack. This information is extracted into the 12th. field of the pads extract file (pads_[brd name].out).

For instance, on fiducials, a designer defines a padstack called FID120RD40RD that appears in Allegro as a 120 mil diameter pad with a 120 mil diameter solder mask. It also has a Padflash definition of ‘RD40’.

Ignore (default) - the Padflash field is ignored and instead, the pad size is used. So, during translation the example padstack would be constructed of 120 mil diameter pads.

Substitute - the name in the Padflash field will be used in conjunction with the thermal models file (see Appendix A) to determine what is placed at the location. In this case, the Padflash name RD40 would determine the actual fiducial on the copper layer based on the current Thermal Model.

For most installations, ‘Substitute’ is the recommended setting for this parameter.

ProfileSymbol

Defines symbol type for arcs and line which are part of the step profile polygon.

Round - the symbol type is round.

Square - the symbol type is square.

Symboltolerance

The system compares shapes that are input, with symbols previously input in the same session, and with standard and semi-standard system symbols.

When Symbol tolerance equals a positive value, the input shape is compared to system symbols within the tolerance specified. If it can be matched, the system symbol is used.

Outline size When creating negative plane layers, the size of the frame is the value of this parameter. For accurate translation this value should match the -o option in the Cadence Allegro artwork program. If these two parameters differ, the frame will be created according to the value in Outline size. Value is specified in inches.

When Symbol tolerance equals zero, only if the input shape matches exactly a system symbol, the system symbol is used. If it does not match, the input shape is used ‘as is’ without change.

Use this parameter according to your discretion as to type of file you expect to input. The lower the tolerance the more critical the system is in judging that shapes are equivalent. Value is specified in mils.


Chapter 3 Cadence

AlternativeConfiguration

File

Specifies another configuration file. Press to find the correct file.

Direct Translation of Design into Enterprise 3000For users that have Valor Enterprise 3000 within their organization, and want to interface directly, the procedure is fully described in Document 0303 Cadence Allegro/APD Interface Manual. Please refer to this manual for instructions.


Chapter 3 Cadence

Orcad-Layout

Common Concepts for ODB++ OutputThe database for the application is a binary file. The Binary file extension is usually.MAX and the ASCII file extension is usually.MIN.

The translator can read either .MIN or .MAX files. Since these files do not contain fabrication data, the generated ODB++ file is not suitable for Fabrication analysis. It only contains the information necessary to support Assembly analysis.

Creation of ODB++ OutputUse the following procedure to generate an ODB++ file:

• Start the Orcad PCB application and load a design.

• Select File > Export > Layout to ODB++, as shown.

The following window appears.


Chapter 3 Cadence

File Names

Input LayoutMAX or MIN

file

Specifies the name of the input file. Press <Browse> to navigate.

Output ValorDirectory

Specifies the destination directory of the generated ODB++ file. Press <Browse> to navigate.

Output ValorJobname

Specifies the name of the ODB++ job.

Options

Overwriteexisting files

Overwrites files with the same name.

Outputcopper pours

Outputs copper pours to the board’s copper layers.

Outputformat

Specifies the type of output to be generated.

Create ODB++ Output - Output is in ODB++

Create XML++ Output - Output is in XML (Extended Markup Language)

Translate Generates the output file.

Cancel No output is generated.


Chapter 3 Cadence

The generated ODB++ file may be viewed with the Valor Universal Viewer (VUV), which can be downloaded from the Valor web pages at http://www.valor.com. It appears similar to the following window.




Chapter 4 Mentor Graphics


Board Station

Common Concepts for ODB++ OutputThe Mentor Graphics Board Station design is a collection of files inside a directory structure. A versioning mechanism exists which maintains a number of copies (typically 3) for each file. Most of the files are readable ASCII files, with the notable exception of the file geoms which is one of the most important files.

In the Mentor Graphics Board Station database, the hierarchy of the information is as follows:

• A list of components, where each one refers to a geometry (Package in the Valor notation). A component also has pins which refer to geometries.

• Each geometry is a collection of many features, each being drawn on a logical layer.

• A special type of geometry, the Artwork Order geometry, contains all the artworks which should be produced and the logical layers to be included inside each. Additional parameters which affect the output may be attached to these artworks.

• The tech file defines the order of the copper layers within the board. This file has no reference to support layers (solder mask, silkscreen, etc.).

• The names of the logical layers carry special meaning in the Mentor Graphics Board Station database.

There are four types of logical layers:

1. Data reporting (such as Errors)

2. Data storage (such as board_outline)

3. Electrical (such as signal, signal_1)

4. Top and bottom mapping (such as pad, pad_1, pad_2)

There are quite complex mapping rules which determine which logical layer, depending on type of layer, will receive a feature. For example, a feature being assigned to layer signal will appear in all layers which are called signal_n where n is an integer number >= 1. A feature in a component geometry which is assigned to layer pad will appear in pad_1 if the component is on the top side and on pad_2 if the component is on the bottom side.



• A special traces file contains all the lines which are used to connect component pins. It also contains the vias which are used in this process and the areas (planes) which were created. Areas can be solid or hatched but also outlines; in which case they are used to define split planes in negative power and ground layers.

• Power and ground layers in the Mentor Graphics Board Station database are always produced negative. Although it is possible to create a signal layer using solid areas which will serve as a ground layer, within Mentor Graphics Board Station it will be considered a signal layer.

• Features which are not a direct part of a component or the connections between them are located inside the board geometry in the geoms file.

• A special panel geometry can be created which adds multiple boards to create a step and repeat pattern. This feature is fully supported by Enterprise 3000 (a panel step containing step and repeat information is created).

List of Relevant Files The following files are required for a correct translation (the listing is in order of importance):

mfg/neutral_file mfg/geoms_asciitracestechlayersaperture_tabledrill_tablepinsvariants

mfg/neutral_file

The neutral_file contains all the required information about components and pin locations. It is not a standard part of the database and has to be created on the Mentor Graphics Board Station system.

Note Components named in the component declaration of this file should not contain spaces. Use ‘A1B2’ and not ‘A1 B2’.

A full neutral_file contains several sections with information:

• BOARD - board attributes

• NET - net points

• GEOM - packages and pins

• COMP - components and toes

• HOLE - drilled holes

• PAD - approximate shape of pads

All of them can be read, except the HOLE section which is not needed since it is derived by other means.

required

optional

strongly advised



mfg/geoms_ascii

The geoms_ascii file is an ASCII representation of the geoms file inside the pcb directory. It is not a standard part of the database and has to be created on the Mentor Graphics Board Station system.

The geoms_ascii file contains commands written in the Mentor Graphics language called AMPLE. Each command starts with the characters $$ and has the following format:

$$command(param_1, ... , param_n)

The geoms_ascii file is composed of a series of $$create_... commands.

Each $$create command defines one of the following entities:

PANELBOARDCOMPONENTPINVIADRAWINGGENERIC_PARTSTACKUP

All geometries, except the Artwork Order geometry, contain figure commands such as $$circle, $$path, $$text and $$polygon. Some of them include special attributes which are specific for the geometry (such as a drill hole for a pin geometry). The Artwork Order geometry contains the mapping of logical layers to artwork pieces. This geometry must exist at least once in the geoms_ascii file for the translation to succeed.

tracesfile

The traces file contains the results of the routing process. Legal commands inside the traces file are:

– ST - status line (first and last lines of file)

– XRF - names of layers, referenced later in the file

– UNITS- defines the units used in the file

– WIR,ANT,SEG- describe fully routed connections (lines and vias)

– TIE - synonymous with WIR.

– FIL,ARE/ARS,ISL/ISS, VER- definition of area-fill/power-fill shapes and cutouts.

– TTI,TTT - apply actual signal thermals to the design,according to the TTI (Thermal Tie Instance)statements that relate to the TTT (Thermal TieTemplate) statements.

– TET- teardrop templates.

Note The version of the Mentor Graphics input is automatically detected from the traces file.

techfile

The tech file contains the physical order of copper layers within the board. It also contains information about geometries which do not go through the board (blind and buried vias). Another valuable piece of information inside the tech file is the net rules which are needed when generating signal layer thermal pads and mixed layers.



The tech file is also composed of AMPLE commands. Here is an example of a section which defines the physical layer order:

In the example above, there are only 8 physical layers. The command name $$define_physical_layer is misleading since these are actually logical layers. This section, combined with the stackup definition, provides the information necessary for creating the physical board structure.

layersfile

The layers file contains layer data that describes the arrangement and characteristics of the system data layers. The Mentor Graphics Board Station classifies layers into four groups. In particular, top and bottom layers are treated differently than other layers. The layers file may add more names which will be treated as top and bottom layers.

The layers file is an ASCII file, and is not written in AMPLE.

aperture_table

file

The aperture_table file contains information about Dcodes (in other words, the wheel). Some pieces of information can only be derived by looking in this file. These include:

• The spot pad which will be used for NPTH drill holes (taken by default as the minimal circular flash aperture)

• The brush which is used for area fills

• The size of tiebars for signal layer thermals

• The definition of thermals used in P&G layers

drill_ tablefile

The drill_table file includes the mapping of drill bits to the positions in a drill magazine. For each drill position, the drill table defines a drill size, hole tolerances, hole plating and the name of generic geometry used for creation of the drill symbol

$$define_physical_layer( 1, “comp_ver”, “SIGNAL_1”, “PAD_1”);$$define_physical_layer( 2, “int1_hor”, “SIGNAL_2”);$$define_physical_layer( 3, “int2_ver”, “SIGNAL_3”);$$define_physical_layer( 4, “int3_hor”, “SIGNAL_4”);$$define_physical_layer( 5, “vcc”, “POWER_1”);$$define_physical_layer( 6, “scsivcc”, “POWER_2”);$$define_physical_layer( 7, “665vcc”, “POWER_3”);$$define_physical_layer( 8, “752vcc”, “POWER_4”);$$define_physical_layer( 9, “avcc”, “POWER_5”);$$define_physical_layer( 10, “cpu3v”, “POWER_6”);$$define_physical_layer( 11, “ctlvcc”, “POWER_7”);$$define_physical_layer( 12, “cvcc”, “POWER_8”);$$define_physical_layer( 13, “hvcc”, “POWER_9”);$$define_physical_layer( 14, “iovcc”, “POWER_10”);$$define_physical_layer( 15, “mvcc”, “POWER_11”);$$define_physical_layer( 16, “gnd”, “POWER_12”);$$define_physical_layer( 17, “752gnd”, “POWER_13”);$$define_physical_layer( 18, “int4_ver”, “SIGNAL_5”);$$define_physical_layer( 19, “int5_hor”, “SIGNAL_6”);$$define_physical_layer( 20, “int6_ver”, “SIGNAL_7”);$$define_physical_layer( 21, “cond_hor”, “SIGNAL_8”,



for a specific drill size. These names are used during translation to create drill symbols on the relevant documentation layers.

pins file The pins file contains pin properties (name, value).

The following is a pins file, an ASCII file, for the property PINREF.

variants file The variants file contains a list of variants and their description

The following is a variant file; it is an ASCII file:

Artwork vs.Layers Order

The ‘physical’ layers order is defined in the Mentor Graphics Board Station database in the tech.tech_XXX file by the following command:

$$define_physical_layer( NN,...)

Where NN defines the physical layer sequence in the stackup.

However, some of Mentor Graphics' ‘physical’ layers are really logical ones, that is, several logical layers are mapped to one physical layer in the stackup.

The <list of logical layers> in the geoms_ascii file command defines logical layers that are mapped to a single artwork:

$$attribute( "ARTWORK_##_LAYER_DEFINITION", "<list of logical layers>");

(the ## is irrelevant to the artwork sequence in the stackup)

This command defines the physical layer (artwork) that contains data from all logical layers named in this <list>.

# BOARD STATION PINS FILE FORMAT 2.0# Pin property is presented in the format (prop_name, prop_value).## PINReference-Pin_noProperties

PIN C1-1 (PINREF,"IN,0.0,0.12,0,CC,0.06,0.06,0.01,std,1,U,+")

# PCB_DA VARIANTS FILE FORMAT 1.1# Date : Tue Mar 19 20:02:03 2002#

########################## Variant Definitions ##########################VARIANT OT_ADDESCRIPTION "201130185"VARIANT OT_TDESCRIPTION "201130186"VARIANT OTMUXDESCRIPTION "201130184"



For example, you may notice that the SIGNAL_1 layer is usually defined in ARTWORK_01_LAYER_DEFINITION. However, solder paste, solder mask and silk screen layers must be ‘upper’ in the stackup. Therefore, SIGNAL_1 layer will not be mapped to the first artwork in the stackup.

The definitions in the tech file are used for copper layers. The regular order is used, as always, for the other board layers.

Post Processing OptionsActions which can be performed on the fly, during output, are:

• Adding teardrops

• Eliminating non-functional pads

• Offsetting the design in X, Y or both

• Creating signal layer thermals

In addition, the operator can choose whether he wants to output only the board (one-up) or a multi-board panel (with step and repeat).

Important Note Mentor Graphics Board Stations’ Process Panels option appears in the Export to ODB++ dialog in Fablink versions prior to EN2004.2. If using such a version, it must be set to No. Setting to Yes, corrupts data. From version EN2004.2, it does not appear.

Completion of the Mentor Graphics Board Station artwork table is a prerequisite for creation of ODB++ from the Mentor Graphics Board Station database. The artwork order table is used to create the physical layer stackup of the board, and the mapping of Mentor Graphics logical design layers to physical board layer graphics.


• Start the Design Manager and select a design.

• Start FabLink.



• Select File > Export > To ODB++ to display the following dialog.

If you do not have the ODB++ translator installed, the option is not available.The translator is available as a 'downloadable' Service Pack to Mentor Graphics Board Station Customers, with a current Mentor Graphics support contract.

Basic Options

General

Input Path Specifies the location directory of the input file. Press <Browse> to navigate.

Output Path Specifies the destination directory of the generated ODB++ file. Press <Browse> to navigate.The output file is put in the manufacturing (mfg) directory within the design directory structure.

Output JobName


Log File Path Specifies the path to the log file. Press <Browse> to navigate. By default a new log file is created for each translation. If the ‘Append’ checkbox is marked, log messages will be appended to the most recent log file.



Output Options

Remove EDAdata


NeutralizeNets


GZIP Specifies whether to compress the ODB++ job. The ODB++ job is made up of several files describing the output. If activated, compression creates a single ‘tar’ed and zipped file. The default is not to compress.


ShowODB++(X)

Settings



FULL - All ODB++ job data is represented. Job layers exported to ODB++(X) are shaded green.



The Fabrication and Assembly modes have several levels of ODB++(X) output:



















1 2 3 4 5 6 7 8 9 10 11 12


BOM/AVL




Drill/ Rout layers

Doc layers

Phys Nets


Inner layers

Non-DocMisc layers

Raw data files



















Set DefaultValues


Export Mode - ASSY

Level - 6



Description (Main Dialog)

ShowOptions




Help Opens the translator’s manual in PDF format.






Quit • Quits the translation program.





Direct Creation of ODB++/ODB++(X)


• Select Start > Programs > Valor > MBS2ODB translator > MBS2ODB.

• Command line: %MBS2ODB_DIR%\mbs2odb

UNIX Type the following command: $MBS2ODB_DIR/mbs2odb

After issuing one of the above commands, the Mentor Graphics Board Station ODB++ Export popup appears, as in the figure below. In this popup, you set both basic and advanced Output Options.

Basic Options

Input PathSpecifies the location directory of the input file. Press to navigate.


The default directory for both input and output path is the path to the current working directory.

Output JobName


Log File Path Specifies the path to the log file. By default it creates a new log file for each translation where ordinary number xxx in log_mbs2odb_xxx.txt increases by 1 for each translation. If the ‘Append’ checkbox is marked, log messages will be appended to the log file with the highest number.



Output Options

Remove EDAdata


Neutralizenets


GZIP Specifies whether to compress the ODB++ job. The ODB++ job is made up of several files describing the output. If activated, compression creates a single tar’ed and zipped file. The default is not to compress.


ShowODB++(X)

Settings



FULL - All ODB++ job data is represented. Job layers exported to XML are shaded green.



The Fabrication and the Assembly modes have several levels of XML output:



















1 2 3 4 5 6 7 8 9 10 11 12


BOM/AVL




Drill/ Rout layers

Doc layers

Phys Nets


Inner layers

Non-DocMisc layers

Raw data files



















Set DefaultValues


Export Mode - ASSY

Level - 6




ShowOptions


Help Opens the translator’s manual in PDF formatFor example:

gns_pdf_viewing_prog=/sw/bin/acroread -useFrontEndProgram

where /sw/bin/acroread is where the PDF viewer is stored.





Advanced Options

• Click to display Advanced Options.

Read DRCfeatures

Enables reading in of DRC data (Such as: routing outline, placement_outline, via_keepout) into the translated job. The default is No.

Roundcorners

Creates round corner surfaces, according to fill brush, or according to the traces file description. The default is No.

Read$NONE$ net

info

Enables users to read in $NONE$ nets defined in the neutral_file, for netlist analysis purposes. The default is Yes.

Processbreakout

geometries

Ignores component breakout geometries, as required for jobs routed by external tools.

When Read Traces is set to Yes, Process breakouts must be set to No to prevent shorts. You cannot set both Read traces and Process breakouts to Yes to disallow unintended shorts. The default is No.

Read inUnplated

Builds padstacks for unplated holes. The default is Yes.



Ignore Comp.Layout Type

Ignores the Component_Layout_Type property of a Mentor Graphics Board Station component, that affects the .comp_mount_type attribute of a ODB++ component. The default is No.

Aperture Defines aperture units.

Options are inches, Millimeters, mils, centimeter, tenth of a mil and Automatic. The default is Automatic.

Drill Defines drill symbol units.

Options are: inches, Millimeters, mils, centimeter, and tenth of a mil and Automatic. The default is Automatic.

Fill Hatch Specifies how hatched surfaces are to be filled.

Options are: None, Part, All, Default. The default is Default.

None - all hatch cells are empty (not filled).

Part - only hatch cells around the border are filled.

All - all hatch cells are filled solid (convert hatch to solid).

Default - fill hatch surface according to Mentor Graphics database design version:

prior to version 8.6.5 it is the same as None, afterwards it is the same as Part.

Pins NFPRemoval

Enables padstack optimization of unused pins and pins with no net.

None - no removal of non-functional pads

Unused Pins - removes isolated pads (not connected to any other copper pad, trace, or surface)

Pins with No Net - removes pads in net $NONE

The following rules are applied:

1.Pads are removed on signal layers only.

2.Pads are not removed for external signal layers of the padstack span.

3.SMD pins are not processed.

4.Only isolated pads (not connected to any other copper pad, trace or surface) are removed.

5.Each modified padstack is assigned with the attribute .pf_optimized on the pad in the matching drill layer. This enables the identification of layers where padstack optimization, the removal of pads, has taken place.

6.In case Pins with No Net option is selected, rules 2 and 4 are ignored.

Vias NFPRemoval

Enables padstack optimization of unused vias.

None - no removal of non-functional pads

Unused Vias - removes isolated pads (not connected to any other copperpad, trace, or surface)

Rules are the same as described in Pins NFP Removal. (Rule 6 is not applicable.)



Read tracesflag

Specifies which trace routing records are to be read from the traces file.

Options are: Yes, No, All. The default is Yes.

Yes - reads complete wired traces (WIR records)

No - does not read any traces

All - reads complete and incomplete wired traces (WIR and INC records) from traces file.

Componentoutline by

Enables choice of Place or Body geometry to determine component outline. Each component outline must be a single, closed polygon. Options are: Place, Body. The default is Place.

Place - from the Placement records

Body - from the Body records

Thermalpads rotation

by

Specifies whether ties are to be rotated.

Options are: Component, None. The default is Component.

Component - instructs the system to rotate the ties together with the component

None - does not rotates the ties. Use this option when you want to rotate the ties manually.

Read inPanel/Boardgeometries

Determines whether to read in Board, Panel or Flatten Panel geometry.

Board - reads in board data only.

Panel - Board and all panels are read in. Panels are translated into ODB++ step & repeat data.

Flatten Panel - panel data is replicated (components and features), as if the step contains only one board.

The selection of Panel or Board must conform to the parameters set in the Mentor Graphics ‘Create Neutral File’ window.

If the Mentor Graphics ‘Multiple Board Data on Panel’ parameter is set Off, you must select Board in the dialog window.

If the Mentor Graphics ‘Multiple Board Data on Panel’ parameter is set On, you must select Panel and type a panel name in the dialog Panel Name field identical to the name chosen in the ‘Create Neutral File’ window.

If you select the wrong option, a shift of data may occur.

Minimum linewidth

Specifies the number of mils to extend the outline on negative planes. The value is between 0 to 2.5. The default is 0 mils.



Symboltolerance

Any new symbol that is encountered during the translation is compared with symbols that have previously been generated during the translation. If the new shape is within the tolerance value specified, the previous shape is used. The value is between 0 to 0.5. The default is 0.2 mils.

Model file Use thermal model file - enables setting of the Thermal file and model to be used.

If known, type the name of the file and the path in the text boxes or press to locate the thermal file. If you do not specify a thermal model file, a default model is used that uses direct connect and no thermals. For an explanation of the thermal model, see Appendix A.

Direct Translation of Design into Enterprise 3000For users that have Valor Enterprise 3000 within their organization, and want to interface directly, the procedure is fully described in Document 0302 Mentor Graphics Board Station Interface Manual. Please refer to this manual for instructions.



PADS (formerly PowerPCB)

Common ConceptsIt is not possible to generate ODB++ output direct from the Mentor Graphics PowerPCB application. An ASCII file is required to be created from the PowerPCB job and sent to manufacturers that use Valor Trilogy 5000. This file has the suffix .asc and contains all data necessary for translation.

The following steps should be used to generate the ASCII file:

• Define completely CAM documents.

• Set Pour Manager to ‘Flood All’. If there are overlapping copper pour outlines, find them and manually fill them one by one. If the design uses split/mixed planes, the planes should be filled in as well.

• Create the ASCII file.

Define CAM DocumentsThe layers created by the translation process do not correspond to the layers defined in the PowerPCB job. Rather, they correspond to the CAM documents defined for the job since they must represent the physical layer stackup of the board.

Only three layers are created for a PowerPCB job with no defined CAM documents: the top and bottom component layers, and the drill layer. All other layers, electrical and non-electrical, correspond to CAM documents defined in the job.

Note Layer names should not begin with a period as this translates into a hidden entity file.

CAM documents are defined using the Define CAM Documents interface.

• Select File > CAM... from the PowerPCB menu.



The Define CAM Documents window appears:

The following table lists the possible CAM document types and their corresponding layer types:

By default, many designers use layer 20 to draw the component outline. The translator searches this layer for drawings to determine the component outline. If not shapes are found on this layer, a fallback algorithm is used.

Fill Copper Pour OutlinesWhen translating a PowerPCB job, unhatched copper areas require processing, as they also do when generating CAM output. Copper pours that have not been flooded are exported to the PowerPCB-ASCII file as an area outline without the required various clearances that the Flood process creates to avoid shorting different nets.

CAM Document Type Trilogy 5000 Layer

Routing Signal Layer

Plane P/G Layer

Silkscreen Silk Screen Layer

Paste_Mask Solder Paste Layer

Solder_Mask Solder Mask Layer

Custom Documentation Layer

Assembly Documentation Layer

Drill_Drawing Documentation Layer

NC_Drill Not applicable

Verify_Photo Not applicable



Once a copper pour area is flood filled, it does not have to be reflooded. When reloading a saved job with flooded copper pour areas the areas will not display as filled in the PowerPCB window. However, they will contain all data necessary for translation, which means clearances are defined in the data.

Therefore, before creating the PowerPCB-ASCII file, all copper pours must have been flooded at least once. To do this, proceed as follows:

• Select Tools > Pour Manager... from the PowerPCB menu:

• In the Pour Manager dialog box, select the Flood tab (at the top). Check Flood All and click <Start>:

This action does not always fill all copper pours. Occasionally, if there are overlapping copper pour outlines, they will be left untouched. You must find these areas and manually fill them one by one. To do this, press <Shift+Click> on a copper pour outline, then right-click and select Flood from the pop-up menu that appears.

After filling all copper pour areas, you may proceed to export and translate the job.



Saving Split/Mixed Plane

Data

If your design uses split/mixed planes, they should be processed in a similar fashion to copper pours: that is, they must be filled in and then exported.

To do this, proceed as follows:

• Select Tools > Pour Manager... from the PowerPCB menu.

• In the Pour Manager dialog box, select the Plane Connect tab, and click <Select All> to process all split/mixed plane layers (see figure below):

• Click <Start> to fill in the split/mixed plane layers.

• Click <Setup...> to open the Preferences dialog box (see figure below):

• Under the heading Save to PCB File, select All Plane Data.

• Press <OK>.

You may now close the Pour Manager dialog box.



Create the ASCII FileUse the following procedure to generate an ASCII file:

• Start the PowerPCB application and load a design.

• Select File > Export... command.

• In the ASCII Output dialog box, select all sections by clicking <Select All>.

If the part type library contains attributes, click the Include Lib Attributes check-box:

Note Only layers that have the ‘Photo’ DOC_DEVICE_TYPE parameter will be translated to ODB++ when the file is imported by Enterprise 3000.

Direct Translation of Design into Enterprise 3000For users that have Valor Enterprise 3000 within their organization, and want to interface directly, the procedure is fully described in Document 0304 Mentor Graphics PowerPCB Interface Manual. Please refer to this manual for instructions.



Expedition


• Start the Expedition application and load a design.

• Select Output > ODBG Interface, as shown.




Output Options

Part numbers Checks if Part numbers are written out to the ODB++ file as stroked text.

Assemblylayers

Determines if top and bottom layers will be written to the ODB++ file. If used the layer is written out as documentation layers.

GeneratedSilkscreen

data

Select only when silkscreen data is generated by using the Silkscreen Generator. Otherwise, the regular silkscreen data will be used.

Drill drawinglayer

Determines if data on the drill drawing layer is output to the ODB++ file. If used, the layer will be created as a documentation layer.

User layers Determines if the mapping grid will be available to map user defined layers.

Definemapping

If you need to transfer component attributes to the generated file you can do so by defining special properties in the Parts Database. Any property that begins with ODB++ will be output as an attribute on each component that uses that part number.

For example, if in the Parts Database editor you added a property called ODB++.comp_type on part number 0001204, then the .comp_type property would be output for any components that used part number 0001204. The ODB++ prefix is stripped from the property name leaving the rest of the property to be used in the output file.



LaunchODB++

Convertor

This option must be selected for ODB++ creation.

OK Press <OK> to start the generation of ODB++.

The generated ODB++ file may be viewed with the Valor Universal Viewer (VUV) which may be downloaded from the Valor web pages at http://www.valor.com. It appears similar to the following window.


Help Opens the Help Browser window which explains the parameters of the translator in more detail.




Supermax ECADSupermax ECAD offers solutions for embedded component technology, MCM, hybrid, RF and advanced packaging design. Supermax offers the option of outputting ODB++ format.


• Start the Supermax application and load a design. Proceed in one of the following manners:

– In the CAM output dialog, specify ODB++ as an output operation.

– Click <Generate> to start the generation of ODB++ output.

—or—

– From the File menu select Export > ODB++.

– Click <Browse> to specify the destination directory of the generated ODB++ file.

– Click <Browse> to specify the location of the mapping file.

– Click <OK> to start the generation of ODB++ output.Click <Cancel> to exit the ODB++ generation dialog.Click <Help> to display the application help information.

When the ODB++ file has been successfully generated, the message at right appears.



Output

Mapfile Contains a layer mapping section and an attribute section for net and component properties. the mapping file follows the Supermax ECAD mapping file standard. The default map file is found in the $IPHOME/tables/odbmap directory.

LayerMappingSection

The layer section contains an ODB++ layer name and a Supermax ECAD layer name. Optional is context, type and side; that is:

If layer merge is wanted for some reason, the layers should be added to the layer section in the mapping file. For example, on layer signal1, if you want to add the layer called TopCoupon, then the layer TopCoupon should be added in the layer section as: signal1 TopCoupon.

Advisable ODB layer names, context, type and side:

where,

NN is electrical layer number seen from the top side of the design.

MM is drill layer number.

Possible ODB layer context values are: board, misc

Possible ODB layer types are: signal, plane, inner, mixed, solder_mask, solder_paste, silkscreen, drill, rout, document, components.

ODB++ [Layer]

SM ECAD Layer

ODB_context ODB_type ODB_side

ts TopSilk silkscreen document top

tref TopRefDes silkscreen document top

bs BotSilk silkscreen document bottom

bref BotRefDes silkscreen document bottom

Layer Type ODB Layer Name

Context Type Side

Signal layers sigNN Board Signal top/bottom

Plane layers sigNN Board Plane top/bottom

Inner layers sigNN Board Signal inner

Top solder paste

spt Board Solder paste top

Bottom solder paste

bts Board Solder paste bottom

Top solder mask

smt Board Solder mask top

Bottom solder mask

smb Board Solder mask bottom

Drill layers drlMM Board Drill none



Possible ODB layer sides are: top, bottom, inner, none.

AttributeMappingSection

The component attribute contains ODB component property name and Supermax ECAD component property name.

[Attribute]

The net attribute contains ODB net property name and Supermax ECAD net property name.

[Attribute]

For example, the net clock has a user property called Critical and carries the value of true. The ECAD_net_property_name should be changed to Critical and the ODB_net_property_name changed to .critical_net (i.e. the name to be exported). If there is no entry in the Mapfile matching the property, it is not output.

The generated ODB++ file may be viewed with the Valor Universal Viewer (VUV), which can be downloaded from the Valor web pages at http://www.valor.com. It appears similar to the window at right.

type comp

Name ODB_comp_property_name ECAD_component_property_name

type comp

Name ODB_net_property_name ECAD_net_property_name



Chapter 5 Zuken

Chapter 5 Zuken

Visula

Common Concepts for ODB++ OutputInput required for translation is an evaluated CADIF file which is generated automatically by the ODB++ output program. An evaluated cadif.file, contains all data necessary to create a job. It is generated from an ASCII file with the suffix .paf by activating an ifd script in the Visula Layout Editor.

An evaluated cadif.file always contains the following line:

(dataSet ARCHIVE ROUTE_RULES PLACE_RULES PIN_SIGNALS PAD_EVALROUTE_ISO)

A non-evaluated cadif.file does not contain the above line.

Partial CADIF FilesNon-evaluated CADIF files, termed Partial CADIF files, will be translated. However, the ODB++ data created is not intended to be used for full fabrication analysis.

Creation of ODB++ OutputThe ODB++ translator is supplied by Zuken and may be downloaded from the Zuken web pages. The generated ODB++ file may be viewed with the Valor Universal Viewer (VUV), which can be downloaded from the Valor web pages at http://www.valor.com.



Chapter 5 Zuken

Visula LayoutEditor

Use the following procedure to generate an ODB++ file:

• Start the Visula application and load a design.

• Select Job > Input/Output > Interfaces > Valor ODB++ Output.

Output path Specifies the directory in which the generated ODB++ file will be placed.

Output file Specifies the ODB++ filename.

• Press <OK> to perform translation.

Note When using the Visula “Interfaces” menu, the dialogs and default responses are determined by an ifd file that resides typically in $red_programs/cad_iface. Users may create their own ifd files and store them locally.When the Visula interface menu is accessed within the Layout application, the application will search for ifd files in the following sequence:

1.$red_programs/cad_iface

2.$red_data/cad_iface

3.$HOME/red_data/cad_iface


Chapter 5 Zuken

To change the default responses for ODB++ output, the valorodb.ifdfile that is supplied with the translator should be edited and copied to oneof the above locations.

A full description of the ifd mechanism may be found in the Visula on-linedocumentation manual - CAD/CAM Interfaces.

Direct Creation of ODB++/ODB++(X)


• Select Start > Programs > Valor > cadif to odb++ translator > Cadif2ODB.

• Command line: %VISULA_CADIF2ODB%\cadif2odb.

UNIX Type the following command: $VISULA_CADIF2ODB/cadif2odb.

After issuing one of the above commands, the CADIF to ODB++ window appears, as in the figure below. In this window, you set both basic and advanced Output Options.

Basic Options

Input PathSpecifies the location directory of the input file. Press to navigate.


The default directory for both Input and Output Path is the path to the current working directory.

Output JobName



Chapter 5 Zuken

Log file Path Specifies the path to the log file. By default creates a new log file for each translation. If the ‘Append’ checkbox is marked, log messages will be appended to the most recent log file.

Output Options

Remove EDAdata


Neutralizenets


GZIP Specifies whether to compress the ODB++ job. The ODB++ job is made up of several files describing the output. If activated, compression creates a single tar’ed and zipped file. The default is not to compress.


ShowODB++(X)

Settings



FULL - All ODB++ job data is represented. Job layers exported to XML are shaded green.



The Fabrication and the Assembly modes have several levels of XML output:




Chapter 5 Zuken















1 2 3 4 5 6 7 8 9 10 11 12


BOM/AVL




Drill/ Rout layers

Doc layers

Phys Nets


Inner layers

Non-DocMisc layers

Raw data files













Chapter 5 Zuken






Set DefaultValues


Export Mode - ASSY

Level - 6




ShowOptions


Help Opens the translator’s manual in PDF format.




Chapter 5 Zuken







Chapter 5 Zuken

Advanced Options

• Click to display Advanced Options.

Cadif SourceFile

Specify the source location of the CADIF file.

• PCB - searches in the pcb sub-directory.

• MCM - searches in the mcm sub-directory.

ExcludeLayers

Layers to be excluded from translation. Separate layer names with a semi-colon ‘;’.

Solder PasteLayers

Layers to be translated as solder-paste layers. A number of layers can be specified together either by name or logical ID, individually or by range, separated by semi-colon ‘;’.

TopSilkscreen

Layers

Layers to be translated as top silkscreen layers. A list of layer names can be specified together either by logical IDs or ranges of either, separated by semi-colon ‘;’.

ClearanceGap

The Clearance expansion (gap) to be used on P&G layers when the input file is not in full mode.


Chapter 5 Zuken

Use matrixfile

Provides a connection between CADIF britup files and ODB++ layers. Press to navigate. The Matrix file can make the connection between selected features in several CADIF layers to a single ODB++ layer, or on a one-to-one basis (CADIF to ODB++ layer), as below:

1. Selected features in several CADIF layers to a specific ODB++ layer (follows Visula WYSIWYG approach).

or

2. A single CADIF layer to its ODB++ counterpart.

An example of a Matrix file is below:

**************************************************************#ODB++ Zuken Cadif Interface#Matrix definition#Format - must be “1.0”FORMAT 1.0#directory#DIR <path>#location of britup files - may be skippedDIR /zj/britup_test/7#layers#LAYER CADIF <layer_name>#put here layer name from cadif file

#LAYER BRITUP <file_name> <type> <side>#File name may be absolute or relative to DIR#Type may be one of the following: sig, pg, mix, ss, sm, sp, doc#Long names for types are also allowable: signal, power_ground, mixed,#silk_screen, solder_mask, solder_paste, document#Leave name as “doc”, system will auto-detect (recommended)#Side may be top, bottom or auto; empty field means “auto”. System checks#layer side and type against internal definition and may change it accordingly.

LAYER BRITUP tal topLAYER BRITUP paste-top.bri sp topLAYER BRITUP resist-top.bri sm topLAYER CADIF L5LAYER CADIF F6LAYER BRITUP paste-bottom.bri sp bottomLAYER BRITUP ident-bottom.bri ss bottomLAYER BRITUP resist-bottom.bri sm bottom***************************************************************


Chapter 5 Zuken

Edit Invokes the Matrix File Editor.

Direct Translation of Design into Enterprise 3000For users that have Valor Enterprise 3000 within their organization, and want to interface directly, the procedure is fully described in Document 0305 Zuken Cadif Interface Manual. Please refer to this manual for instructions.


Chapter 5 Zuken

Board Designer (CR5000)

Common ConceptsIt is not possible to generate ODB++ output direct from the Board Designer (CR5000) application. ASCII files (described below) must be created from the Board Designer (CR5000) job and sent to manufacturers that use Valor Trilogy 5000.

A Board Designer archive design should be saved in two ASCII files: one file with extension .pcf or .pnf. and will have an associated footprint file with the extension .ftf located in the same directory. Board Designer has a flat file directory structure and all Board Designer files are created/saved in the same (job) directory.

PC Board ASCII File (PCF) - ASCII file describing the contents of the PC Board Database. It must be accompanied by one ftf file.

Panel ASCII File (PNF) - ASCII file describing the contents of the Panel Database.

Footprint ASCII File (FTF) - ASCII file describing the contents of the Footprint Library.

Package ASCII File (PKF) (Optional) - ASCII file describing packages used for component types.

A pcf or pnf file, together with a footprint file, contains the minimal required data to create a job.

The following steps should be used to generate the ASCII files:

• Use the standard Board Designer Input/Output module to generate ASCII data. If this module does not exist, the following script may be used to convert Board Designer jobs to ASCII. The script assumes a C shell environment running in Windows. The script location’s path must be defined using the PATH environment variable. It is invoked in C shell.

Script

bd2val.csh The following c-shell script is used to extract ASCII files from binary files in the BD system:

#!/bin/csh

######################################### BD ASCII

if ( -f $1.pcb ) then

pcout.sh -r $1.pcb -o $1.pcfpartback.sh -r $1.pcb -o $1.prfpkgback.sh -r $1.pcb -o $1.pkfftout.sh -r $1.pcb -o $1.ftfmrout.sh -r $1.mrl -o $1.mrf


Chapter 5 Zuken

else if ( -f $1.pnl ) then

pnout.sh -r $1.pnl -o $1.pnfpartback.sh -r $1.pnl -o $1.prfpkgback.sh -r $1.pnl -o $1.pkfftout.sh -r $1.pnl -o $1.ftfmrout.sh -r $1.mrl -o $1.mrf

endif

Direct Translation of Design into Enterprise 3000For users that have Valor Enterprise 3000 within their organization, and want to interface directly, the procedure is fully described in Document 0307, Zuken BD Interface manual. Please refer to this manual for instructions.


Chapter 5 Zuken

PWS (CR3000)

Common ConceptsIt is not possible to generate ODB++ output direct from the PWS (CR3000) application. ASCII files (described below) must be created from the PWS (CR3000) job and sent to manufacturers that use Valor Trilogy 5000.

The databases for CR-3000 PWS are binary files built on a foundation of object-oriented databases. The contents of these databases can be viewed by outputting information in ASCII format. The PWS databases can be built up by preparing ASCII files in a prescribed format.

The following three PWS ASCII files are needed for complete translation of a design, CR-3000 PWS utilities should be used to generate all required ASCII files.

Mandatory Technology file (BSF) - defines design specifications such as layers, via tables, aperture table, units and other miscellaneous data.

Component Shape Catalog File (MDF) - defines top and bottom component artworks. To differentiate between the top and bottom artworks, either a t or a b is respectively added to the artwork number.

PC Board Shape File (UDF) - defines component and feature artworks not belonging to nets. In some cases, features listed in the WDF file (see below) may also appear in this file (UDF). The translator deletes UDF duplicate features.

Optional Additional PWS ASCII file types can be created and will be used by the translation software if available.

Wiring Specifications By Signal (CCB, CCF, ECF, WDF or DRN) - defines netlist at the reference designator level. The file search sequence first checks the CCB file. If it exists, it looks no further.

If CCB does not exist, the search sequence checks in the following sequence:

1.CCF file

2.ECF file

3.WDF file

4.DRN (DRC Netlist File)

Wiring Shape File (WDF) - defines all conductive features belonging to nets (pads, traces, surfaces, etc.).

PWS to ODB++ Layer Mapping File (PRM) - lists layers, which will be created in the ODB++ job, and their attributes.

The.prm file maps PWS layers and Nouns to their respective layers in the resulting ODB++ job. A Noun defines the type of feature(s) or objects found in layer.

If the.prm file is missing, default layer definitions are extracted from the.bsf file.

Translation may complete successfully with only a partial list of files, and some information may be partial or missing. However, such a generated ODB++ file may not be suitable for Fabrication analysis.


Chapter 5 Zuken

Direct Translation of Design into Enterprise 3000For users that have Valor Enterprise 3000 within their organization, and want to interface directly, the procedure is fully described in Document 0306, Zuken PWS Interface manual. Please refer to this manual for instructions.


Chapter 5 Zuken

Cadstar


• Start the Cadstar application and load a design.

• Select File > Export.

• Select ODB++, as shown.

Output Options

ODB++ Generates full ODB++ output.


ODB++(X)Partial

Restricts the XML output to only the component and pad data on the outer layers. Physical nets and internal layer items are not included in the output.

Remove EDAdata


NeutralizeNets



Chapter 5 Zuken

CompressJob

Compresses the ODB++ job into one single zipped file describing the output. If ‘unzipped’, the ODB++ job is made up of several files describing the output.

• Press <OK> to start the generation of ODB++.


Direct Translation of Design into Enterprise 3000For users that have Valor Enterprise 3000 within their organization, and want to interface directly, the procedure is fully described in Document 0305, Zuken Cadif Interface manual. Please refer to this manual for instructions.



Chapter 6 Altium

Chapter 6 Altium

P-CAD

Common Concepts for ODB++ OutputThe P-CAD 2002 ODB++ output provides configuration options that allow the user to select which data items are to be included in the ODB++ output. Certain layers may be used in conjunction with other layers. For example, a dimension layer may be output with a Notes layer.

Although it is possible to select board layers to be included in the ODB++ output, it is recommended that all layers be output to ensure there is no missing data. When generating an ODB++ database, a directory tree structure is created with files for all appropriate design data.


• Start the P-CAD application and load a design.

• Select File > Export > ODB++, as shown.


Chapter 6 Altium

• Select the Board and Drill Layers to export. Click on a layer's checkbox to toggle its inclusion.

If required, specify which layers will be included with the targeted layer for output by right-clicking on Included Layers as shown, and then clicking on the desired associated layer(s).

It is possible to specify whether to output Pads, Vias, Refdes, Type, Value, Title, and no mounting hole copper. This is done by right-clicking on the setting under Layer Settings and clicking on True or False. The example at the right shows pads output selection. However, it is recommended that all data be included in ODB++ output.

NC Drill information is output as layers. Each layer contains the name of the start and end board layers for each drill range. The drill layers are generated automatically based on the user pad and via styles. None of the settings for the NC Drill layers can be changed. The NC Drill information relies on the existence of all the signal/plane layers in the ODB++ database. You need to specify which of the NC Drill layers to output.


Chapter 6 Altium

View Log FileUpon

Completion(Optional)

• Shows the translator log. All program messages are written to this file.

OutputLocation

• Specifies the destination directory for the generated ODB++ data. To change this path, click <Output Location>. From the Save As dialog that appears, browse to and select the particular directory in which you wish the exported data to be stored. The current output path will be updated accordingly (the selected directory must exist).

Generate • Generates the output file.The ODB++ file is saved in the Output Location chosen.

Note For ease of communication, it is recommended that the generated ODB++ design directory be sent to manufacturers as a compressed archive file (such as tar, zip format).


Direct Translation of Design into Enterprise 3000For users that have Valor Enterprise 3000 within their organization, and want to interface directly, the procedure is fully described in Document 0308, Altium P-CAD ASCII Interface manual. Please refer to this manual for instructions.



Chapter 6 Altium

Protel

Common Concepts for ODB++ OutputThe complete database for this application is contained in one binary file. A Protel archive design should be saved in one ASCII file with the extension pcb.

Creation of ODB++ OutputODB++ output can be generated by two different procedures, the second procedure gives the user more control over the ODB++ output, but can only be used when the design data (PCB + Schematics) is in one project.

Procedure 1

• Start the Protel application and load a project.

• Select Project > Project Options.

• Select the ‘Options’ tab and in the ‘Output Options’ group box, deselect ‘Open outputs after compile’, as shown.

• Press <OK> to close this dialog.

• Select File > Fabrication Outputs > ODB++ Files, as shown.


Chapter 6 Altium


• Select the layers to be included in the ODB++ translation.

• Select the Mechanical Layer(s) to be included in the ODB++ translation.

UnconnectedPads

Select the ‘Include unconnected mid-layer pads’ option.


Chapter 6 Altium

GenerateDRC Rules

Deselect the ‘Generate DRC Rules export file (.RUL)’ option (it is not required for ODB++ export.)

Plot Layers Select layers for ODB ++ export.

All - Selects all layers for ODB++ export

None - Excludes all layers from ODB++ export

• Press <OK> to start the generation of ODB++.

The generated ODB++ file will be saved in the ODB directory within the Project Outputs folder. It may be viewed with the Valor Universal Viewer (VUV), which can be downloaded from the Valor web pages at http://www.valor.com. It appears similar to the following window.

Procedure 2

• Start the Protel application and load a design.

• Select File > New > Output Job File, as shown. This creates a new Output Job file and places it under the Output Job Files branch of the project tree.



Chapter 6 Altium

• Select the newly created Job from the Project Tree. A dialog similar to the following graphic appears. The Fabrication Output section contains all fabrication formats that are supported.


Chapter 6 Altium

• If ODB++ Files is not listed, select Edit > Add Fabrication Outputs > ODB++ Files, as shown.

• Check that the Data Source is the PCB document that you want to generate the Outputs for. If not, click the Data Source cell and select the PCB document that you want to use.


Chapter 6 Altium

• Double-click on the ODB++ Files Fabrication Outputs option.


• Select the layers to be included in the ODB++ translation.

• Select the Mechanical Layer(s) to be included in the ODB++ translation

UnconnectedPads

Select the ‘Include unconnected mid-layer pads’ option.

GenerateDRC Rules

Deselect the ‘Generate DRC Rules export file (.RUL)’ option (it is not required for ODB++ export.)

Plot Layers Select layers for ODB ++ export.

All - Selects all layers for ODB++ export

None - Excludes all layers from ODB++ export

• Press <OK> to close the dialog.


Chapter 6 Altium

• Right-click the Job from the Project Tree and select Save from the popup menu, as shown. This saves the configuration that you have built for future use on this project.

• Right-click on the ODB++ Files Fabrication Outputs option, and select ‘Run Output Generator...’. This generates the ODB++ data. The ODB++ file is saved in the ODB directory within the Project Outputs folder.


Chapter 6 Altium


Direct Translation of Design into Enterprise 3000For users that have Valor Enterprise 3000 within their organization, and want to interface directly, the procedure is fully described in Document 0309, Altium Protel Interface manual. Please refer to this manual for instructions.




Chapter 7 Number One Systems


Easy-PC for WindowsEasy-PC is the industry standard at entry level shrink wrapped market for PCB design products under US$1,000. It provides a complete front-to-back design solution of Schematics and PCB design editors, along with library create tools, a supplied library and full manufacturing outputs. As a modular system, it is highly scaleable with additional cost options and design capacity.


• Start the Easy-PC for Windows application and load a design.

• Select Output > ODB++ Export.

• Select Compressed to have all data compressed into one .tgz file.Otherwise, data is output in structured folder format.

• Click Browse to designate a location for the folder structure or the compressed file.

Output All data is compressed into one single compressed archive describing the output. If the compressed option is not selected, select Browse to designate a location where a structured folder for the various files and subfolders that describe the output will be created.

• Click OK to start the generation of ODB++.



The generated ODB++ file may be viewed with the Valor Universal Viewer (VUV), which can be downloaded from the Valor web pages at http://www.valor.com. It appears similar to the window at right.



Chapter 8 Pulsonix

Chapter 8 Pulsonix

PulsonixThe Pulsonix product sets the new standard in the mid-range PCB design market. A sophisticated toolset is enhanced with one of the easiest to use graphical user interfaces available. This product is ready to use by both the casual and professional user, with almost no training required. A full product of integrated Schematic Capture, PCB layout editor, graphical library creation suite and a powerful manufacturing output feature make Pulsonix stand out.


• Start the Pulsonix application and load a design.

• Select Output > ODB++.

• Select Compressed to have all data compressed into one .tgz file.Otherwise, data is output in structured folder format.

• Click Browse to designate a location for the folder structure or the compressed file.

OutputAll data is compressed into one single compressed archive describing the output. If the compressed option is not selected, select Browse to designate a location where a structured folder for the various files and subfolders that describe the output will be created.

• Click OK to start the generation of ODB++.


Chapter 8 Pulsonix

The generated ODB++ file may be viewed with the Valor Universal Viewer (VUV), which can be downloaded from the Valor web pages at http://www.valor.com. It appears similar to the following window. Other viewers may require non-compressed format.



Chapter 9 Valor

Chapter 9 Valor

Enterprise 3000

Creation of ODB++ OutputUse the following procedure to export a job from an internal ODB++ job database, either as ODB++ compatible data or in ODB++(X) (XML format):

• Start the Enterprise 3000 application.

• Select File > Export from the Engineering Toolkit, as shown:

Output Options• Select ODB++ Job to output an ODB++ file, or ODB++(X) to output in XML

(eXtended Markup Language) format.

ODB++ JobThe following window appears:


Chapter 9 Valor

Job Name Type name of job to be exported. Press to navigate.

Path Type the path to the directory in which the job is to be saved. Press to navigate.

Mode Select a mode.

Tar gzip (.tgz) - Produces a compressed Tape Archived (tar) set of files

Tar - Produces a combined set of files (compressed or uncompressed)

Directory - Outputs using the same directory structure as the job. Files are copied without compression.

Tar gzip is the preferred option for optimum data transfer. A full description of the output modes can be found in Doc. 0102, Engineering Toolkit.

• Press <OK> to start the generation of ODB++, and close the dialog.

• Press <Apply> to start the generation of ODB++, but leave the dialog open for further output.

Overwrite Specifies whether to overwrite existing files of the same name in the defined location.

Yes - Overwrites existing files

No - Does not overwrite existing files

ODB++(X) The following window appears:

Job Name Type name of job to be exported. Press to navigate.

Path Type the path to the directory in which the job is to be saved. Press to navigate.

Overwrite Specifies whether to overwrite existing files of the same name in the defined location.


Chapter 9 Valor

Yes - Overwrites existing files

No - Does not overwrite existing files

Units Specifies units of measurement used in output file.

Metric (mm) - millimeter


Placed CompOnly

Specifies whether to output all components including components having .comp_ignore attribute.

Yes - Outputs only components that have been placedNo - Outputs all components

Mode Select mode to output data:

Full - Exports all the information in the job

Partial - Exports only component and pad data on outer layers (identical to Assy level 6).

FAB - Exports fabrication-related data. The Level field opens; select 1 for the maximum information to be exported up to Level 4 for the minimum information to be exported. The precise data to be exported are displayed in the right panel of the popup.

ASSY - Exports assembly-related data. The Level field opens; select 1 for the maximum information to be exported up to Level 6 for the minimum information to be exported. The precise data to be exported are displayed in the right panel of the popup.

Note The Mode, Level and Layers fields are interdependent. That is, selecting one value in one of the parameters may affect the selection of the other. In all of the above options you specify in the Layers field which layers to export.

Level (1 to 6) - 1 = highest, 6=lowest. This option only appears when Mode = Fab (Level = 1-4) or Mode = Assy (Level = 1-6). It indicates the amount of data to export. Select a level and the data to be exported are automatically marked in the right panel.

Layers Specifies the layers to export.

Default - System determines the layers

All - Exports all layers.

None - No layers are exported

Non-selectable, for information only. Selected data types depend on your choice of Mode.


Chapter 9 Valor

Select - Select for export each layer individually (by clicking on the checkbox). After choosing ‘Select’, all layers will become selected. Deselect any layer you do not want to export.

SuppressData

Specifies data is to be suppressed.

No - Exports all data

Yes - Does not export blank data.

Table showing associations between Mode and Level with data to export

Description of Output TableOrig BOM/AVL files - text files as received by Enterprise 3000.

BOM/AVL - after translation as BOM entity.





Raw data files - (RAW Data) all data not exported as XML.

1 2 3 4 5 6 7 8 9 10 11 12


BOM/AVL




Drill/ Rout layers

Doc layers

Phys Nets


Inner layers

Non-DocMisc layers

Raw data files

Full Y Y Y Y Y Y Y Y Y Y Y Y

FAB 1 N N Y Y Y Y Y Y Y Y Y Y

2 N N N Y Y Y Y Y Y Y Y Y

3 N N N Y Y Y Y Y Y Y Y N

4 N N N Y Y Y Y Y Y Y N N

ASSY 1 Y Y Y Y Y Y Y Y Y Y Y N

2 Y Y Y Y Y Y Y Y Y Y N N

3 Y Y Y Y Y Y Y Y Y N N N

4 N Y Y Y Y Y Y Y N N N N

5 N Y Y Y Y Y Y N N N N N

6 N Y Y Y N N N N N N N N


Appendix A Thermal Model


Depending on the PCB application, to generate accurate board data, you are required to use of a Thermal Model to explicitly define these shapes.

Structure of a Thermal Model FileThe Thermal Model File includes a units definition followed by any number of models. Lines preceded by a ‘#’ character are treated as comments and ignored.

.units < inch | mm > - The units definition specifies the measurement units that will be used for the models. Legal values are inch and mm.

.model <name> - Each model begins with the model directive. The name is limited to 64 characters that may include letters, digits, and the following symbols:

For an example of a Thermal Model file, see “Sample Thermal Model File” on page 89.

BNF (Backus-Naur Form) of RulesThe model directive is followed by a sequence of rules.

<rule> ::= <condition> : <derivation>

If the condition is met, then the thermal shape definition described in the derivation is used for the pad. The first match is used.

<condition> ::= <type> { <equation> }<type> ::= PIN | VIA | geometry_name | 'geometry_name'<equation> ::= [D|C] ['<' | '<=' | '=' | '>' | '>='] <value>

The padstack can be compared by its type, either PIN or VIA, or by its padstack name. The padstack name may be enclosed in quotes to accommodate padstacks named PIN or VIA.

The padstack can also be compared based on drill size (represented by the ‘D’ in the equation), or by clearance size (represented by the ‘C’ in the equation).

<derivation> ::= NULL | '<sym_name>' | <set_values><sym_name> ::= any ODB++ standard or semi-standard name

Name Symbol

dash -

underscore _

period .

plus +



The shape can be defined directly by providing the symbol name; or the parameters for the symbol can be derived based on the drill and clearance sizes (represented by ‘D’ and ‘C’, respectively).

The ‘NULL’ shape can be used to produce direct connects.

<set_values> ::= <id> <od> <tie> <num_ties> <angle><oshape> <ishape> <style>

<id>::=<diam_value><od>::=<diam_value><diam_value>::=[ C | D ] [ "+" | "-" ] [<value>]

The inner diameter is represented by <id> and the outer diameter is represented by <od>.

<tie> ::= <value><num_ties> ::= <value>

<tie> is the size of the tie and <num_ties> is the number of ties.

<angle> ::= <value>

<angle> represents the start angle for the first tie in degrees.

<oshape> ::= R | S | C<ishape> ::= R | S | C<style> ::= R | S

• <oshape> represents the outer shape. It can be either Round (‘R’), Square (‘S’) or the same shape as the clearance (‘C’).

• <ishape> represents the inner shape. It can be either Round (‘R’), Square (‘S’) or the same shape as the clearance (‘C’).

• <style> can be Rounded (‘R’) or Squared (‘S’).

Sample Thermal Model File.units inch.model allegro_model# direct replacement of symbols

# replace the padflash named "TH05" with a round clearance of #5 mils. TH05 : 'r5'

# replace the padflash named "T165X145X20X45" with a square thermal# with an outer diameter of 165 mils, inner diameter of 145 mils# with four ties each of 20 mils, first starting at 45 degrees.T165X145X20X45 : 'ths165x145x45x4x20'

# replace the padflash named "5MIL" with a direct connection5MIL : 'null'

# calculated values

# Place a direct connect for all VIA padsVIA : NULL



# For pins with a clearance less than or equal to 45 mils# place a rounded thermal with outer diameter the size of the clearance# inner diameter 20 mils smaller, # 4 ties of 20 mil starting at 45 degrees# outer and inner diameters shaped as the clearancePIN C<=45 : C C-20 15 4 45 C C R




In Cadence Allegro, the following extract files are used.

Note To locate all the files, the file names must be specified correctly. In all extract files, the text <job_name> should be replaced with the name of the current job.

Note For CAD layers to be present in the generated ODB++, you need to create the films for those layers.

comps_<job_name>.out

Contains the outline shape of the components. In ODB++, components must each be defined as a single closed shape, therefore the PLACE_BOUND outlines are typically used.

films_<job_name>.out

Contains the artwork information from Allegro.

geoms_<job_name>.out

Graphical data describing feature placement.

layers_<job_name>.out

Provides information on the order of the physical layers.

nets_<job_name>.out

This file is optional and is not required for translation. It contains two types of information on nets: classes & properties. Allegro declares 3 types of class: spacing, physical & electrical. Every net may connect/have any combination of triplet of spacing, physical & electrical classes, if any. The classes are defined in the technology file. It also contains some net properties, such as impedance.

pads_<job_name>.out

Contains information on the padstacks in the job.

Note The Allegro .brd file currently does not contain information on the PADSHAPES. Therefore, the names that appear in the Padflash field, must be defined with the Thermal Model.

pins_<job_name>.out

Contains information on pins and vias.

Note The translator reads the pins in order of appearance. Therefore, the extract pins file must be sorted in ascending order according to pin number. This is performed automatically when invoked from Cadence Allegro.



props_<job_name>.out

Contains additional component property information. This file is optional. This was originally added so that users could read additional component properties directly into ODB++. Users requiring the extraction of additional properties can manually add them to the view file.

tech_<job_name>.out

This file is an optional ASCII file that contains Allegro/APD parameter and constraint data. By using the tech file, a user can apply a uniform set of design rules and constraints to designs that share the same set of design rules and constraints.

• Tech files defines:

• User Units

• Drawing Parameters

• Layout CrossSection Parameters

• Spacing Constraints

• Physical Constraints

• Electrical Constraints

• User Property Definitions

Part of the spacing constraints are the clearances rules.

Data Exchange - 0312 - Prime Elettronica · The Valor Universal Viewer (VUV), a freely distributed...

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