CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 10: Digital System Design...
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CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 10: Digital System Design Chapter 10
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Transcript of CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 10: Digital System Design...
CS/EE 3700 : Fundamentals of Digital System Design
Chris J. Myers
Lecture 10: Digital System Design
Chapter 10
Digital System Design
• Digital system consists of two parts:– Datapath circuit – used to store, manipulate,
and transfer date.– Control circuit – controls the operation of the
datapath. Usually its built using an FSM.
Figure 10.1 A flip-flop with an enable input
D Q
Q
Q R
Clock
E
0 1
Figure 10.2 VHDL code for a D flip-flop with an enable input
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY rege ISPORT ( R, Resetn, E, Clock : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC ) ;END rege ;
ARCHITECTURE Behavior OF rege ISBEGIN
PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THENQ <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THENIF E = '1' THEN
Q <= R ;ELSE
Q <= Q ;END IF ;
END IF ;END PROCESS ;
END Behavior ;
Figure 10.3 VHDL code for an n-bit register with an enable input
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY regne ISGENERIC ( N : INTEGER := 4 ) ;PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;E, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regne ;
ARCHITECTURE Behavior OF regne ISBEGIN
PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THENQ <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THENIF E = '1' THEN
Q <= R ;END IF ;
END IF ;END PROCESS ;
END Behavior ;
Figure 10.4a Code for a right-to-left shift register with an enable input
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
-- right-to-left shift register with parallel load and enableENTITY shiftlne IS
GENERIC ( N : INTEGER := 4 ) ;PORT( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
L, E, w : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END shiftlne ;
ARCHITECTURE Behavior OF shiftlne ISBEGIN
PROCESSBEGIN
… con’t
Figure 10.4b Code for a right-to-left shift register with an enable input (con’t)
… con’t
WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF E = '1' THEN
IF L = '1' THENQ <= R ;
ELSEQ(0) <= w ;Genbits: FOR i IN 1 TO N-1 LOOP
Q(i) <= Q(i-1) ;END LOOP ;
END IF ;END IF ;
END PROCESS ;END Behavior ;
Figure 10.5a Component declaration statements for building blocks
LIBRARY ieee ;USE ieee.std_logic_1164.all ;PACKAGE components IS
-- 2-to-1 multiplexerCOMPONENT mux2to1
PORT ( w0, w1 : IN STD_LOGIC ;s : IN STD_LOGIC ;f : OUT STD_LOGIC ) ;
END COMPONENT ;-- D flip-flop with 2-to-1 multiplexer connected to DCOMPONENT muxdff
PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC ) ;
END COMPONENT ;
-- n-bit register with enableCOMPONENT regne
GENERIC ( N : INTEGER := 4 ) ;PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;E, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END COMPONENT ;
… con’t
Figure 10.5b Component declaration statements for building blocks (con’t)
… con’t
-- n-bit right-to-left shift register with parallel load and enableCOMPONENT shiftlne
GENERIC ( N : INTEGER := 4 ) ;PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
L, E, w : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END COMPONENT ;
-- n-bit left-to-right shift register with parallel load and enableCOMPONENT shiftrne
GENERIC ( N : INTEGER := 4 ) ;PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
L, E, w : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END COMPONENT ;
… con’t
Figure 10.5c Component declaration statements for building blocks (con’t)
… con’t
-- up-counter that counts from 0 to modulus-1COMPONENT upcount
GENERIC ( modulus : INTEGER := 8 ) ;PORT ( Resetn : IN STD_LOGIC ;
Clock, E, L : IN STD_LOGIC ;R : IN INTEGER RANGE 0 TO modulus-1 ;Q : BUFFER INTEGER RANGE 0 TO modulus-1 ) ;
END COMPONENT ;
-- down-counter that counts from modulus-1 down to 0COMPONENT downcnt
GENERIC ( modulus : INTEGER := 8 ) ;PORT ( Clock, E, L : IN STD_LOGIC ;
Q : BUFFER INTEGER RANGE 0 TO modulus-1 ) ;END COMPONENT ;
END components ;
Static Random Access Memory
• SRAM is used when a large amount of data needs to be stored.
• SRAM block is 2-dimensional array of SRAM cells where each cell stores 1-bit.
• To store m elements of n-bits, the aspect ratio of the SRAM array would be m n.
Figure 10.6 An SRAM cell
Sel
DataData
Figure 10.7 A 2 x 2 array of SRAM cells
Sel 1
Sel 0
Data0 Data1
Figure 10.8 A 2m x n SRAM block
Sel 2
Sel 1
Sel 0
Sel 2 m 1 ”
Read
Write
d 0 d n 1 – d n 2 –
q 0 q n 1 – q n 2 –
m -to-2
m deco
der
Address
a 0
a 1
a m 1 –
Data outputs
Data inputs
Figure 10.9 Pseudo-code for the bit counter
B = 0 ; while A 0 do
if a 0 = 1 thenB = B + 1 ;
End if;Right-shift A ;
End while;
Figure 10.10 ASM chart for the bit counter
Done
B B 1 +
B 0
s
Load A
a 0
Reset
S3
0
1
0
1
0
1 s
S1
S2
1
0
A 0 = ?
Shift right A
Figure 10.11 Data path for the bit counter
L
E Counter
w
L E
Shift
LB
EBLA
EA
0
Clock
0
B z a 0
Data
n
A
n
log 2 n
log 2 n
Figure 10.12 ASM chart for the bit counter control circuit
EA
EB z
LB EB
s
EA
a 0
Reset
S3
0
1
0
1
0
1 s LA
S2
S1
0
1
0
1
Done
Figure 10.13a VHDL code for the bit-counting circuit
LIBRARY ieee ;USE ieee.std_logic_1164.all ;LIBRARY work ;USE work.components.shiftrne ;
ENTITY bitcount ISPORT( Clock, Resetn : IN STD_LOGIC ;
LA, s : IN STD_LOGIC ;Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;B : BUFFER INTEGER RANGE 0 to 8 ;Done : OUT STD_LOGIC ) ;
END bitcount ;
ARCHITECTURE Behavior OF bitcount ISTYPE State_type IS ( S1, S2, S3 ) ;SIGNAL y : State_type ;SIGNAL A : STD_LOGIC_VECTOR(7 DOWNTO 0) ;SIGNAL z, EA, LB, EB, low : STD_LOGIC ;
BEGINFSM_transitions: PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THENy <= S1 ;
… con’t
Figure 10.13b VHDL code for the bit-counting circuit (con’t)
ELSIF (Clock'EVENT AND Clock = '1') THENCASE y IS
WHEN S1 =>IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;END IF ;
END PROCESS ;FSM_outputs: PROCESS ( y, s, A(0), z )BEGIN
EA <= '0' ; LB <= '0' ; EB <= '0' ; Done <= '0' ;CASE y IS
WHEN S1 =>LB <= '1' ; EB <= '1' ;IF s = '0' AND LA = '1' THEN EA <= '1' ; ELSE EA <= '0' ; END IF ;
WHEN S2 =>EA <= '1' ;IF A(0) = '1' THEN EB <= '1' ; ELSE EB <= '0' ; END IF ;
… con’t
Figure 10.13c VHDL code for the bit-counting circuit (con’t)
WHEN S3 =>Done <= '1' ;
END CASE ;END PROCESS ;-- The datapath circuit is described belowupcount: PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THENB <= 0 ;
ELSIF (Clock'EVENT AND Clock = '1') THENIF EB = '1' THEN
IF LB = '1' THENB <= 0 ;
ELSEB <= B + 1 ;
END IF ;END IF ;
END IF;END PROCESS;low <= '0' ;ShiftA: shiftrne GENERIC MAP ( N => 8 )
PORT MAP ( Data, LA, EA, low, Clock, A ) ;z <= '1' WHEN A = "00000000" ELSE '0' ;
END Behavior ;
Figure 10.14 Simulation results for the bit-counting circuit
Figure 10.15 An algorithm for multiplication
(a) Manual method
(b) Pseudo-code
Multiplicand11
Product
Multiplier10
01
11
1 1 0 11011
00001011
01 0 0 1 1 1 1
Binary
1311
1313
143
Decimal
P = 0 ; for i = 0 to n 1 do
if b i
= 1 thenP = P + A ;
end if; Left-shift A ;
end for;
–
Figure 10.16 ASM chart for the multiplier
Shift left A , Shift right B Done
P P A + B 0 = ?
P 0
s
Load A
b 0
Reset
S3
0
1
0
1
0 1
s
S1
S2
1
0
Load B
Figure 10.17 Datapath circuit for the multiplierE
L E
L E
0
Data
A
LA
EA
A
Clo
ck
P
Data
P
Regis
ter
EP
Su
m
0
z
B
b 0
Data
B
LB
EB
+
2n
n
n
Sh
ift-
left
regis
ter
Sh
ift-
rig
ht
regis
tern
n
2n
2n
Pse
l1
0
2n
2n
Figure 10.18 ASM chart for the multiplier control circuitEP
z b 0
Rese
t
S3
0
1
0
1s
0
1
Done
Pse
l0
=EP
s0
1
S1 S2
LA EA
LB EB
0
1
0
1
Pse
l1
=EA
EB
Figure 10.19a VHDL code for the multiplier circuit
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;USE work.components.all ;
ENTITY multiply ISGENERIC ( N : INTEGER := 8; NN : INTEGER := 16 ) ;PORT ( Clock : IN STD_LOGIC ;
Resetn : IN STD_LOGIC ;LA, LB, s : IN STD_LOGIC ;DataA : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;DataB : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;P : BUFFER STD_LOGIC_VECTOR(NN-1 DOWNTO 0) ;Done : OUT STD_LOGIC ) ;
END multiply ;
ARCHITECTURE Behavior OF multiply ISTYPE State_type IS ( S1, S2, S3 ) ;SIGNAL y : State_type ;SIGNAL Psel, z, EA, EB, EP, Zero : STD_LOGIC ;SIGNAL B, N_Zeros : STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;SIGNAL A, Ain, DataP, Sum : STD_LOGIC_VECTOR(NN-1 DOWNTO 0) ;
BEGIN… con’t
Figure 10.19b VHDL code for the multiplier circuit (con’t)
FSM_transitions: PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THENy <= S1 ;
ELSIF (Clock'EVENT AND Clock = '1') THENCASE y IS
WHEN S1 =>IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;END IF ;
END PROCESS ;FSM_outputs: PROCESS ( y, s, LA, LB, B(0) )BEGIN
EP <= '0' ; EA <= '0' ; EB <= '0' ; Done <= '0' ; Psel <= '0';CASE y IS
WHEN S1 =>EP <= '1' ;IF s = '0' AND LA = '1' THEN EA <= '1' ; ELSE EA <= '0' ; END IF ;IF s = '0' AND LB = '1' THEN EB <= '1' ;
… con’t
Figure 10.19c VHDL code for the multiplier circuit (con’t)
ELSE EB <= '0' ; END IF ;WHEN S2 =>
EA <= '1' ; EB <= '1' ; Psel <= '1' ;IF B(0) = '1' THEN EP <= '1' ; ELSE EP <= '0' ; END IF ;
WHEN S3 =>Done <= '1' ;
END CASE ;END PROCESS ;-- Define the datapath circuitZero <= '0' ; N_Zeros <= (OTHERS => '0' ) ;Ain <= N_Zeros & DataA ;ShiftA: shiftlne GENERIC MAP ( N => NN )
PORT MAP ( Ain, LA, EA, Zero, Clock, A ) ;ShiftB: shiftrne GENERIC MAP ( N => N )
PORT MAP ( DataB, LB, EB, Zero, Clock, B ) ;z <= '1' WHEN B = N_Zeros ELSE '0' ;Sum <= A + P ;-- Define the 2n 2-to-1 multiplexers for DataPGenMUX: FOR i IN 0 TO NN-1 GENERATE
Muxi: mux2to1 PORT MAP ( Zero, Sum(i), Psel, DataP(i) ) ;END GENERATE;RegP: regne GENERIC MAP ( N => NN )
PORT MAP ( DataP, Resetn, EP, Clock, P ) ;END Behavior ;
Figure 10.20 Simulation results for the multiplier circuit
Figure 10.21 An algorithm for division
R = 0 ; for i = 0 to n 1 do
Left-shift RA ; if R B then
q i = 1 ; R = R B ;
elseq i = 0 ;
end if; end for;
(c) Pseudo-code
9 14095045
5
15
100
1010
011001001
00001111
100100101
10000100111101001101
Q
AB
R(a) An example using decimal numbers
(b) Using binary numbers
–
–
Figure 10.22 ASM chart for the divider
R
B
?
R
0
C
n
1
–
s 0
1
S1
S2 0
Load
ALo
ad
B
Shift
left
R||
A
C
C
1
”
Shift
0 into
QS
hift
1 into
QR
R
B
–
C
0
=
?
1
1
0
S3
Rese
t
Done
S4
0
1
s
Figure 10.23 Datapath circuit for the divider
ELE L
E
DataB
LRER
EQ
Clock
Q
Register
EB
0
R
DataALA
EA
+
Ecout cin 1
B
w
Rsel
n
Left-shiftregister
n
Left-shiftregister
n n
nn
nn
Left-shiftregister
an 1” A
w
01
Figure 10.24 ASM chart for the divider control circuit
Rse
l0
=LR
, ER
, LC
, EC
s0
1
S1
S2
Done
s
EQ
, R
sel
1=
EC
LR, ER
10
S4
S3
Rese
t
LAEA
ER
, EA
c out
z
1
01
0
10
Figure 10.25 An example of division using n = 8 clock cycles
Load A, B 0 0 0 1
0 0 1 1
0 1 2 3 1
0 0
0 0 0
4 5 6 0 0 7
1 0 0 0 1 1 0 0
Clock cycle
0 0 8
0
A/Q
0 1 1 0
1 1 0 0
0 0 0
0 0 0
0 0 0 0
1 0 0 0
0 0 0 0
0 0 0
0 0 0
0 1 1 1
0 0 0 0 0 0 1 1 1
0 0 0 0 1 1 1 1
rr0 R
0 0 0 0
0 0 0 0
0 0 0
0 0 0
0 0
0 0 0 0 0 0 0 0
0 0 0
0 0 0 0
0 0 0 0
0 1 1
1 0 0
1 0 0 1
0 0 0 1
0 0 1 0
0 0 0
0 0 0
0 0 1 1
0 1 0 0 0 1 1 0 0
0 0 0 0 1 0 1 0
0 0 0 0 0 0 0 0 0 0
100011001001 A B
Shift left
Subtract, Q 0 1
Shift left, Q 0 0 Shift left, Q 0 0 Shift left, Q 0 0
Subtract, Q 0 1 Subtract, Q 0 1 Subtract, Q 0 1
Shift left, Q 0 0
Figure 10.26 An example of division using n = 8 clock cycles
Rse
l0
=
LCEC
ER
s
0
1
S1
S2
LR
1
0
Rese
t
EA
, ER
0
c out
z
1
0
ER
ER
0 E
AR
sel
1
=
LR
LAEA
EC
1
0
Done
s
S3
1
0
Figure 10.27 Datapath circuit for the enhanced divider
E
L
E L
E
Dat
aB
LR
ER
Clo
ck
Reg
iste
r
EB
0
R
Dat
aA
LA
EA
+
c out
c in1
B
w
Rse
ln
Lef
t-sh
ift
regi
ster n
Lef
t-sh
ift
regi
stern
n n n
n
q n 1 –
Q
0 1
D
Q
Q
ER
0 0 1 0
n 1
– n
r n 2 –
r 0
w
n n
rr0
Figure 10.28a VHDL code for the divider circuit
LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all ;USE work.components.all ;ENTITY divider IS
GENERIC ( N : INTEGER := 8 ) ;PORT ( Clock : IN STD_LOGIC ;
Resetn : IN STD_LOGIC ;s, LA, EB : IN STD_LOGIC ;DataA : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;DataB : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;R, Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Done : OUT STD_LOGIC ) ;
END divider ;
ARCHITECTURE Behavior OF divider ISTYPE State_type IS ( S1, S2, S3 ) ;SIGNAL y : State_type ;SIGNAL Zero, Cout, z : STD_LOGIC ;SIGNAL EA, Rsel, LR, ER, ER0, LC, EC, R0 : STD_LOGIC ;SIGNAL A, B, DataR : STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;SIGNAL Sum : STD_LOGIC_VECTOR(N DOWNTO 0) ; -- adder outputsSIGNAL Count : INTEGER RANGE 0 TO N-1 ;
… con’t
Figure 10.28b VHDL code for the divider circuit (con’t)
BEGINFSM_transitions: PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THEN y <= S1 ;ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y ISWHEN S1 =>
IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ;WHEN S2 =>
IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ;WHEN S3 =>
IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ;END CASE ;
END IF ;END PROCESS ;FSM_outputs: PROCESS ( s, y, Cout, z )BEGIN
LR <= '0' ; ER <= '0' ; ER0 <= '0' ;LC <= '0' ; EC <= '0' ; EA <= '0' ; Done <= '0' ;Rsel <= '0' ;CASE y IS
WHEN S1 =>… con’t
Figure 10.28c VHDL code for the divider circuit (con’t)
LC <= '1' ; EC <= '1' ; ER <= '1' ; IF s = '0' THEN
LR <= '1' ; IF LA = '1' THEN EA <= '1' ; ELSE EA <= '0' ; END IF ;
ELSEEA <= '1' ; ER0 <= '1' ;
END IF ;WHEN S2 =>
Rsel <= '1' ; ER <= '1' ; ER0 <= '1' ; EA <= '1' ;IF Cout = '1' THEN LR <= '1' ; ELSE LR <= '0' ; END IF ;IF z = '0' THEN EC <= '1' ; ELSE EC <= '0' ; END IF ;
WHEN S3 =>Done <= '1' ;
END CASE ;END PROCESS ;-- define the datapath circuitZero <= '0' ;RegB: regne GENERIC MAP ( N => N )
PORT MAP ( DataB, Resetn, EB, Clock, B ) ;ShiftR: shiftlne GENERIC MAP ( N => N )
PORT MAP ( DataR, LR, ER, R0, Clock, R ) ;
… con’t
Figure 10.28d VHDL code for the divider circuit (con’t)
FF_R0: muxdff PORT MAP ( Zero, A(N-1), ER0, Clock, R0 ) ;ShiftA: shiftlne GENERIC MAP ( N => N )
PORT MAP ( DataA, LA, EA, Cout, Clock, A ) ;Q <= A ;Counter: downcnt GENERIC MAP ( modulus => N )
PORT MAP ( Clock, EC, LC, Count ) ;z <= '1' WHEN Count = 0 ELSE '0' ;
Sum <= R & R0 + (NOT B +1) ;Cout <= Sum(N) ;DataR <= (OTHERS => '0') WHEN Rsel = '0' ELSE Sum ;
END Behavior ;
Figure 10.29 Simulation results for the divider circuit
Figure 10.30 An algorithm for finding the mean of k numbers
Sum
= 0
; fo
r i =
k
1 do
wn
to0
doSu
m =
Sum
+R
;
i
end
for;
M =
Sum
÷ k
;
(a)
Pse
udo-
code
(b)
AS
M c
hart
Sum
0
C
k 1
–
, s
0
1
S1
S2
Don
e
s
Res
et
1
0
Sum
S
um
R i
+
S4
C
0 =
?
M
Sum
k
C
C
1 –
0
1 S
3
Loa
d re
gist
ers
–
Figure 10.31 Datapath circuit for the mean operation
Figure 10.32 ASM chart for the control circuit
Figure 10.33 Schematic of the mean circuit with an SRAM block
Figure 10.34 Simulation results for the mean circuit using SRAM
Figure 10.35 Pseudo-code for the sort operation
for i = 0 to k 2 doA = R i ; for j = i + 1 to k 1 do
B = R j ; if B < A then
R i = B ; R j = A ; A = R i ;
end if ; end for;
end for;
–
–
Figure 10.36 ASM chart for the sort operation
B
A
<
?
C i
0
s 0
1
S1
S2
Don
es
Res
et
A
R i
C j
C i
,
C i
C i
1 +
S4
S5
0
1
S3 C
j C
j 1
+
B
R j
R j
A
R i
B
A
R i
C j
k 1
– =
?
C j
C j
1 +
C i
k 2
– =
?
0
1
0
1
Loa
d re
gist
ers
0
1
S9
S7
S6
S8
Figure 10.37 A part of the datapath circuit for the sort operation
E E E E
Clock
DataIn
WrInit
Rin 3 Rin 2 Rin 1 Rin 0
E E Bin Ain
DataOut
Rd
ABData
Imux
Bout
BltA
1 0 A B
0 1
RData
R 0 R 1 R 2 R 3
0 1 2 3
ABmux n
n
n
Figure 10.38 A part of the datapath circuit for the sort operation
L
E
L
E
1 0
1 0
k 2 – =
k – 1 =
LJ
EJ
LI
EI
2-to-4 decoder
WrInit
Wr
RAdd
Clock
Csel
Int
Imux
2
C i C j
z i
z j Cmux
Rin 0
Rin 1
Rin 2
Rin 3
0
2
2
2
2
2
Counter Counter
R
Q Q
R
w 0 w 1
En
y 0
y 1
y 2
y 3
2
Figure 10.39 ASM chart for the control circuitC
sel
0 =
In
t 1
=
Ain
,
,
Cse
l0
=
In
t 1
=
W
rB
out
Cse
l1
=
In
t 1
=
W
rA
out
Bin
Cse
l1
=
In
t 1
=
s 0
1
S1
S2
Done
s
Rese
t
S4
S5
0
1
S3
1
0
1
S9
S7
S6
S8
LIEI
Int
0
=
Int
1
=
Cse
l0
=
A
in LJ
EJ
EJ
Blt
AEJ
EI
0
1
0
z j z i
Figure 10.40a VHDL code for the sort operation
LIBRARY ieee;USE ieee.std_logic_1164.all;USE work.components.all ;
ENTITY sort ISGENERIC ( N : INTEGER := 4 ) ;PORT ( Clock, Resetn : IN STD_LOGIC ;
s, WrInit, Rd : IN STD_LOGIC ;DataIn : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;RAdd : IN INTEGER RANGE 0 TO 3 ;DataOut : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Done : BUFFER STD_LOGIC ) ;
END sort ;
ARCHITECTURE Behavior OF sort ISTYPE State_type IS ( S1, S2, S3, S4, S5, S6, S7, S8, S9 ) ;SIGNAL y : State_type ;SIGNAL Ci, Cj : INTEGER RANGE 0 TO 3 ;SIGNAL Rin : STD_LOGIC_VECTOR(3 DOWNTO 0) ;TYPE RegArray IS ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;SIGNAL R : RegArray ;SIGNAL RData, ABMux : STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;SIGNAL Int, Csel, Wr, BltA : STD_LOGIC ;SIGNAL CMux, IMux : INTEGER RANGE 0 TO 3 ;
Figure 10.40b VHDL code for the sort operation (con’t)
SIGNAL Ain, Bin, Aout, Bout : STD_LOGIC ;SIGNAL LI, LJ, EI, EJ, zi, zj : STD_LOGIC ;SIGNAL Zero : INTEGER RANGE 3 DOWNTO 0 ; -- parallel data for Ci = 0SIGNAL A, B, ABData : STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
BEGINFSM_transitions: PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THENy <= S1 ;
ELSIF (Clock'EVENT AND Clock = '1') THENCASE y IS
WHEN S1 => IF S = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 => y <= S3 ;WHEN S3 => y <= S4 ;WHEN S4 => y <= S5 ;WHEN S5 => IF BltA = '1' THEN y <= S6 ; ELSE y <= S8 ; END IF ;WHEN S6 => y <= S7 ;WHEN S7 => y <= S8 ;WHEN S8 =>
IF zj = '0' THEN y <= S4 ;ELSIF zi = '0' THEN y <= S2 ;ELSE y <= S9 ;END IF ;
Figure 10.40c VHDL code for the sort operation (con’t)
WHEN S9 => IF s = '1' THEN y <= S9 ; ELSE y <= S1 ; END IF ;END CASE ;
END IF ;END PROCESS ;-- define the outputs generated by the FSMInt <= '0' WHEN y = S1 ELSE '1' ;Done <= '1' WHEN y = S9 ELSE '0' ;FSM_outputs: PROCESS ( y, zi, zj )BEGIN
LI <= '0' ; LJ <= '0' ; EI <= '0' ; EJ <= '0' ; Csel <= '0' ;Wr <= '0'; Ain <= '0' ; Bin <= '0' ; Aout <= '0' ; Bout <= '0' ;CASE y IS
WHEN S1 => LI <= '1' ; EI <= '1' ;WHEN S2 => Ain <= '1' ; LJ <= '1' ; EJ <= '1' ;WHEN S3 => EJ <= '1' ;WHEN S4 => Bin <= '1' ; Csel <= '1' ;WHEN S5 => -- no outputs asserted in this stateWHEN S6 => Csel <= '1' ; Wr <= '1' ; Aout <= '1' ;WHEN S7 => Wr <= '1' ; Bout <= '1' ;WHEN S8 => Ain <= '1' ;
IF zj = '0' THENEJ <= '1' ;
ELSEEJ <= '0' ;
Figure 10.40d VHDL code for the sort operation (con’t)
IF zi = '0' THENEI <= '1' ;
ELSEEI <= '0' ;
END IF;END IF ;
WHEN S9 => -- Done is assigned 1 by conditional signal assignmentEND CASE ;
END PROCESS ;-- define the datapath circuitZero <= 0 ;GenReg: FOR i IN 0 TO 3 GENERATE
Reg: regne GENERIC MAP ( N => N )PORT MAP ( RData, Resetn, Rin(i), Clock, R(i) ) ;
END GENERATE ;RegA: regne GENERIC MAP ( N => N )
PORT MAP ( ABData, Resetn, Ain, Clock, A ) ;RegB: regne GENERIC MAP ( N => N )
PORT MAP ( ABData, Resetn, Bin, Clock, B ) ;BltA <= '1' WHEN B < A ELSE '0' ;ABMux <= A WHEN Bout = '0' ELSE B ;RData <= ABMux WHEN WrInit = '0' ELSE DataIn ;OuterLoop: upcount GENERIC MAP ( modulus => 4 )
PORT MAP ( Resetn, Clock, EI, LI, Zero, Ci ) ;
Figure 10.40e VHDL code for the sort operation (con’t)
InnerLoop: upcount GENERIC MAP ( modulus => 4 )PORT MAP ( Resetn, Clock, EJ, LJ, Ci, Cj ) ;
CMux <= Ci WHEN Csel = '0' ELSE Cj ;IMux <= Cmux WHEN Int = '1' ELSE Radd ;WITH IMux Select
ABData <= R(0) WHEN 0,R(1) WHEN 1,R(2) WHEN 2,R(3) WHEN OTHERS ;
RinDec: PROCESS ( WrInit, Wr, IMux )BEGIN
IF (WrInit OR Wr) = '1' THENCASE IMux IS
WHEN 0 => Rin <= "0001" ;WHEN 1 => Rin <= "0010" ;WHEN 2 => Rin <= "0100" ;WHEN OTHERS => Rin <= "1000" ;
END CASE ;ELSE Rin <= "0000" ; END IF ;
END PROCESS ;Zi <= '1' WHEN Ci = 2 ELSE '0' ;Zj <= '1' WHEN Cj = 3 ELSE '0' ;DataOut <= (OTHERS => 'Z') WHEN Rd = '0' ELSE ABData ;
END Behavior ;
Figure 10.41a Simulation results for the sort operation
Figure 10.41b Simulation results for the sort operation
Figure 10.42 Using tri-state buffers in the datapath circuit
E E E E
Clock
DataIn
WrInit
Rin3Rin2Rin1Rin0
E EBinAin
A B
BltABout
Aout
DataOut
Rd
Rout3Rout2Rout1Rout0
n
n
n n n n
n
nn
Figure 10.43 Clock enable circuit
D Q
Q
Data
Clock
E
Figure 10.11 Data path for the bit counter
L
E Counter
w
L E
Shift
LB
EBLA
EA
0
Clock
0
B z a 0
Data
n
A
n
log 2 n
log 2 n
Figure 10.44 An H tree clock distribution network
Clock
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
Figure 10.45 A flip-flop in an integrated circuit
D Q
Data
Clock
Chip package pin
A
B
t Clock
t Data
Out
t od
Figure 10.46 Flip-flop timing in a chip
Data
Clock
A
3ns
4.5ns
1.5ns
B
Asynchronous Inputs to FFs
• Inputs generated asynchronously may violate setup and hold times of flip-flops.
• FF may take on a value between 0 and 1.• This condition is called a metastable state.• There is no guarantee of how long the
circuit will persist in this state.• Care must be taken to reduce the probability
of having synchronization failure.
Figure 10.47 Asynchronous inputs
D Q
Q
Data
Clock
(asynchronous)D Q
Q
Data(synchronous)
Figure 10.48 Switch debouncing circuit
Data
S
R
V DD
R
V DD
R
(a) Single-pole single-throw switch
Data
V DD
R
(b) Single-pole double-throw switch with a basic SR latch
