CSE 231 Lab Report

COURSE INSTRUCTOR: DR. ABUL L. HAQUE

LAB INSTRUCTOR: SWARNA RAHMAN

LAB REPORT

SHATADRU SHIKTA1311169042

2 | P a g e

EXPERIMENT NUMBER EXPERIMENT NAME PAGE NUMBER1 Introduction to different

Digital IC3

2 Introduction to combinational logic

7

3 Construction of adders and subtractors using

basic logic gates.

11

4 Design a combinational logic that will act as an adder if control bit is ‘0’

and as a subtractor if control bit is ‘1’

18

5 Design a BCD adder that will add two BCD numbers and the sum

will be also in BCD

21

6 Introduction to Multiplexers

24

7 Implementation of Demultiplexers

27

8 design of Flip-flop using basic gates

30

SHATADRU SHIKTA 1311169042

CONTENTS

3 | P a g e

EXPERIMENT NAME:

Introduction to different Digital IC

OBJECTIVE :

To be introduced to different Digital IC’s; Test digital IC’s of different types of the same 74 series and to obtain appropriate results.

INSTRUMENTS:

1. Trainer Board2. IC 7400,7402,7404,7408,7432,74863. Wires for Connection

PROCEDURE:

1. Place the IC on IC trainer kit.2. Connect Vcc and GND respective pins of IC with trainer board.3. Connect the inputs with the switches and the outputs with the LEDs.4. Apply various combinations of inputs and observe the results.

DATA SHEET AND CALCULATIONS:

IC 7400: NAND F= AB

A B F0 0 10 1 11 0 11 1 0

IC 7402: NOR F= A+B

IC 7404: NOT F= A


A B F0 0 10 1 01 0 01 1 0

4 | P a g e

IC 7408: AND F= AB

IC 7432: OR F= A+B


A F0 11 0

A B F0 0 00 1 01 0 01 1 1

A B F0 0 00 1 11 0 11 1 1

5 | P a g e

IC 7486: XOR F= A⊕B


A B F0 0 00 1 11 0 11 1 0

6 | P a g e

REPORT:

How can I make a three input AND/OR/XOR gate with a two input AND/OR/XOR gate?

Solution: Connect A and B to pin 1 and 2 respectively. The output from 3 is then connected to pin 4 and C is connected to pin 5. The output from 6 gives (A.B.C) with

7408, (A+B+C) with 7432 and (A⊕B⊕C) with 7486.

Is it possible to make a 3 input NAND/NOR gate with a 2 input NAND/NOR?

Soultion: No. It is not possible since, For NAND, after connecting A and B to pin 1 and 2 respectively. C is then connected to pin 4 and 5. Next the output from 3 and 6 are connected to pin 9 and ten respectively and the output from pin 8 gives (A+B+C).

COMMENTS:

While working with the IC’s, one must be careful while handling it, since the pins are very soft and maligned. The wiring should be carefully done since any misalignment might result in a short circuit which might result in harming the board and/or the IC’s. the connections between the IC’c Vcc and GND should be carefully established.


7 | P a g e

EXPERIMENT NAME:

Introduction to combinational logic.

OBJECTIVE :

To be introduced to combinational logic and implement the following functions:

f=AB+BC’+CA and f= (AB+B).(C+A).(AC+B)

INSTRUMENTS:

1. Trainer Board2. 7486, IC 7432, IC 7408, IC 74003. Wires for Connection

PROCEDURE:

JOB 1: f=AB+BC’+CA

1. Note the output logic for all combination of inputs.2. Now fill up the truth table for the function.

3. Simplify the function in POS and in SOP form using K-map.

0 0 0 10 1 1 1

f=AC+BC’4. Draw logic diagram to implement the functions


A

B

C

A B C f0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 11 1 0 11 1 1 1

8 | P a g e

5. Select ICs and implement the logic diagram on trainer board.6. Check the output with truth table.

JOB 2 : f= (AB+B).(C+A).(AC+B)


A B C f0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

3. Simplify the function in POS and in SOP form using K-map.

0 0 1 00 0 1 1

f=AB+BC

4. Draw logic diagram to implement the functions


AC

B

9 | P a g e

5. Select ICs and implement the logic diagram on trainer board.

REPORT:

First, the IC’s were installed in the trainer kit and the Vcc and GND’s were connected accordingly. The inputs were connected then according to the circuit diagrams and the outputs were matched repectively accordingly to the truth table given.

COMMENTS:

Keeping aside the general precuations for the IC’s, the inputs and outputs should be connected respectively according to the pin number for accurate results. Any misconnection in pin number might cause a short circuit causing heating of the IC’s resulting in wrong results.


10 | P a g e

EXPERIMENT NAME:

Construction of adders and subtractors using basic logic gates.

OBJECTIVE :

Construct the basic adder and subtractor circuit with common logic gates and test their operability.

INSTRUMENTS:

1. Trainer Board2. 7486, IC 7432, IC 7408, IC 74003. Wires for Connection

PROCEDURE:

JOB 1: Half adder


A B CarryC

SumS

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

3. Determine the Boolean function for half adder.



11 | P a g e


JOB 2 : Half subtractor


A B BorrowB

DifferenceD

0 0 0 0

0 1 1 1

1 0 0 1

1 1 0 0

3. Determine the Boolean function for half adder. B=A’B



12 | P a g e


JOB 3 : Full adder


A B C SumS

CarryC

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 2 0

1 0 0 1 1

1 0 1 2 0

1 1 0 2 0

1 1 1 3 1

3. Determine the Boolean function for half adder.



13 | P a g e


JOB 4 : Full Subtractor


A B C BorrowB

DifferenceD

0 0 0 0 00 0 1 1 10 1 0 1 10 1 1 1 01 0 0 0 11 0 1 0 01 1 0 0 01 1 1 1 1


14 | P a g e

3. Determine the Boolean function for full subtractor.



REPORT:

The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely,

0 + 0 = 00 + 1 = 11 + 0 = 1

1 + 1 = 102

The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum. For half adder, the input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits. For Full adder, The three input bits include two significant bits and a previous carry bit.

The arithmetic operation, subtraction of two binary digits has four possible elementary operations, namely,


15 | P a g e

0 - 0 = 0 0 - 1 = 1 (with 1 borrow)

1 - 0 = 11 - 1 = 0

In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.For half subtractor, The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits. For Full subtractor, The three input bits include two significant bits and a previous borrow bit.


COMMENTS:



16 | P a g e

EXPERIMENT NAME:

Design a combinational logic that will act as an adder if control bit is ‘0’ and as a subtractor if control bit is ‘1’.

OBJECTIVE :

Addition of two 4-bit binary numbers can be easily done by using a four bit binary adder IC (7483/74283)taking the 2’s complement of the subtrahend and then adding that with the minuend can do subtraction of two 4-bit binary numbers.

INSTRUMENTS:

1. Trainer Board

2. IC 7486, IC 7432, IC 7408, IC 74833. Wires for Connection

PROCEDURE:

1. Collect the required ICs and implement the circuit.

2. Note the output logic for different inputs.


17 | P a g e

A B M S1001 0010 1 001110111 1000 0 011111111 1111 0 111101111 1111 1 000001111 1011 1 001000110 0011 1 000111010 1001 0 100110111 1001 0 100000111 1001 1 X

REPORT:

Why have we used XOR gate in this circuit?

Sol: If the mode value is 0, there is no change to the second input, thus resulting in the addition of the second and first input. But, when the mode value is 1, there is a change in value in the second output and it becomes the complement, thus resulting in the subtraction of the second value from the first value.

COMMENTS:



18 | P a g e

EXPERIMENT NAME:

Design a BCD adder that will add two BCD numbers and the sum will be also in BCD.

OBJECTIVE :

A BCD adder can be designed by considering the arithmetic addition of two decimal digits in BCD, together with a possible carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 9+9+1=19this can be designed with a 4-bit binary adder together with a correction logic circuit.

INSTRUMENTS:

1. Trainer Board

2. IC 7432, IC 7408, IC 74833. Wires for Connection

PROCEDURE:

1. Collect the required ICs and implement the circuit.

2. Note the output logic for different inputs.

Binary Sum BCD SumK Z8 Z4 Z2 Z1 C S8 S4 S2 S10 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 0 0 10 0 0 1 0 0 0 0 1 00 0 0 1 1 0 0 0 1 1


19 | P a g e

0 0 1 0 0 0 0 1 0 00 0 1 0 1 0 0 1 0 10 0 1 1 0 0 0 1 1 00 0 1 1 1 0 0 1 1 10 1 0 0 0 0 1 0 0 00 1 0 0 1 0 1 0 0 10 1 0 1 0 1 0 0 0 00 1 0 1 1 1 0 0 0 10 1 1 0 0 1 0 0 1 00 1 1 0 1 1 0 0 1 10 1 1 1 0 1 0 1 0 00 1 1 1 1 1 0 1 0 11 0 0 0 0 1 0 1 1 01 0 0 0 1 1 0 1 1 11 0 0 1 0 1 1 0 0 01 0 0 1 1 1 1 0 0 1

REPORT:


COMMENTS:



20 | P a g e

EXPERIMENT NAME:

Introduction to Multiplexers.

OBJECTIVE :

Multiplexers are the most important attributions of digital circuitry in communication hardware. These digital switches enable us to achieve the communication network we have today. In this experiment, the students will have to construct MUX (multiplexers) with simple logic gates.

INSTRUMENTS:

1. Trainer Board

2. IC 7404, IC 7411, IC 74323. Wires for Connection

PROCEDURE:

1. Write the truth table for 4:1 MUX.S1 S0 Y

0 0 I0

0 1 I11 0 I21 1 I3

S1 S0 I0 I1 I2 I30 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

2. Write the Boolean function for the output logic.F= S1’S0’ I0 + S1’S0 I1+ S1S0’ I2+ S1S0 I3

3. Draw the logic diagram to implement the Boolean function.


21 | P a g e

4. Select the required ICs.5. Observe and note the output logic for all combination of inputs.

REPORT:

A multiplexer or mux is a combinational circuits that selects several analog or digital input signals and forwards the selected input into a single output line. A multiplexer of 2n inputs has n selected lines, are used to select which input line to send to the output. First, the IC’s were installed in the trainer kit and the Vcc and GND’s were connected accordingly. The inputs were connected then according to the circuit diagrams and the outputs were matched repectively accordingly to the truth table given by alternating the inputs I0 ,I1 ,I2 ,I3.

COMMENTS:



22 | P a g e


23 | P a g e

EXPERIMENT NAME:

Implementation of Demultiplexers.

OBJECTIVE :

A Demultiplexer does the opposite function of multiplexers. It has one input line and 2n output lines, where n is the number of selection bits. The output channel can be selected depending on the combination of selector bits.

INSTRUMENTS:

1. Trainer Board

2. IC 7404, IC 74113. Wires for Connection

PROCEDURE:

1) Write the truth table for 1:4 DE-MUX.S1 S0 I0 I1 I2 I3

0 0 Y 0 0 0

0 1 0 Y 0 0

1 0 0 0 Y 0

1 1 0 0 0 Y

2) Write the Boolean function for the output logic.S1 S0 Y I0 I1 I2 I30 0 0 0 0 0 00 0 1 1 0 0 00 1 0 0 0 0 00 1 1 0 1 0 01 0 0 0 0 0 01 0 1 0 0 1 01 1 0 0 0 0 01 1 1 0 0 0 1

3) Draw the logic diagram to implement the Boolean function.


24 | P a g e

4) Select the required ICs.5) Observe and note the output logic for all combination of inputs.

REPORT:

The demultiplexer takes one single input data line and then switches it to any one of a number of individual output lines one at a time. The demultiplexer converts a serial data signal at the input to a parallel data at its output lines as shown below.First, the IC’s were installed in the trainer kit and the Vcc and GND’s were connected accordingly. The inputs were connected then according to the circuit diagrams and the outputs were matched repectively accordingly to the truth table given.

COMMENTS:



25 | P a g e


26 | P a g e

EXPERIMENT NAME:

Design of Flip-flop using basic gates.

OBJECTIVE :

The memory elements in a sequential circuit are called flip-flops. A flip-flop circuit has two outputs, one for the normal value and one for the complement value of the stored bit. Binary information can enter a flip-flop in a variety of ways and gives rise to different types of flip-flops.

INSTRUMENTS:

1. Trainer Board

2. IC 7400, IC 74023. Wires for Connection

PROCEDURE:

Job -1: Design of an SR Flip-flop using NOR gates only.1. Draw the logic diagram to implement SR Flip-flop.

2. Fill up the Table with different combination of inputs.

S R Q Q’1 0 1 00 0 1 00 1 0 10 0 0 11 1 1 0

3. Observe the condition for which no change or race conditions arise.

Job -2: Design of an SR Flip-flop using NAND gates only.1. Draw the logic diagram to implement SR Flip-flop.


27 | P a g e


S R Q Q’1 0 0 11 1 0 10 1 1 01 1 1 01 1 1 1

3. Observe the condition for which no change or race conditions arise.

Job -3: Design of a J-K Flip-flop using AND and NOR gates only.1) Draw the logic diagram to implement J-K Flip-flop.

2) Fill up the Table with different combination of inputs.

J K Q Q’1 0 1 00 0 1 00 1 0 10 0 0 11 1 1 01 0 1 0


28 | P a g e

1 1 0 1

Job -4: Design of a T Flip-flop from a J-K Flip-flop.1. Draw the logic diagram to implement T Flip-flop.


T Q0 01 10 11 0

Job -5: Design of a D Flip-flop from a J-K Flip-flop..1. Draw the logic diagram to implement D Flip-flop.


D Q0 01 10 01 1


29 | P a g e

REPORT:

SR: The clocked SR flip-flop consists of a basic NOR flip-flop and two AND gates. The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R input values. When the clock pulse goes to 1, information from the S and R inputs passes through to the basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0. When the pulse is removed, the state of the flip-flop is indeterminate, ie., either state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse.

D: The D flip-flop is the edge-triggered variant of the transparent latch. On the rising edge of the clock, the output is given the value of the D input at that moment. The output can be only changed at the clock edge, and if the input changes at other times, the output will be unaffected.

JK: The JK flip-flop is a simple enhancement of the SR flip-flop where the state J=K=1 is not forbidden. It works just like a SR flip-flop where J is serving as set input and K serving as reset. The only difference is that for the formerly “forbidden” combination J=K=1 this flip-flop now performs an action: it inverts its state. As the behavior of the JK flip-flop is completely predictable under all conditions, this is the preferred type of flip-flop for most logic circuit designs. But there is still a problem i.e. both the outputs are same when one tests the circuit practically. This is because of the internal toggling on every propagation elapse completion. The main remedy is going for master-slave jk flip-flop,this flip-flop overrides the self(internal) recurring toggling through the pulsed clocking feature incorporated.

T: The T or "toggle" flip-flop changes its output on each clock edge, giving an output which is half the frequency of the signal to the T input.

COMMENTS:



CSE 231 Lab Report

Documents

Transcript of CSE 231 Lab Report